Preliminary Technical Data 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR® Differential ADC in MSOP/QFN AD7693 FEATURES APPLICATION DIAGRAM APPLICATIONS Battery-powered equipment Data acquisitions Seismic data acquisition systems DVMs Instrumentation Medical instruments +2.5V TO +5V +5V IN+ REF VDD VIO SDI IN– SDO +1.8V TO VDD 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) SCK ±10V, ±5V, ... GND CNV ADA4941-1 AD7693 -001 16-bit resolution with no missing codes Throughput: 500 kSPS INL: +/-0.25 LSB typical, ±0.65 LSB max (±10 ppm of FSR) Dynamic range: 96.5 dB typical @ 500 kSPS SINAD: 96 dB typical @ 1 kHz, REF = 5V THD: −120 dB typical @ 1 kHz. REF = 5V True differential analog input range: ±VREF 0 V to VREF with VREF up to VDD on both inputs No pipeline delay Single-supply 5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs and busy indicator Power dissipation 4 mW @ 5 V/100 kSPS 40 μW @ 5 V/1 kSPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN 1 (LFCSP) (SOT-23 size) Pin-for-pin compatible with the AD7687, AD7688 and 18-bit AD7690 and AD7691 Figure 2. Table 1. MSOP, QFN1 (LFCSP)/SOT-23 14-/16-/18-Bit PulSAR ADC 100 kSPS 250 kSPS AD7691 16-Bit True Differential AD7684 AD7687 16-Bit Pseudo Differential/ Unipolar 14-Bit AD7683 AD7680 AD7685 AD7694 AD7940 AD7942 Type 18-Bit 1 400 kSPS to 500 kSPS AD7690 AD7688 AD7693 AD7686 AD7946 ADC Driver ADA4941-1 ADA4841-x ADA4941-1 ADA4841-x ADA4841-x ADA4841-x QFN package in development. Contact sales for samples and availability. GENERAL DESCRIPTION The AD7693 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. On the CNV rising edge, it samples the voltage difference between the IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage, VDD. Its power scales linearly with throughput. The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply. Figure 1. Integral Nonlinearity vs. Code The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN1 (LFCSP) with operation specified from −40°C to +85°C. 1 QFN package in development. Contact sales for samples and availability. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7693 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram........................................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply............................................................................... 15 Revision History ............................................................................... 2 Supplying the ADC from the Reference.................................. 16 Specifications..................................................................................... 3 Digital Interface.......................................................................... 16 Timing Specifications....................................................................... 5 CS Mode 3-Wire, No BUSY Indicator..................................... 17 Absolute Maximum Ratings............................................................ 6 CS Mode 3-Wire with BUSY Indicator ................................... 18 ESD Caution.................................................................................. 6 CS Mode 4-Wire, No BUSY Indicator..................................... 19 Pin Configurations and Function Descriptions ........................... 7 CS Mode 4-Wire with BUSY Indicator ................................... 20 Terminology ...................................................................................... 8 Chain Mode, NO BUSY Indicator ........................................... 21 Typical Performance Characteristics ............................................. 9 Chain Mode with BUSY Indicator........................................... 22 Theory of Operation ...................................................................... 12 Application Hints ........................................................................... 23 Circuit Information.................................................................... 12 Layout .......................................................................................... 23 Converter Operation.................................................................. 12 Evaluating the AD7693’s Performance.................................... 23 Typical Connection Diagram ................................................... 13 Outline Dimensions ....................................................................... 24 Analog Inputs.............................................................................. 14 Ordering Guide .......................................................................... 24 REVISION HISTORY Rev. PrB | Page 2 of 24 Preliminary Technical Data AD7693 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25°C Input Impedance 1 THROUGHPUT Conversion Rate Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error 3 Gain Error Temperature Drift Zero Error3 Zero Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Intermodulation Distortion 5 Conditions/Comments Min 18 IN+ − (IN−) IN+, IN− IN+, IN− fIN = 250 kHz Acquisition phase −VREF −0.1 0 Typ VREF/2 65 1 0 Full-scale step 16 −0.65 −0.5 REF = VDD = 5 V -30 VREF = 5 V fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 5 V 96 95.5 95.5 1 Unit Bits +VREF VREF + 0.1 VREF/2 + 0.1 V V V dB nA 500 400 kSPS ns ±1 ±1 Bits LSB LSB 2 LSB LSB ppm/°C LSB ppm/°C ppm 96.5 96 93 −120 −120 96 TBD dB 4 dB dB dB dB dB dB ±0.25 ±0.2 0.16 ±1.5 ±0.5 −10 VDD = 5 V ± 5% Max +0.65 +0.5 +30 +10 See the Analog Inputs section. LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV. See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 5 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale. 2 3 Rev. PrB | Page 3 of 24 AD7693 Preliminary Technical Data VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay 1 VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 2, 3 Power Dissipation Energy per Conversion TEMPERATURE RANGE 4 Specified Performance Conditions/Comments Min Typ 0.5 Max Unit VDD + 0.3 500 kSPS, REF = 5 V 100 V μA VDD = 5V 9 2.5 MHz ns −0.3 0.7 × VIO −1 −1 +0.3 × VIO VIO + 0.3 +1 +1 V V μA μA 0.4 V V 5.5 VDD + 0.3 VDD + 0.3 50 V V V nA μW mW mW nJ/sample +85 °C Serial 16 bits twos complement ISINK = +500 μA ISOURCE = −500 μA VIO − 0.3 Specified performance Specified performance 4. 5 2.3 1.8 VDD and VIO = 5 V, 25°C 100 SPS throughput 100 kSPS throughput 500 kSPS throughput TMIN to TMAX 1 5 5 15 50 −40 1 Conversion results available immediately after completed conversion. With all digital inputs forced to VIO or GND as required. 3 During acquisition phase. 4 Contact an Analog Devices sales representative for extended temperature range. 2 Rev. PrB | Page 4 of 24 Preliminary Technical Data AD7693 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 4.5 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY Indicator) VIO Above 4.5 V VIO Above 2.3 V 1 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK tSCKL tSCKH tHSDO tDSDO Min 0.5 400 2.0 10 15 Typ Max 1.6 17 18 19 20 7 7 4 Unit μs ns μs ns ns ns ns ns ns ns ns ns 14 15 16 17 ns ns ns ns 15 18 22 25 ns ns ns ns ns ns ns ns ns ns 15 26 ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI See Figure 3 and Figure 4 for load conditions. Rev. PrB | Page 5 of 24 15 0 5 10 3 4 AD7693 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, 1 IN−1 REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance (MSOP-10) θJC Thermal Impedance (MSOP-10) Lead Temperature Range 1 Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 200°C/W 44°C/W JEDEC J-STD-20 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. See the Analog Inputs section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500µA IOL 1.4V TO SDO CL 50pF IOH -002 500µA Figure 3. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 -003 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Rev. PrB | Page 6 of 24 Preliminary Technical Data AD7693 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 AD7693 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK IN– 4 7 SDO GND 5 6 CNV GND 5 IN+ 3 -004 IN– 4 10 VIO VDD 2 AD7693 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. QFN PACKAGE IN DEVELOPMENT. CONTACT SALES FOR SAMPLES AND AVAILABILITY. Figure 5. 10-Lead MSOP Pin Configuration -005 REF 1 Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 SDO SCK DO DI 9 SDI DI 10 VIO P Description Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part; chain or CS mode. In chain mode, the data should be read when CNV is high. In CS mode, it enables the SDO pin when low. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. PrB | Page 7 of 24 AD7693 Preliminary Technical Data TERMINOLOGY Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is LSB(V ) = VINp-p Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. 2N Total Harmonic Distortion (THD) Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 25). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ½ LSB above nominal negative full scale (−4.999847 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999771 V for the ±5 V range.) The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Rev. PrB | Page 8 of 24 Preliminary Technical Data AD7693 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Transition Figure 9. FFT Plot Figure 12. SNR vs. Input Level Rev. PrB | Page 9 of 24 AD7693 Preliminary Technical Data Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage Figure 14. SNR vs. Temperature Figure 17. THD vs. Temperature Figure 15. SINAD vs. Frequency Figure 18. THD vs. Frequency Rev. PrB | Page 10 of 24 Preliminary Technical Data AD7693 1000 VDD OPERATING CURRENT (µA) fS = 100kSPS VDD 750 500 250 4.75 5.00 5.25 5.50 SUPPLY (V) 05792-041 VIO 0 4.50 Figure 22. Offset and Gain Error vs. Temperature Figure 19. Operating Currents vs. Supply 25 20 750 tDSDO DELAY (ns) POWER-DOWN CURRENT (nA) 1000 500 15 VDD = 5V, 85°C 10 VDD = 5V, 25°C 250 5 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 20. Power-Down Currents vs. Temperature 500 250 VIO –35 –15 5 25 45 65 85 105 SUPPLY (V) 125 05792-042 OPERATING CURRENT (µA) VDD 750 –6 –55 0 20 40 60 80 SDO CAPACITIVE LOAD (pF) 100 Figure 23. tDSDO Delay vs. Capacitance Load and Supply 1000 fS = 100kSPS 0 Figure 21. Operating Currents vs. Temperature Rev. PrB | Page 11 of 24 120 05792-034 0 –55 05792-033 VDD + VIO AD7693 Preliminary Technical Data THEORY OF OPERATION IN+ SWITCHES CONTROL MSB 32,768C LSB 4C 16,384C 2C C SW+ C BUSY REF COMP GND 32,768C 4C 16,384C 2C C MSB CONTROL LOGIC OUTPUT CODE C LSB SW– -024 CNV IN– Figure 24. ADC Simplified Schematic CIRCUIT INFORMATION The AD7693 is a fast, low power, single-supply, precise, 16-bit ADC using a successive approximation architecture. The AD7693 is capable of converting 500,000 samples per second (500 kSPS) and powers down between conversions. When operating at 1 kSPS, for example, it consumes 40 μW typically, ideal for battery-powered applications. The AD7693 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7693 is specified from 4.5 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. It is pin-for-pin compatible with the 16-bit AD7687 and AD7688 and with the 18-bit AD7690 and AD7691. CONVERTER OPERATION The AD7693 is a successive approximation ADC based on a charge redistribution DAC. Figure 24 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7693 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. PrB | Page 12 of 24 Preliminary Technical Data AD7693 TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7693 is shown in Figure 25 and Table 7. Figure 26 shows an example of the recommended connection diagram for the AD7693 when multiple supplies are available. ADC CODE (TWOS COMPLEMENT) Transfer Functions 011...111 011...110 011...101 100...010 100...001 –FSR + 1LSB +FSR – 1LSB +FSR – 1.5LSB –FSR + 0.5LSB -025 100...000 –FSR ANALOG INPUT Figure 25. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 2 Digital Output Code (Hex) 0x7FFF1 0x0001 0x0000 0xFFFF 0x8001 0x80002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). V+ REF1 5V 10µF2 100nF V+ 1.8V TO VDD 100nF 15Ω REF 0 TO VREF VDD IN+ ADA4841-23 2.7nF V– V+ AD7693 VIO SDI SCK 3- OR 4-WIRE INTERFACE5 SDO 4 IN– 15Ω CNV GND VREF TO 0 ADA4841-23 2.7nF V– 4 1 SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3 SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE. Figure 26. Typical Application Diagram with Multiple Supplies Rev. PrB | Page 13 of 24 -026 1 Analog Input VREF = 5 V +4.999847 V +152.6 μV 0V −152.6 μV −4.999847 V −5 V AD7693 Preliminary Technical Data ANALOG INPUTS Figure 27 shows an equivalent circuit of the input structure of the AD7693. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, for example, an input buffer with a short-circuit, the current limitation can be used to protect the part. When the source impedance of the driving circuit is low, the AD7693 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. DRIVER AMPLIFIER CHOICE Although the AD7693 is easy to drive, the driver amplifier must meet the following requirements: • VDD D1 IN+ OR IN– CPIN CIN RIN D2 -027 GND The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7693. The noise coming from the driver is filtered by the AD7693 analog input circuit’s 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7693 is 56 μV rms, the SNR degradation due to the amplifier is Figure 27. Equivalent Analog Input Circuit SNRLOSS The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. VREF = VDD = 5V 85 80 CMRR (dB) 75 70 65 • For ac applications, the driver should have a THD performance commensurate with the AD7693. • For multichannel multiplexed applications, the driver amplifier and the AD7693 analog input circuit must settle for a full-scale step onto the capacitor array at an 16-bit level (0.0015%, 15 ppm). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at an 16-bit level and should be verified prior to driver selection. 55 50 45 40 10 100 1000 FREQUENCY (kHz) 10000 -028 1 Figure 28. Analog Input CMRR vs. Frequency During the acquisition phase, the impedance of the analog inputs (IN+ and IN−) can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 Ω and is a lumped component made up of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. ⎞ ⎟ ⎟ ⎟ ⎟⎟ ⎠ where: f−3 dB is the input bandwidth in megahertz of the AD7693 (9 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. 90 60 ⎛ ⎜ 56 = 20 log ⎜⎜ π π ⎜⎜ 56 2 + f −3 dB ( Ne N ) 2 + f −3 dB ( Ne N ) 2 2 2 ⎝ Table 8. Recommended Driver Amplifiers Amplifier ADA4941-1 ADA4841-x AD8655 AD8021 AD8022 OP184 AD8605, AD8615 Rev. PrB | Page 14 of 24 Typical Application Very low noise, low power single to differential Very low noise, small, and low power 5 V single supply, low noise Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low power Preliminary Technical Data AD7693 If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, especially DNL. SINGLE-TO-DIFFERENTIAL DRIVER For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-1 single-ended-to-differential driver allows for a differential input into the part. The schematic is shown in Figure 29. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. R1 and R2 set the attenuation ratio between the input range and the ADC range (VREF). R1, R2, and CF will be chosen depending on the desired input resistance, signal bandwidth, antialiasing and noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. POWER SUPPLY The AD7693 uses two power supply pins: a core supply, VDD, and a digital input/output interface supply, VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7693 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 30. R3 and R4 set the common mode on the IN− input, and R5 and R6 set the common mode on the IN+ input of the ADC. The common mode should be set close to VREF/2; however, if single supply is desired, it can be set slightly above VREF/2 to provide some headroom for the ADA4941-1 output stage. For example, for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. R4 75 +5V REF 10µF +5.2V +5.2V 100nF REF 15Ω 70 VDD 65 60 IN+ 2.7nF 55 AD7693 2.7nF 50 IN– 100nF 15Ω GND 45 ADA4941 40 1 10 100 1000 10000 -030 R3 80 FREQUENCY (kHz) R1 Figure 30. PSRR vs. Frequency R2 -029 CF Figure 29. Single-Ended-to-Differential Driver Circuit VOLTAGE REFERENCE INPUT The AD7693 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using low temperature drift ADR43x and ADR44x references. The AD7693 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. This makes the part ideal for low sampling rate (even a few hertz) and low battery-powered applications. 10000 1000 OPERATING CURRENT (µA) ±10V, ±5V, ... VDD = 5V 100 10 VIO 1 0.1 0.01 0.001 10 100 1k 10k 100k SAMPLING RATE (SPS) Figure 31. Operating Currents vs. Sample Rate Rev. PrB | Page 15 of 24 1M -031 R6 VREF = VDD = 5V 85 CMRR (dB) R5 90 AD7693 Preliminary Technical Data SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7693, with its low operating current, can be supplied directly using the reference circuit shown in Figure 32. The reference line can be driven by • The system power supply directly. • A reference voltage with enough current output capability, such as the ADR43x. • A reference buffer, such as the AD8031, which can also filter the system power supply, as shown in Figure 32. 5V 10k 1µF AD8031 10µF 1µF 1 REF VDD VIO In either mode, the AD7693 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. REFERENCE BUFFER AND FILTER. -032 AD7693 1OPTIONAL When in chain mode, the AD7693 provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is selected. 5V 10 5V ADSP-219x. In this mode, the AD7693 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. Figure 32. Example of Application Circuit DIGITAL INTERFACE Though the AD7693 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7693 is compatible with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or The busy indicator feature is enabled • • In the CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 36 and Figure 40). In the chain mode if SCK is high during the CNV rising edge (see Figure 44). Rev. PrB | Page 16 of 24 Preliminary Technical Data AD7693 subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7693 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 33, and the corresponding timing is given in Figure 34. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it continues until completion irrespective of the state of CNV. This could be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7693 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by CONVERT DIGITAL HOST CNV VIO SDI AD7693 DATA IN SDO SCK -033 CLK Figure 33. 3-Wire CS Mode Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 14 tHSDO 16 tSCKH tDSDO tEN D15 D14 D13 tDIS D1 D0 034 SDO 15 Figure 34. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High) Rev. PrB | Page 17 of 24 AD7693 Preliminary Technical Data data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7693 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 35, and the corresponding timing is given in Figure 36. If multiple AD7693s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7693 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The CONVERT VIO CNV DIGITAL HOST VIO SDI AD7693 DATA IN SDO SCK IRQ -035 CLK Figure 35. 3-Wire CS Mode with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 15 tHSDO 16 17 tSCKH tDSDO D15 D14 D1 D0 -036 SDO tDIS Figure 36. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High) Rev. PrB | Page 18 of 24 Preliminary Technical Data AD7693 time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7693 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7693 can be read. CS MODE 4-WIRE, NO BUSY INDICATOR This mode is usually used when multiple AD7693s are connected to an SPI-compatible digital host. A connection diagram example using two AD7693s is shown in Figure 37, and the corresponding timing is given in Figure 38. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV SDI DIGITAL HOST CNV AD7693 SDO SDI AD7693 SCK SDO SCK -037 DATA IN CLK Figure 37. 4-Wire CS Mode Without Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 3 14 tHSDO 16 17 18 D1 D0 D16 D15 30 31 32 D1 D0 tDSDO tEN SDO 15 tSCKH D15 D14 D13 tDIS Figure 38. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing Rev. PrB | Page 19 of 24 -038 SCK AD7693 Preliminary Technical Data line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7693 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, SDO returns to high impedance. CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7693 is connected to an SPI-compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 39, and the corresponding timing is given in Figure 40. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO CS1 CONVERT VIO CNV SDI AD7693 DIGITAL HOST DATA IN SDO SCK IRQ -039 CLK Figure 39. 4-Wire CS Mode with Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL SCK 1 2 3 tHSDO 15 16 17 tSCKH tDSDO tDIS tEN D15 D14 D1 D0 -040 SDO Figure 40. 4-Wire CS Mode with Busy Indicator Serial Interface Timing Rev. PrB | Page 20 of 24 Preliminary Technical Data AD7693 readback. When the conversion is complete, the MSB is output onto SDO and the AD7693 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and consequently more AD7693s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate can be reduced due to the total readback time. CHAIN MODE, NO BUSY INDICATOR This mode can be used to daisy-chain multiple AD7693s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7693s is shown in Figure 41, and the corresponding timing is given in Figure 42. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data CONVERT SDI CNV AD7693 SDO DIGITAL HOST AD7693 SDI A B SCK SCK SDO DATA IN -041 CNV CLK Figure 41. Chain Mode Without Busy Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 14 15 tSSDISCK 16 17 18 DA15 DA14 30 31 32 DA1 DA0 tSCKH tHSDISC tEN SDOA = SDIB DA15 DA14 DA13 DA1 DA0 DB15 DB14 DB13 DB1 DB0 SDOB Figure 42. Chain Mode Without Busy Indicator Serial Interface Timing Rev. PrB | Page 21 of 24 -042 tHSDO tDSDO AD7693 Preliminary Technical Data subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7693 ADC labeled C in Figure 43) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7693 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7693s in the chain, provided the digital host has an acceptable hold time. CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy chain multiple AD7693s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7693s is shown in Figure 43, and the corresponding timing is given in Figure 44. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the CONVERT SDI CNV AD7693 SDO SDI DIGITAL HOST CNV AD7693 SDO SDI AD7693 A B C SCK SCK SCK DATA IN SDO IRQ -043 CNV CLK Figure 43. Chain Mode with Busy Indicator Connection Diagram tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 15 16 18 19 31 32 33 34 35 tSCKL tHSDISC DA15 DA14 DA13 17 D A1 SDOB = SDIC 49 D A0 tDSDOSDI DB15 DB14 DB13 D B1 DB0 DA15 DA14 D A1 D A0 DC15 DC14 DC13 D C1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 tDSDOSDI SDOC 48 tDSDOSDI tHSDO tDSDO tDSDOSDI 47 tDSDOSDI Figure 44. Chain Mode with Busy Indicator Serial Interface Timing Rev. PrB | Page 22 of 24 DA1 DA0 -044 CNV = SDIA Preliminary Technical Data AD7693 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7693 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7693, with all its analog signals on the left side and all its digital signals on the right side, eases this task. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7693s. -045 Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7693 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. Figure 45. Example Layout of the AD7693 (Top Layer) The AD7693 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7693 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7693 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. -046 An example of a layout following these rules is shown in Figure 45 and Figure 46. EVALUATING THE AD7693’S PERFORMANCE Figure 46. Example Layout of the AD7693 (Bottom Layer) Other recommended layouts for the AD7693 are outlined in the documentation of the evaluation board for the AD7693 (EVAL-AD7693-CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. PrB | Page 23 of 24 AD7693 Preliminary Technical Data OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5.15 4.90 4.65 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 47.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters INDEX ARE A PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 1 (BOT TOM VIEW) 6 0.80 0.75 0.70 0.80 MAX 0.55 TYP SIDE VIEW SEATING PLANE 0.30 0.23 0.18 2.48 2.38 2.23 EXPOSED PAD TOP VIEW 0.50 0.40 0.30 5 1.74 1.64 1.49 0.05 MAX 0.02 NOM PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES 0.20 REF QFN Package in development. Contact sales for samples and availability. Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model EVAL-AD7693CB 1 EVAL-CONTROL BRD2 2 EVAL-CONTROL BRD32 1 2 Temperature Range Ordering Quantity Package Description Evaluation Board Controller Board Controller Board Package Option This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05793-9/06(PrB) Rev. PrB | Page 24 of 24 Branding