Infineon HYS64T64020KM-37-A Double-data-rate-two sdram micro-dimm Datasheet

D at a S he et , Rev. 0.6, J un e 2 00 4
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
Pr
eli
mi
na
DDR2 MDIMM
ry
Double-Data-Rate-Two SDRAM Micro-DIMM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
The information in this document is subject to change without notice.
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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question please contact your nearest Infineon Technologies Office.
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be endangered.
D at a S he et , Rev. 0.6, J un e 2 00 4
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
Pr
eli
mi
na
DDR2 MDIMM
ry
Double-Data-Rate-Two SDRAM Micro-DIMM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Preliminary
Revision History:
Rev. 0.6
2004-06
Previous Revision:
2004-04
Rev. 0.5
Page
Subjects (major changes since last revision)
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Added production variants with “H” instead of “L” in product type
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HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table of Contents
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
8
2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
3.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
4.1
4.2
IDD Specifications and Conditions
5
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Sheet
5
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
Preliminary
Double-Data-Rate-Two SDRAM Micro-DIMM
DDR2 MDIMM
1
HYS64T32000[H/K/L]M–[3.7/5]–A
HYS64T64020[H/K/L]M–[3.7/5]–A
Overview
This chapter gives an overview of the Double-Data-Rate-Two SDRAM Micro-DIMM product family and describes
its main characteristics.
1.1
•
•
•
•
•
Features
•
•
•
214-pin PC2-4200 and PC2-3200 DDR2 SDRAM
memory modules for use as main memory when
installed in systems such as mobile personal
computers.
32M × 64 and 64M × 64 module organisation and
32M × 16 chip organisation
JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
Built with 512Mb DDR2 SDRAMs in P-TFBGA-84-2
chipsize packages
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
Table 1
•
•
•
•
Burst Refresh, Distributed Refresh and Self Refresh
All inputs and outputs SSTL_1.8 compatible
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Serial Presence Detect with E2PROM
Micro-DIMM Dimensions (nominal) : 30 mm high,
54.0 mm wide
Based on JEDEC standard reference layouts Raw
Card “A” & “B”
2-piece type Mezzanine Socket with 0,4 mm
contact centers
Performance
Product Type Speed Code
–3.7
–5
Units
Speed Grade
PC2–4200 4–4–4
PC2–3200 3–3–3
—
266
200
MHz
266
200
MHz
200
200
MHz
15
15
ns
15
15
ns
45
45
ns
60
60
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
Description
The memory array is designed with 512Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs.
Decoupling capacitors are mounted on the PCB board.
The DIMMs feature serial presence detect based on a
serial E2PROM device using the 2-pin I2C protocol. The
first 128 bytes are programmed with configuration data
and are write protected; the second 128 bytes are
available to the customer.
The
INFINEON
HYS64T[3200/6402]0[H/K/L]M–
[3.7/5]–A module family are low profile Unbuffered
Micro-DIMM modules “MDIMMs” with 30,0 mm height
based on DDR2 technology. DIMMs are available as
32M × 64 and 64M × 64 organisation and density,
intended for mounting into 214-pin mezzanine
connector sockets.
Data Sheet
6
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 2
Overview
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
HYS64T64020KM-3.7-A
512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (×16)
HYS64T32000KM-3.7-A
256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T64020KM-5-A
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
HYS64T32000KM-5-A
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
HYS64T64020HM-3.7-A
512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (×16)
HYS64T64020LM-3.7-A
512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM
HYS64T32000HM-3.7-A
256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T32000LM-3.7-A
256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM
HYS64T64020HM-5-A
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
HYS64T64020LM-5-A
512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM
HYS64T32000HM-5-A
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
HYS64T32000LM-5-A
256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM
All product types end with a place code, designating the
silicon die revision. Example: HYS72T64000KM–5–A,
indicating Rev. A dies are used for DDR2 SDRAM
components. For all INFINEON DDR2 module and
component nomenclature see Chapter 8 of this data
sheet.
The Compliance Code is printed on the module label
and provides technical details to the user, e. g. "512MB
2R×16 PC2-4200M-444-11-A0" where "512MB" tells
the density in megabytes, "2R ×16" means 2 ranks on
module built of ×16 components, "PC2-4200M" means
DDR2 Micro-DIMM with 4.26 GB/s module bandwidth,
"444-11" means CAS latency of 4, RCD1) latency of 4,
and RP2) latency of 4 using JEDEC SPD revision 1.1,
and “A0” means JEDEC raw card A revision 0.
Table 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
# of
SDRAMs
# of row/bank/column bits
Raw
Card
256 MByte
32M × 64
1
4
13/2/10
B
512 MByte
64M × 64
2
8
13/2/10
A
Table 4
Components on Modules1)
Product Type
DRAM Components
2)
2)
HYS64T32000HM
HYS64T32000LM2)
HYB18T512160AF
HYS64T32000KM
HYB18T512160AC
2)
2)
HYS64T64020HM
HYS64T64020LM2)
HYB18T512160AF
HYS64T64020KM
HYB18T512160AC
DRAM Density
DRAM Organisation
512 Mbit
32M × 16
512 Mbit
32M × 16
512 Mbit
32M × 16
512 Mbit
32M × 16
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
1) RCD: Row Column Delay
2) RP: Row Precharge
Data Sheet
7
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
1.3
Overview
Pin Configuration
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1.
Table 5
Pin Configuration of MDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
122
CK0
I
SSTL
Clock Signals 1:0
194
CK1
I
SSTL
123
CK0
I
SSTL
Clock Signals
Complement Clock Signals 1:0
195
CK1
I
SSTL
43
CKE0
I
SSTL
Clock Enables
147
CKE1
I
SSTL
Note: 2-rank module
NC
NC
165
S0
I
SSTL
Chip Select Rank 0
62
S1
I
SSTL
Chip Select Rank 1
NC
NC
163
RAS
I
SSTL
Row Address Strobe
60
CAS
I
SSTL
Column Address Strobe
56
WE
I
SSTL
Write Enable
55
BA0
I
SSTL
Bank Address 1:0
162
BA1
I
SSTL
161
A0
I
SSTL
159
A1
I
SSTL
52
A2
I
SSTL
158
A3
I
SSTL
51
A4
I
SSTL
50
A5
I
SSTL
157
A6
I
SSTL
48
A7
I
SSTL
155
A8
I
SSTL
154
A9
I
SSTL
54
A10
I
SSTL
AP
I
SSTL
47
A11
I
SSTL
Address Input 11
153
A12
I
SSTL
Address Input 12
Note: 1-rank module
Control Signals
Note: 2-rank module
Note: 1-rank module
Address Signals
Data Sheet
8
Address Inputs 9:0
Address Input 10/Autoprecharge
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 5
Overview
Pin Configuration of MDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
3
DQ0
I/O
SSTL
Data Bus 63:0
4
DQ1
I/O
SSTL
9
DQ2
I/O
SSTL
Data Signals
10
DQ3
I/O
SSTL
109
DQ4
I/O
SSTL
110
DQ5
I/O
SSTL
114
DQ6
I/O
SSTL
115
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
117
DQ12
I/O
SSTL
118
DQ13
I/O
SSTL
125
DQ14
I/O
SSTL
126
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
128
DQ20
I/O
SSTL
129
DQ21
I/O
SSTL
133
DQ22
I/O
SSTL
134
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
38
DQ26
I/O
SSTL
39
DQ27
I/O
SSTL
136
DQ28
I/O
SSTL
137
DQ29
I/O
SSTL
142
DQ30
I/O
SSTL
143
DQ31
I/O
SSTL
67
DQ32
I/O
SSTL
68
DQ33
I/O
SSTL
73
DQ34
I/O
SSTL
74
DQ35
I/O
SSTL
174
DQ36
I/O
SSTL
175
DQ37
I/O
SSTL
179
DQ38
I/O
SSTL
Data Sheet
9
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 5
Overview
Pin Configuration of MDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
180
DQ39
I/O
SSTL
Data Bus 63:0
76
DQ40
I/O
SSTL
77
DQ41
I/O
SSTL
81
DQ42
I/O
SSTL
82
DQ43
I/O
SSTL
182
DQ44
I/O
SSTL
183
DQ45
I/O
SSTL
188
DQ46
I/O
SSTL
189
DQ47
I/O
SSTL
84
DQ48
I/O
SSTL
85
DQ49
I/O
SSTL
92
DQ50
I/O
SSTL
93
DQ51
I/O
SSTL
191
DQ52
I/O
SSTL
192
DQ53
I/O
SSTL
200
DQ54
I/O
SSTL
201
DQ55
I/O
SSTL
95
DQ56
I/O
SSTL
96
DQ57
I/O
SSTL
101
DQ58
I/O
SSTL
102
DQ59
I/O
SSTL
203
DQ60
I/O
SSTL
204
DQ61
I/O
SSTL
208
DQ62
I/O
SSTL
209
DQ63
I/O
SSTL
112
DM0
I
SSTL
Data Masks 7:0
120
DM1
I
SSTL
131
DM2
I
SSTL
Note: See block diagram for corresponding
DQ M signals
36
DM3
I
SSTL
177
DM4
I
SSTL
79
DM5
I
SSTL
90
DM6
I
SSTL
206
DM7
I
SSTL
Data Sheet
10
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 5
Overview
Pin Configuration of MDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
7
DQS0
I/O
SSTL
Data Strobes 7:0
6
DQS0
I/O
SSTL
19
DQS1
I/O
SSTL
Note: See block diagram for corresponding
DQS signals
18
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
27
DQS2
I/O
SSTL
140
DQS3
I/O
SSTL
139
DQS3
I/O
SSTL
71
DQS4
I/O
SSTL
70
DQS4
I/O
SSTL
186
DQS5
I/O
SSTL
185
DQS5
I/O
SSTL
198
DQS6
I/O
SSTL
197
DQS6
I/O
SSTL
99
DQS7
I/O
SSTL
98
DQS7
I/O
SSTL
105
SCL
I
CMOS
Serial Presence Detect (SPD) Clock Input
104
SDA
I/O
OD
SPD Data Input/Output
211
SA0
I
CMOS
SPD Address 1:0
213
SA1
I
CMOS
AI
–
I/O Reference Voltage
PWR
–
Power Supply
PWR
–
EEPROM Power Supply
GND
–
Ground Plane
EEPROM
Power Supplies
VREF
42, 45, 49, 53, 57, 61, 64, 146, 149, VDD
1
152, 156, 160, 164, 168, 171
VDDSPD
2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, VSS
107
35, 37, 40, 66, 69, 72, 75, 78, 80, 83,
86, 89, 91, 94, 97, 100, 103, 108,
111, 113, 116, 119, 121, 124, 127,
130, 132, 135, 138, 141, 144, 173,
176, 178, 181, 184, 187, 190, 193,
196, 205, 199, 202, 207, 210
Other Pins
166
ODT0
On-Die Termination Control 1:0
63
ODT1
Note: 2-rank module
NC
Note: 1-rank module
15, 16, 41, 44, 46, 58, 59, 65, 87, 88, NC
106, 145, 148, 150, 151, 167, 169,
170, 172, 212, 214
Data Sheet
NC
–
Not connected
Note: Pins not
MDIMMs
11
connected
on
Infineon
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 6
Overview
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 7
Abbreviation
Abbreviations for Buffer Type
Description
SSTL
Serial Stub Terminated Logic (SSTL_1.8)
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Overview
V REF - Pin 001
DQ0 - Pin 003
V SS - Pin 005
DQS0 - Pin 007
DQ2 - Pin 009
V SS - Pin 011
DQ9 - Pin 013
NC - Pin 015
V SS - Pin 017
DQS1 - Pin 019
DQ10 - Pin 021
V SS - Pin 023
DQ17 - Pin 025
DQS2 - Pin 027
V SS - Pin 029
DQ19 - Pin 031
DQ24 - Pin 033
V SS - Pin 035
V SS - Pin 037
DQ27 - Pin 039
NC - Pin 041
CKE0 - Pin 043
V DD - Pin 045
A11 - Pin 047
V DD - Pin 049
A4 - Pin 051
V DD - Pin 053
BA0 - Pin 055
V DD - Pin 057
NC - Pin 059
V DD - Pin 061
ODT1 - Pin 063
NC - Pin 065
DQ32 - Pin 067
V SS - Pin 069
DQS4 - Pin 071
DQ34 - Pin 073
V SS - Pin 075
DQ41 - Pin 077
DM5 - Pin 079
DQ42 - Pin 081
V SS - Pin 083
DQ49 - Pin 085
NC - Pin 087
V SS - Pin 089
V SS - Pin 091
DQ51 - Pin 093
DQ56 - Pin 095
V SS - Pin 097
DQS7 - Pin 099
DQ58 - Pin 101
V SS - Pin 103
SCL - Pin 105
V DDSPD - Pin 107
Figure 1
Data Sheet
V SS - Pin 002
Pin 109 - DQ4
DQ1 - Pin 004
DQS0 - Pin 006
V SS - Pin 008
Pin 111 - V SS
Pin 113 - V SS
Pin 115 - DQ7
DQ3 - Pin 010
Pin 117 - DQ12
DQ8 - Pin 012
Pin 119 - V SS
V SS - Pin 014
Pin 121 - V SS
NC - Pin 016
Pin 123 - CK0
DQS1 - Pin 018
Pin 125 - DQ14
V SS - Pin 020
Pin 127 - V SS
DQ11 - Pin 022
DQ16 - Pin 024
Pin 129 - DQ21
V SS - Pin 026
DQS2 - Pin 028
Pin 133 - DQ22
DQ18 - Pin 030
V SS - Pin 032
Pin 137 - DQ29
DQ25 - Pin 034
DM3 - Pin 036
DQ26 - Pin 038
Pin 141 - V SS
Pin 131 - DM2
Pin 135 - V SS
Pin 139 - DQS3
Pin 143 - DQ31
Pin 145 - NC
Pin 147 - CKE1
V SS - Pin 040
V DD - Pin 042
Pin 149 - V DD
NC - Pin 044
NC/BA2 - Pin 046
Pin 151 - NC
A7 - Pin 048
A5 - Pin 050
Pin 155 - A8
A2 - Pin 052
A10/AP - Pin 054
WE - Pin 056
Pin 159 - A1
Pin 161 - A0
NC - Pin 058
CAS - Pin 060
Pin 165 - S0
S1 V DD V SS DQ33 -
Pin 153 - A12
Pin 157 - A6
Pin 163 - RAS
Pin 167 - NC
Pin 062
Pin 169 - NC
Pin 064
Pin 171 - V DD
Pin 066
Pin 068
Pin 173 - V SS
Pin 175 - DQ37
DQS4 - Pin 070
V SS - Pin 072
DQ35 - Pin 074
Pin 177 - DM4
DQ40 - Pin 076
V SS - Pin 078
Pin 183 - DQ45
V SS - Pin 080
DQ43 - Pin 082
Pin 187 - V SS
DQ48 - Pin 084
V SS - Pin 086
Pin 191 - DQ52
NC - Pin 088
DM6 - Pin 090
DQ50 - Pin 092
Pin 195 - CK1
V SS - Pin 094
DQ57 - Pin 096
DQS7 - Pin 098
Pin 201 - DQS5
V SS - Pin 100
DQ59 - Pin 102
SDA - Pin 104
Pin 207 - V SS
NC - Pin 106
Pin 213 - SA1
Pin 179 - DQ38
Pin 181 - V SS
Pin 185 - DQS5
Pin 189 - DQ47
Pin 193 - V SS
Pin 197 - DQS6
Pin 199 - V SS
Pin 203 - DQ60
Pin 205 - V SS
Pin 209 - DQ63
Pin 211 - SA0
Pin 108 - V SS
Pin 110 - DQ5
Pin 112 - DM0
Pin 114 - DQ6
Pin 116 - V SS
Pin 118 - DQ13
Pin 120 - DM1
Pin 122 - CK0
Pin 124 - V SS
Pin 126 - DQ15
Pin 128 - DQ20
Pin 130 - V SS
Pin 132 - V SS
Pin 134 - DQ23
Pin 136 - DQ28
Pin 138 - V SS
Pin 140 - DQS3
Pin 142 - DQ30
Pin 144 - V SS
Pin 146 - V DD
Pin 148 - NC
Pin 150 - NC
Pin 152 - V DD
Pin 154 - A9
Pin 156 - V DD
Pin 158 - A3
Pin 160 - V DD
Pin 162 - BA1
Pin 164 - V DD
Pin 166 - ODT0
Pin 168 - V DD
Pin 170 - NC
Pin 172 - NC
Pin 174 - DQ36
Pin 176 - V SS
Pin 178 - V SS
Pin 180 - DQ39
Pin 182 - DQ44
Pin 184 - V SS
Pin 186 - DQS5
Pin 188 - DQ46
Pin 190 - V SS
Pin 192 - DQ53
Pin 194 - CK1
Pin 196 - V SS
Pin 198 - DQS6
Pin 200 - DQ54
Pin 202 - V SS
Pin 204 - DQ61
Pin 206 - DM7
Pin 208 - DQ62
Pin 210 - V SS
Pin 212 - NC
Pin 214 - NC
Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins)
13
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Overview
Table 8
Input/Output Functional Description
Symbol
Type
Polarity Function
CK[1:0],
CK[1:0]
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE[1:0]
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
S[1:0]
I
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA[1:0]
I
—
Selects internal SDRAM memory bank
ODT[1:0]
I
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[12:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to
define which bank to precharge.
DQ[63:0]
I/O
—
Data Input/Output pins
DM[7:0]
I
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[7:0],
DQS[7:0]
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 Ω to 10 kΩ resistor
and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply —
VDDSPD, VSS
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
SDA
I/O
—
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to to VDDSPD on the motherboard to act
as a pull-up.
SCL
I
—
This signal is used to clock data into and out of the SPD EEPROM.
SA[1:0]
I
—
Address pins used to select the Serial Presence Detect base address.
Data Sheet
14
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
2
Block Diagrams
Block Diagrams
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
CK0
CK1
CK1
VDD,SPD
VDD/VDDQ
VREF
VSS
BA0 - BA1: SDRAMs D0 - D7
A0 - An: SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
CKE0: SDRAMs D0 - D3
CKE1: SDRAMs D4 - D7
ODT0: SDRAMs D0 - D3
ODT1: SDRAMs D4 - D7
4 loads
4 loads
VDD: SPD EEPROM E0
VDD/V DDQ: SDRAMs D0 - D7
VREF: SDRAMs D0 - D7
VSS: SDRAMs D0 - D7
E0
SCL
SCL
SDA
SDA
SA0
A0
SA1
A1
A2
WP
S0
Vss
S1
DM0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D0
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D1
CS
D4
DM4
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D2
D3
CS
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
D6
D7
LDM
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
MPBT0010
Figure 2
Block Diagram Raw Card A (x64, 2 Ranks, x16)
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
Notes
1. DQ, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
15
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Block Diagrams
BA0 - BA1
A0 - An
RAS
CAS
WE
VSS
CKE0
ODT0
BA0 - BA1: SDRAMs D0 - D3
A0 - An: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
VSS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
ODT: SDRAMs D0 - D3
VDD,SPD
VDD/VDDQ
VREF
VSS
VDD: SPD EEPROM E0
VDD/V DDQ: SDRAMs D0 - D3
VREF: SDRAMs D0 - D3
VSS: SDRAMs D0 - D3
S0
CK0
CK0
CK1
CK1
SCL
SDA
SA0
SA1
2 loads
2 loads
SCL
SDA
A0
A1
A2
WP
Vss
E0
DM0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDM CS
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDM CS
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D0
D1
DM4
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDM CS
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDM CS
LDQS
LDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDM
UDQS
UDQS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
D2
D3
MPBT0020
Figure 3
Block Diagram Raw Card B (x64, 1 Rank, x16)
Notes
3. Load matching Capacitors on BA0 - BA1, A0 - An,
RAS, CAS, WE, with 8 pF ± 0.5pF
1. DQ, DQS, DM resistors are 22 Ω ±5 %
2. S0, BAn, An, RAS, CAS, WE, ODTO, CKEO
resistors are 3 Ω ±5 %
Data Sheet
16
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 9
Absolute Maximum Ratings
Parameter
Symbol
Values
Voltage on any pins relative to VSS
VIN, VOUT
Voltage on VDD relative to VSS
VDD
Voltage on VDDQ relative to VSS
VDDQ
Storage Humidity (without condensation) HSTG
Unit
Note/Test
Condition
Min.
Max.
– 0.5
2.3
V
1)
– 1.0
2.3
V
1)
– 0.5
2.3
V
1)
5
95
%
1)
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
Table 10
Operating Conditions
Parameter
Symbol
Operating temperature (ambient)
DRAM Case Temperature
Storage Temperature
TOPR
TCASE
TSTG
Barometric Pressure (operating & storage)
HOPR
Operating Humidity (relative)
Values
Unit
min.
max.
0
+65
°C
0
+95
°C
– 50
+100
°C
105
69
kPa
10
90
%
Notes
1)2)3)4)
5)
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to
tREFI = 3.9 µs
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85 °C Case Temperature before initiating Self-Refresh operation.
5) Up to 3000 m.
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Device Supply Voltage
VDD
Limit Values
Unit
min.
nom.
max.
1.7
1.8
1.9
Notes
V
—
Output Supply Voltage
VDDQ
1.7
1.8
1.9
V
1)
Input Reference Voltage
VREF
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
SPD Supply Voltage
VDDSPD
1.7
—
3.6
V
DC Input Logic High
VIH (DC)
VREF + 0.125
—
VDDQ + 0.3
V
DC Input Logic Low
VIL (DC)
– 0.30
—
VREF – 0.125
V
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
Data Sheet
17
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
IDD Specifications and Conditions
4
IDD Specifications and Conditions
Table 12
IDD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,
tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
IDD2N
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
IDD3P(1)
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD4R
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Distributed Refresh Current
IDD5D
tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
18
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 12
IDD Specifications and Conditions
IDD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
IDD6
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Organization
HYS64T64020HM-5-A
HYS64T64020LM-5-A
HYS64T64020KM-5-A
HYS64T32000HM-5-A
HYS64T32000LM-5-A
HYS64T32000KM-5-A
Product Type
HYS64T64020HM-3.7-A
HYS64T64020LM-3.7-A
HYS64T64020KM-3.7-A
IDD Specification
HYS64T32000HM-3.7-A
HYS64T32000LM-3.7-A
HYS64T32000KM-3.7-A
Table 13
Unit
Notes
256 MB
256 MB
512 MB
512 MB
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×64
×64
Symbol
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
280
320
296
336
mA
1)2)
300
360
316
376
mA
1)2)
16
16
32
32
mA
1)3)
128
160
256
320
mA
1)3)
100
120
200
240
mA
1)3)
52
64
104
128
mA
1)3)
20
20
40
40
mA
1)3)
140
160
280
320
mA
1)3)
340
400
356
416
mA
1)2)
360
440
376
456
mA
1)2)
480
520
496
536
mA
1)2)
24
24
40
40
mA
1)3)
16
16
32
32
mA
1)3)
840
880
856
896
mA
1)2)
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
2) For 2-rank modules only: The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) For 2-rank modules only: Both ranks are in the same
Data Sheet
IDD mode
19
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
4.1
IDD Specifications and Conditions
IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 14 are used.
Table 14
IDD Measurement Test Condition
Parameter
Symbol
-3.7
-5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
CAS Latency
CLmin
4
3
tCK
Clock Cycle Time
tCKmin
tRCDmin
tRCmin
3.75
5
ns
15
15
ns
60
60
ns
Active bank A to Active bank B command
delay
tRRDmin
10
10
ns
Active to Precharge Command
tRASmin
tRPmin
tRFCmin
45
45
ns
15
15
ns
105
105
ns
tREFI
7.8
7.8
µs
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
4.2
ODT (On Die Termination) Current
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
Table 15
ODT current per terminated pin
Parameter
Symbol min.
Enabled ODT current per DQ
IODTO
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
IODTT
typ.
max. Unit
EMRS(1) State
5
6
7.5
mA/DQ A6 = 0, A2 = 1
2.5
3
3.75
mA/DQ A6 = 1, A2 = 0
10
12
15
mA/DQ A6 = 0, A2 = 1
5
6
7.5
mA/DQ A6 = 1, A2 = 0
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
20
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
Table 16
AC Timing - Absolute Specifications −5/−3.71)
Parameter
Symbol −3.7
−5
PC2-4200M
Unit Notes
PC2-3200M
Min.
Max.
Min.
Max.
tAC
tCCD
tCH
tCK3
tCK4
tCKE
-500
+500
−600
+600
ps
2
—
2
—
0.45
0.55
0.45
0.55
tCK
tCK
5000
8000
5000
8000
ps
2)
3750
8000
5000
8000
ps
3)
3
—
3
—
tCK
tCL
tDAL
0.45
0.55
0.45
0.55
WR + tRP
—
WR + tRP
—
tCK
tCK
tIS + tCK + tIH —
tIS + tCK+ tIH —
ns
225
—
275
—
ps
0.35
—
0.35
—
tCK
DQS output access time from CK/CK tDQSCK
−450
+450
−500
+500
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
300
—
350
ps
Write command to 1st DQS latching
transition
tDQSS
WL - 0.25
WL + 0.25 WL − 0.25
WL + 0.25 tCK
100
—
150
—
ps
0.2
—
0.2
—
tCK
—
0.2
—
tCK
DQ output access time from CK/CK
CAS A to CAS B Command Period
CK, CK high-level width
Clock cycle time
CKE minimum high and low pulse
width
CK, CK low-level width
Auto precharge write recovery +
precharge time
Minimum time clocks remain ON
tDELAY
after CKE asynchronously drops low
DQ and DM input hold time
DQ and DM input pulse width (each
input)
tDH
tDIPW
tDS
DQS falling edge hold time from CLK tDSH
DQ and DM input setup time
(write cycle)
DQS falling edge to CLK setup time
(write cycle)
tDSS
0.2
Clock Half Period
tHP
tHZ
min. (tCL, tCH)
—
tACmax
—
tACmax
ps
tIH
tIPW
375
—
475
—
ps
0.6
—
0.6
—
tCK
250
—
350
—
ps
tLZ(DQ)
tLZ(DQS)
tMRD
2×tACmin
2×tACmin
tACmin
tACmax
tACmax
ps
tACmin
tACmax
tACmax
2
—
2
—
tCK
tOIT
0
12
0
12
ns
Data-out high-impedance time from
CK/CK
Address and control input hold time
Control and Addr. input pulse width
(each input)
Address and control input setup time tIS
DQ low-impedance from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle
time
OCD drive mode output delay
Data Sheet
21
min. (tCL, tCH)
tCK
ps
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 16
Electrical Characteristics & AC Timings
AC Timing - Absolute Specifications −5/−3.71)
Parameter
Symbol −3.7
−5
PC2-4200M
Unit Notes
PC2-3200M
Min.
Max.
Min.
Max.
tQH
tQHS
tRAS
tRC
tHP−tQHS
—
tHP−tQHS
—
tCK
—
400
—
450
ps
45
70000
45
70000
ns
60
—
60
—
ns
Active to Read or Write delay (with
and without Auto-Precharge) delay
tRCD
15
—
15
—
ns
Average Periodic Refresh Interval
tREFI
—
7.8
—
7.8
µs
4)
—
3.9
—
3.9
µs
5)
Data Output hold time from DQS
Data hold skew factor
Active to Precharge command
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
tRFC
105
—
105
—
ns
Precharge command period
tRP
tRPRE
tRPST
tRRD
15
—
15
—
ns
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
tCK
tCK
10
—
10
—
ns
Internal read to precharge command tRTP
delay
7.5
—
7.5
—
ns
tWPRE
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit power down to any valid
tXARD
0.25
—
0.25
—
0.40
0.60
0.40
0.60
tCK
tCK
15
—
15
—
ns
7.5
—
10
—
ns
2
—
2
—
tCK
6 − AL
—
6 − AL
—
tCK
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
command
(other than NOP or Deselect)
Exit active power-down mode to read tXARDS
command (slew exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
tCK
Exit Self-Refresh to non-read
command
tXSNR
tRFC + 10
—
tRFC + 10
—
ns
Exit Self-Refresh to read command
tXSRD
200
—
200
—
tCK
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) 0 °C ≤ TCASE ≤ 85 °C
5) 85 °C < TCASE ≤ 95 °C
Data Sheet
22
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Table 17
Electrical Characteristics & AC Timings
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol
Parameter / Condition
Min.
Max.
Unit
tAOND
tAON
tAONPD
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC(min)
tAC(min) + 2 ns
tAC(max) + 1 ns
2 tCK + tAC(max) + 1 ns
ns
ns
tAOFD
tAOF
tAOFPD
ODT turn-off delay
2.5
2.5
tCK
tAC(max) + 0.6 ns
2.5 tCK + tAC(max) + 1 ns
ns
ODT turn-on (Power-Down
Modes)
tAC(min)
ODT turn-off delay (Power-Down tAC(min) + 2 ns
ODT turn-off
ns
Modes)
tANPD
ODT to Power Down Mode Entry 3
Latency
—
tCK
tAXPD
ODT Power Down Exit Latency
—
tCK
Data Sheet
8
23
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
SPD Codes
SPD Codes
Table 18
SPD Codes for PC2-4200M and PC2-3200M
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
Jedec SPD Revision
HYS64T32000LM–3.7–A
HYS64T32000HM–5–A
×64
HYS64T32000KM–5–A
×64
HYS64T32000LM–5–A
×64
HYS64T64020HM–5–A
×64
HYS64T64020KM–5–A
256 MB
HYS64T64020LM–5–A
512 MB
HYS64T32000HM–3.7–A
256 MByte
HYS64T32000KM–3.7–A
512 MByte
HYS64T64020HM–3.7–A
Organization
HYS64T64020KM–3.7–A
Product Type
HYS64T64020LM–3.7–A
6
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1
Rev 1.1
Rev 1.1
Rev 1.1
Byte# Description
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
0
Programmed SPD Bytes in
E2PROM
80
80
80
80
80
80
80
80
80
80
80
80
1
Total number of Bytes in
E2PROM
08
08
08
08
08
08
08
08
08
08
08
08
2
Memory Type (DDR = 07h)
08
08
08
08
08
08
08
08
08
08
08
08
3
Number of Row Addresses
0D
0D
0D
0D
0D
0D
0D
0D
0D
0D
0D
0D
4
Number of Column Addresses 0A
0A
0A
0A
0A
0A
0A
0A
0A
0A
0A
0A
5
Number of DIMM Ranks
61
61
61
60
60
60
61
61
61
60
60
60
6
Data Width
40
40
40
40
40
40
40
40
40
40
40
40
7
not used
00
00
00
00
00
00
00
00
00
00
00
00
8
Interface Voltage Levels
05
05
05
05
05
05
05
05
05
05
05
05
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte
3D
3D
3D
3D
3D
3D
50
50
50
50
50
50
50
50
50
50
50
50
60
60
60
60
60
60
11
Error Correction Support (non- 00
/ ECC)
00
00
00
00
00
00
00
00
00
00
00
12
Refresh Rate/Type
82
82
82
82
82
82
82
82
82
82
82
82
13
Primary SDRAM Width
10
10
10
10
10
10
10
10
10
10
10
10
14
Error Checking SDRAM Width 00
00
00
00
00
00
00
00
00
00
00
00
15
not used
00
00
00
00
00
00
00
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
0C
0C
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM
Device
04
04
04
04
04
04
04
04
04
04
04
04
18
CAS Latency
38
38
38
38
38
38
38
38
38
38
38
38
19
not used
00
00
00
00
00
00
00
00
00
00
00
00
20
DIMM Type Information
08
08
08
08
08
08
08
08
08
08
08
08
21
DIMM Attributes
00
00
00
00
00
00
00
00
00
00
00
00
10
18) [ns]
Data Sheet
24
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
SPD Codes for PC2-4200M and PC2-3200M
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
Jedec SPD Revision
HYS64T32000LM–3.7–A
HYS64T32000HM–5–A
×64
HYS64T32000KM–5–A
×64
HYS64T32000LM–5–A
×64
HYS64T64020HM–5–A
×64
HYS64T64020KM–5–A
256 MB
HYS64T64020LM–5–A
512 MB
HYS64T32000HM–3.7–A
256 MByte
HYS64T32000KM–3.7–A
512 MByte
HYS64T64020HM–3.7–A
Organization
HYS64T64020KM–3.7–A
Product Type
HYS64T64020LM–3.7–A
Table 18
SPD Codes
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1
Rev 1.1
Rev 1.1
Rev 1.1
Byte# Description
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
22
Component Attributes
01
01
01
01
01
01
01
01
01
01
01
01
23
3D
3D
3D
3D
3D
3D
50
50
50
50
50
50
50
50
50
50
50
50
60
60
60
60
60
60
50
50
50
50
50
50
50
50
50
50
50
50
60
60
60
60
60
60
60
60
60
60
60
60
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
28
28
28
28
28
28
28
28
28
28
28
28
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
30
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
2D
2D
2D
2D
2D
2D
2D
2D
2D
2D
2D
2D
31
Module Density per Rank
40
40
40
40
40
40
40
40
40
40
40
40
32
25
25
25
25
25
25
35
35
35
35
35
35
37
37
37
37
37
37
47
47
47
47
47
47
10
10
10
10
10
10
15
15
15
15
15
15
22
22
22
22
22
22
27
27
27
27
27
27
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
28
28
28
28
28
28
38
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
tWR [ns]
tWTR [ns]
tRTP [ns]
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
00
00
00
00
00
00
00
40
00
00
00
00
00
00
00
00
00
00
00
00
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
69
69
69
69
69
69
69
69
69
69
69
69
80
80
80
80
80
80
80
80
80
80
80
80
1E
1E
1E
1E
1E
1E
23
23
23
23
23
23
28
24
25
26
27
28
29
33
34
35
36
37
45
tRC and tRFC extension
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
28
28
28
28
28
2D
2D
2D
2D
2D
2D
46
PLL Relock Time
00
00
00
00
00
00
00
00
00
00
00
00
47
Tc(max) Delta / DT4R4W Delta 53
53
53
53
53
53
51
51
51
51
51
51
48
Psi(T-A) DRAM
72
72
72
72
72
72
72
72
72
72
72
72
49
DT0
52
52
52
52
52
52
42
42
42
42
42
42
41
42
43
44
Data Sheet
25
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
SPD Codes for PC2-4200M and PC2-3200M
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
Jedec SPD Revision
HYS64T32000LM–3.7–A
HYS64T32000HM–5–A
×64
HYS64T32000KM–5–A
×64
HYS64T32000LM–5–A
×64
HYS64T64020HM–5–A
×64
HYS64T64020KM–5–A
256 MB
HYS64T64020LM–5–A
512 MB
HYS64T32000HM–3.7–A
256 MByte
HYS64T32000KM–3.7–A
512 MByte
HYS64T64020HM–3.7–A
Organization
HYS64T64020KM–3.7–A
Product Type
HYS64T64020LM–3.7–A
Table 18
SPD Codes
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1
Rev 1.1
Rev 1.1
Rev 1.1
Byte# Description
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
50
DT2N (UDIMM) or DT2Q
(RDIMM)
2B
2B
2B
2B
2B
2B
23
23
23
23
23
23
51
DT2P
1D
1D
1D
1D
1D
1D
1D
1D
1D
1D
1D
1D
52
DT3N
1D
1D
1D
1D
1D
1D
19
19
19
19
19
19
53
DT3Pfast
23
23
23
23
23
23
1C
1C
1C
1C
1C
1C
54
DT3Pslow
16
16
16
16
16
16
16
16
16
16
16
16
55
DT4R / DT4R4W Sign
36
36
36
36
36
36
2E
2E
2E
2E
2E
2E
56
DT5B
1C
1C
1C
1C
1C
1C
1A
1A
1A
1A
1A
1A
57
DT7
30
30
30
30
30
30
2D
2D
2D
2D
2D
2D
58
Psi(ca) PLL
00
00
00
00
00
00
00
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
00
00
00
00
00
00
00
60
DTPLL
00
00
00
00
00
00
00
00
00
00
00
00
61
DTREG / Toggle Rate
00
00
00
00
00
00
00
00
00
00
00
00
62
SPD Revision
11
11
11
11
11
11
11
11
11
11
11
11
63
Checksum of Byte 0-62
C0
C0
C0
BF
BF
BF
12
12
12
11
11
11
64
JEDEC ID Code of Infineon (1) C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
C1
65
JEDEC ID Code of Infineon (2) 00
00
00
00
00
00
00
00
00
00
00
00
66
JEDEC ID Code of Infineon (3) 00
00
00
00
00
00
00
00
00
00
00
00
67
JEDEC ID Code of Infineon (4) 00
00
00
00
00
00
00
00
00
00
00
00
68
JEDEC ID Code of Infineon (5) 00
00
00
00
00
00
00
00
00
00
00
00
69
JEDEC ID Code of Infineon (6) 00
00
00
00
00
00
00
00
00
00
00
00
70
JEDEC ID Code of Infineon (7) 00
00
00
00
00
00
00
00
00
00
00
00
71
JEDEC ID Code of Infineon (8) 00
00
00
00
00
00
00
00
00
00
00
00
72
Module Manufacturer Location xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
36
36
36
36
36
36
36
36
74
Product Type, Char 2
34
34
34
34
34
34
34
34
34
34
34
34
75
Product Type, Char 3
54
54
54
54
54
54
54
54
54
54
54
54
76
Product Type, Char 4
36
36
36
33
33
33
36
36
36
33
33
33
Data Sheet
26
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
SPD Codes for PC2-4200M and PC2-3200M
2 Ranks (×16)
1 Rank (×16)
2 Ranks (×16)
1 Rank (×16)
Label Code
Jedec SPD Revision
HYS64T32000LM–3.7–A
HYS64T32000HM–5–A
×64
HYS64T32000KM–5–A
×64
HYS64T32000LM–5–A
×64
HYS64T64020HM–5–A
×64
HYS64T64020KM–5–A
256 MB
HYS64T64020LM–5–A
512 MB
HYS64T32000HM–3.7–A
256 MByte
HYS64T32000KM–3.7–A
512 MByte
HYS64T64020HM–3.7–A
Organization
HYS64T64020KM–3.7–A
Product Type
HYS64T64020LM–3.7–A
Table 18
SPD Codes
PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333
Rev 1.1
Rev 1.1
Rev 1.1
Rev 1.1
Byte# Description
HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX
77
Product Type, Char 5
34
34
34
32
32
32
34
34
34
32
32
32
78
Product Type, Char 6
30
30
30
30
30
30
30
30
30
30
30
30
79
Product Type, Char 7
32
32
32
30
30
30
32
32
32
30
30
30
80
Product Type, Char 8
30
30
30
30
30
30
30
30
30
30
30
30
81
Product Type, Char 9
4C
4B
48
4C
4B
48
4C
4B
48
4C
4B
48
82
Product Type, Char 10
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
83
Product Type, Char 11
33
33
33
33
33
33
35
35
35
35
35
35
84
Product Type, Char 12
2E
2E
2E
2E
2E
2E
41
41
41
41
41
41
85
Product Type, Char 13
37
37
37
37
37
37
20
20
20
20
20
20
86
Product Type, Char 14
41
41
41
41
41
41
20
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
20
20
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
20
20
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
20
20
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
20
20
20
20
20
20
20
91
Module Revision Code
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
92
Test Program Revision Code
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
93
Module Manufacturing Date
Year
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
94
Module Manufacturing Date
Week
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
99 127
Not used
00
00
00
00
00
00
00
00
00
00
00
00
128255
BLANK
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Data Sheet
27
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
7
Package Outlines
Package Outlines
3.8 MAX.
54 ±0.15
1.65 -0.25
B
30 ±0.15
2.3 ±0.2
2.6 ±0.1
0.1 C
0.62 ±0.03
C
A
0.1
(44.72)
43.38 ±0.02
D
0.8 ±0.08
0.1 M C B M
A
0.4
214
A
1
107
B
4.3
B
2.9
(2.43)
(3.44)
106 x 0.4 = 42.4
108
Detail of contacts
A-A
B-B
E
1.3 ±0.02
0.1 M A B M
1.08 -0.04
Contact Area
0.4
0.26 ±0.02
0.06 C D E 107x
Burnished, no burr allowed
Figure 4
Data Sheet
GLD09638
PCB Raw Card A Component Placement L-DIM-214-1
32
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
Package Outlines
2.34 MAX.
54 ±0.15
1.65 -0.25
B
30 ±0.15
2.3 ±0.2
2.6 ±0.1
0.1 C
0.62 ±0.03
C
A
0.1
(44.72)
43.38 ±0.02
D
0.8 ±0.08
0.1 M C B M
0.4
107
214
1
B
A
4.3
B
A
2.9
(2.43)
(3.44)
106 x 0.4 = 42.4
108
Detail of contacts
A-A
B-B
E
1.3 ±0.02
0.1 M A B M
1.08 -0.04
Contact Area
0.4
0.26 ±0.02
0.06 C D E 107x
Burnished, no burr allowed
Figure 5
Data Sheet
GLD09668
PCB Raw Card B Component Placement L-DIM-214-2
33
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A
Double-Data-Rate-Two SDRAM Micro-DIMM
Preliminary
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 20 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 21 and for components in Table 22.
Table 20
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512
16
0
A
C
–5
1
INFINEON
Modul Prefix
HYS
Constant
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
2
Module Data
Width [bit]
64
Non-ECC
Table 22
72
ECC
Field Description
3
DRAM
Technology
T
DDR2
1
INFINEON
Component Prefix
4
Memory Density
per I/O [Mbit];
Module Density1)
32
256 MByte
2
Interface Voltage [V] 18
64
512 MByte
3
DRAM Technology
128
1 GByte
4
256
2 GByte
Component Density 256
[Mbit]
512
0 .. 9
look up table
Table 21
DDR2 DIMM Nomenclature
Field Description
Values Coding
5
Raw Card
Generation
6
Number of Module 0, 2, 4
Ranks
1, 2, 4
7
Product Variations 0 .. 9
look up table
8
Package,
Lead-Free Status
A .. Z
look up table
Module Type
S
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
9
10
11
Speed Grade
Die Revision
Data Sheet
DDR2 DRAM Nomenclature
5+6 Number of I/Os
HYB
Constant
SSTL1.8
T
DDR2
256 Mbit
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
7
Product Variations
0 .. 9
look up table
8
Die Revision
A
First
B
Second
C
FBGA,
lead-containing
F
FBGA, lead-free
–3.7
DDR2-533
–5
DDR2-400
9
10
11
34
Values Coding
Package,
Lead-Free Status
Speed Grade
N/A for Components
Rev. 0.6, 2004-06
03242004-2CBE-IJ2X
www.infineon.com
Published by Infineon Technologies AG