AD AD7938BCPZ-6 8-channel, 625 ksps, 12-bit parallel adcs with a sequencer Datasheet

8-Channel, 625 kSPS, 12-Bit
Parallel ADCs with a Sequencer
AD7938-6
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
AD7938-6
VREFIN/
VREFOUT
2.5V
VREF
VIN0
I/P
MUX
CLKIN
12-BIT
SAR ADC
AND
CONTROL
T/H
CONVST
BUSY
VIN7
SEQUENCER
VDRIVE
PARALLEL INTERFACE/CONTROL REGISTER
DB0 DB11
CS RD WR W/B
04751-001
Throughput rate: 625 kSPS
Specified for VDD of 2.7 V to 5.25 V
Power consumption
3.6 mW maximum at 625 kSPS with 3 V supplies
7.5 mW maximum at 625 kSPS with 5 V supplies
8 analog input channels with a sequencer
Software-configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo differential inputs
7-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
±0.2% maximum @ 25°C, 25 ppm/°C maximum
69 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface with word/byte modes
Full shutdown mode: 2 µA maximum
32-lead LFCSP and TQFP packages
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7938-6 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter (ADC). The
part operates from a single 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS. The part contains a
low noise, wide bandwidth, differential track-and-hold
amplifier that can handle input frequencies up to 50 MHz.
The AD7938-6 features eight analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. The part can operate
with either single-ended, fully differential, or pseudo differential
analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is initiated at
this point.
The AD7938-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
features flexible power management options. An on-chip
control register allows the user to set up different operating
conditions, including analog input range and configuration,
output coding, power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
High throughput with low power consumption.
Eight analog inputs with a channel sequencer.
Accurate on-chip 2.5 V reference.
Single-ended, pseudo differential, or fully differential
analog inputs that are software selectable.
Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V or 5 V processor systems independent of VDD.
No pipeline delay.
Accurate control of the sampling instant via a CONVST
input and once-off conversion control.
Table 1.
Similar Device
AD7938/AD7939
AD7933/AD7934
AD7934-6
No. of Bits
12/10
10/12
12
No. of Channels
8
4
4
Speed
1.5 MSPS
1.5 MSPS
625 kSPS
The AD7938-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
Rev. D
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AD7938-6
Data Sheet
TABLE OF CONTENTS
Features .....................................................................................1
Converter Operation ........................................................... 16
Functional Block Diagram.........................................................1
ADC Transfer Function ....................................................... 16
General Description ..................................................................1
Typical Connection Diagram............................................... 17
Product Highlights.................................................................1
Analog Input Structure ........................................................ 17
Revision History ........................................................................2
Analog Inputs ...................................................................... 18
Specifications.............................................................................3
Analog Input Selection ........................................................ 20
Timing Specifications.............................................................5
Reference ............................................................................. 21
Absolute Maximum Ratings ......................................................6
Parallel Interface.................................................................. 23
ESD Caution ..........................................................................6
Power Modes of Operation .................................................. 26
Pin Configuration and Function Descriptions...........................7
Power vs. Throughput Rate.................................................. 27
Typical Performance Characteristics .........................................9
Microprocessor Interfacing.................................................. 27
Terminology ............................................................................11
Application Hints .................................................................... 29
On-Chip Registers ...................................................................13
Grounding and Layout ........................................................ 29
Control Register...................................................................13
PCB Design Guidelines for Chip Scale Package................... 29
Sequencer Operation ...........................................................14
Evaluating the AD7938-6 Performance ............................... 29
Shadow Register...................................................................14
Outline Dimensions ................................................................ 30
Circuit Information .................................................................16
Ordering Guide ................................................................... 31
REVISION HISTORY
1/2017—Rev. C to Rev. D
Changed CP-32-2 to CP-32-7 ...................................Throughout
Changes to Figure 2 ...................................................................7
Added Figure 3; Renumbered Sequentially................................7
Updated Outline Dimensions..................................................30
Changes to Ordering Guide.....................................................31
10/2011—Rev. B to Rev. C
Change to Features Section........................................................1
Added Exposed Pad Notation to Outline Dimensions ............ 30
Changes to Ordering Guide..................................................... 31
2/2007—Rev. 0 to Rev. A
Changes to Specifications.......................................................... 3
Changes to Figure 13............................................................... 10
Changes to Sequencer Operation Section................................ 14
Changes to Analog Inputs Section........................................... 18
Updated Outline Dimensions.................................................. 30
10/2004—Revision 0: Initial Version
10/2011—Rev. A to Rev. B
Changes to Table 2.....................................................................3
Changes to Figure 2 and Table 5 ................................................7
Rev. D | Page 2 of 32
Data Sheet
AD7938-6
SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; f CLKIN = 10 MHz, f SAMPLE = 625 kSPS; TA = TMIN to
TMAX 1, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Differential Mode
Single-Ended Mode
Single-Ended and Pseudo Differential Input
Offset Error 2
Offset Error Match2
Gain Error 2
Gain Error Match2
Fully Differential Input
Positive Gain Error 2
Positive Gain Error Match2
Zero-Code Error 2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Single-Ended Input Range
Pseudo Differential Input Range:
VIN+
VIN−
Fully Differential Input Range
VIN+ and VIN−
VIN+ and VIN−
Value 1
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
Single-ended mode
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
fa = 30 kHz, fb = 50 kHz
69
67
71
69
−73
−69.5
−72
dB min
dB min
dB min
dB min
dB max
dB max
dB max
−86
−90
−85
5
72
50
10
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
12
±1
±1.5
Bits
LSB max
LSB max
±0.95
−0.95/+1.5
LSB max
LSB max
±12
±3
±3
±2
LSB max
LSB max
LSB max
LSB max
±3
±1.5
±9.5
±1
±3
±1.5
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
0 to VREF
0 to 2 × VREF
V
V
RANGE bit = 0
RANGE bit = 1
0 to VREF
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
V
V
V typ
V typ
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
VDD = 5 V
VCM ± VREF/2
VCM ± VREF
V
V
VCM = common-mode voltage 3 = VREF/2
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
fIN = 50 kHz, fNOISE = 300 kHz
@ 3 dB
@ 0.1 dB
Differential mode
Single-ended mode
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
Twos complement output coding
Rev. D | Page 3 of 32
AD7938-6
Parameter
DC Leakage Current 4
Input Capacitance
REFERENCE INPUT/OUTPUT
VREF Input Voltage 5
DC Leakage Current
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
VREF Noise
VREF Output Impedance
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, I IN
Input Capacitance, CIN4
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
I DD 6
Normal Mode (Static)
Normal Mode (Operational)
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
Normal Mode (Operational)
Autostandby Mode (Static)
Full/Autoshutdown Mode (Static)
Data Sheet
Value 1
±1
45
10
Unit
µA max
pF typ
pF typ
Test Conditions/Comments
2.5
±1
2.5
25
5
10
130
10
15
25
V
µA max
V
ppm/°C max
ppm/°C typ
µV typ
µV typ
Ω typ
pF typ
pF typ
±1% for specified performance
2.4
0.8
±5
10
V min
V max
µA max
pF max
2.4
0.4
±3
10
Straight (Natural) Binary
Twos Complement
V min
V max
µA max
pF max
t 2 + 13 t CLKIN
125
80
625
ns
ns max
ns typ
kSPS max
2.7/5.25
2.7/5.25
V min/max
V min/max
0.8
1.5
1.2
0.3
160
2
mA typ
mA max
mA max
mA typ
µA typ
µA max
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
fSAMPLE = 100 kSPS, VDD = 5 V
Static
SCLK on or off
7.5
3.6
800
480
10
6
mW max
mW max
µW typ
µW typ
µW max
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
When in track
When in hold
±0.2% max @ 25°C
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
When in track
When in hold
Typically 10 nA, VIN = 0 V or VDRIVE
I SOURCE = 200 µA
I SINK = 200 µA
CODING bit = 0
CODING bit = 1
1
Full-scale step input
Sine wave input
Temperature range is −40°C to +85°C.
See the Terminology section.
For full common-mode range, see Figure 26 and Figure 27.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range of 0.1 V to V . See the Reference section for more information.
DD
6 Measured with a midscale dc analog input.
2
3
Rev. D | Page 4 of 32
Data Sheet
AD7938-6
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; f CLKIN = 10MHz, f SAMPLE = 625 kSPS; TA = TMIN to
TMAX , unless otherwise noted.
Table 3.
Parameter 1
fCLKIN 2
Limit at TMIN, TMAX
700
10
t QUIET
Description
CLKIN frequency
30
Unit
kHz min
MHz
max
ns min
t1
t2
10
15
ns min
ns min
t3
t4
t5
50
0
0
ns max
ns min
ns min
CONVST pulse width.
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
CS to WR hold time.
t6
t7
10
10
ns min
ns min
WR pulse width.
Data setup time before WR .
t8
t9
t 10
10
10
0
ns min
ns min
ns min
t 11
t 12
0
30
ns min
ns min
Data hold after WR .
New data valid before falling edge of BUSY.
CS to RD setup time.
CS to RD hold time.
RD pulse width.
t 13 3
t 14 4
30
3
ns max
ns min
Data access time after RD .
Bus relinquish time after RD .
t 15
50
0
ns max
ns min
t 16
t 17
t 18
0
10
0
ns min
ns min
ns min
Bus relinquish time after RD .
HBEN to RD setup time.
HBEN to RD hold time.
Minimum time between reads/writes.
HBEN to WR setup time.
t 19
t 20
t 21
t 22
10
40
15.7
7.8
ns min
ns max
ns min
ns min
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
Minimum time between end of read and start of next conversion, that is, time from when
the data bus goes into three-state until the next falling edge of CONVST .
1
Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2 Minimum CLKIN for specified performance, with slower CLKIN frequencies performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
14
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. D | Page 5 of 32
AD7938-6
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to AGND/DGND
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to DGND
VREFIN to AGND
AGND to DGND
Input Current to Any Pin Except Supplies 1
Operating Temperature Range,
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec)
ESD
1
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
±10 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
108.2°C/W (LFCSP)
121°C/W (TQFP)
32.71°C/W (LFCSP)
45°C/W (TQFP)
255°C
1.5 kV
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. D | Page 6 of 32
Data Sheet
AD7938-6
W/B
VDD
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
30
29
28
27
26
25
24
VIN1
DB1 2
23
VIN0
DB2 3
22
VREFIN/VREFOUT
TOP VIEW
(Not to Scale)
20
CS
DB5 6
19
RD
DB6 7
18
WR
DB7 8
17
CONVST
9
04751-006
Figure 2. Pin Configuration (CP-32-7)
10
11
12
13
14
15
16
CLKIN
AGND
DB4 5
BUSY
21
DB11
AD7938-6
DB10
DB3 4
DB9
VDRIVE
DGND
DB8/HBEN
DB9
DB10
DB11
BUSY
CLKIN
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF
THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE
OF THE PCB USING MULTIPLE VIAS.
PIN 1
IDENTIFIER
DB0 1
DB8/HBEN
TOP VIEW
(Not to Scale)
VIN1
VIN0
VREFIN/VREFOUT
AGND
CS
RD
WR
CONVST
DGND
AD7938-6
24
23
22
21
20
19
18
17
04751-106
W/B
VDD
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
31
VDRIVE
1
2
3
4
5
6
7
8
32
9
10
11
12
13
14
15
16
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
32
31
30
29
28
27
26
25
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration (SU-32-2)
Table 5. Pin Function Description
Pin No.
1 to 8
Mnemonic
DB0 to DB7
9
VDRIVE
10
DGND
11
DB8/HBEN
12 to 14
DB9 to DB11
15
BUSY
16
CLKIN
17
CONVST
18
WR
Description
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic
high/low voltage levels for these pins are determined by the VDRIVE input.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that
at VDD but should never exceed VDD by more than 0.3 V.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of
data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4 to DB6
of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s.
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR.
The logic high/low voltage levels for these pins are determined by the VDRIVE input.
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode
just prior to the falling edge of BUSY on the 13th rising edge of CLKIN (see Figure 36).
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from
track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point.
Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is
used to power up the device.
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Rev. D | Page 7 of 32
AD7938-6
Pin No.
19
Mnemonic
20
CS
21
AGND
22
VREFIN /VREFOUT
23 to 30
VIN 0 to VIN 7
31
VDD
32
W/B
RD
EPAD
Data Sheet
Description
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data
to the internal registers.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7938-6. All analog
input signals and any external reference signal should be referred to this AGND voltage. The AGND and
DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the
ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. It is recommended that this pin
be decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input
voltage range for the external reference is 0.1 V to VDD ; however, care must be taken to ensure that the analog
input range does not exceed VDD + 0.3 V. See the Reference section.
Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-andhold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register
appropriately (see Table 9). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be
used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow
register to be programmed. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and
the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the
control register. Any unused input channels should be connected to AGND to avoid noise pickup.
Power Supply Input. The VDD range for the AD7938-6 is 2.7 V to 5.25 V. The supply should be decoupled to AGND
with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938-6 in 12-bit words on
Pin DB0 to Pin DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are
transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when
operating in byte transfer mode should be tied off to DGND.
Exposed Pad. The exposed pad is located on the underside of the package. Connect the EPAD to the ground
plane of the PCB using multiple vias.
Rev. D | Page 8 of 32
Data Sheet
AD7938-6
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
–60
0
100mV p-p SINE WAVE ON VDD AND/OR VDRIVE
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
–70
–20
–30
INT REF
–80
–40
(dB)
PSRR (dB)
4096 POINT FFT
VDD = 5V
FSAMPLE = 625kSPS
FIN = 49.62kHz
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
–10
–90
–50
–60
EXT REF
–70
–100
–80
04751-007
700
600
VDD = 5V
DIFFERENTIAL MODE
0.8
–75
0.6
DNL ERROR (LSB)
–80
–85
–90
0.4
0.2
0
–0.2
–0.4
04751-021
–0.6
0
100
200
300
400
500
600
NOISE FREQUENCY (kHz)
700
04751-010
NOISE ISOLATION (dB)
500
1.0
INTERNAL/EXTERNAL REFERENCE
VDD = 5V
–0.8
–1.0
800
0
500
1000
1500
2000 2500
CODE
3000
3500
4000
Figure 8. AD7938-6 Typical DNL @ VDD = 5 V
Figure 5. AD7938-6 Channel-to-Channel Isolation
1.0
80
VDD = 5V
VDD = 5V
DIFFERENTIAL MODE
0.8
70
0.6
VDD = 3V
INL ERROR (LSB)
60
50
40
0.4
0.2
0
–0.2
–0.4
FSAMPLE = 625kSPS
RANGE = 0 TO VREF
DIFFERENTIAL MODE
0
100
200
300
400 500 600 700
FREQUENCY (kHz)
800
900
04751-011
–0.6
30
–0.8
04751-008
SINAD (dB)
400
Figure 7. AD7938-6 FFT @ VDD = 5 V
–70
20
300
FREQUENCY (kHz)
Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
–195
200
–110
1010
100
210
410
610
810
SUPPLY RIPPLE FREQUENCY (kHz)
–100
0
–120
10
04751-009
–90
–110
–1.0
1000
Figure 6. AD7938-6 SINAD vs. Analog Input
Frequency for Various Supply Voltages
0
500
1000
1500
2000 2500
CODE
3000
Figure 9. AD7938-6 Typical INL @ VDD = 5 V
Rev. D | Page 9 of 32
3500
4000
AD7938-6
Data Sheet
6
10000
SINGLE-ENDED MODE
DIFFERENTIAL MODE
9000
5
9997
CODES
INTERNAL
REF
8000
7000
6000
3
???
DNL (LSB)
4
2
5000
4000
1
3000
POSITIVE DNL
04751-012
–1
0.25
NEGATIVE DNL
0.50
0.75
1.00
1.25
1.50 1.75
VREF (V)
2.00
2.25
2.50
04751-015
2000
0
1000
0
2046
2.75
3 CODES
2047
2048
2049
2050
CODE
Figure 10. AD7938-6 DNL vs. VREF for VDD = 3 V
Figure 13. AD7938-6 Histogram of Codes for
10,000 Samples @ VDD = 5 V with Internal Reference
12
120
11
110
VDD = 5V
DIFFERENTIAL MODE
10
100
VDD = 5V
SINGLE-ENDED MODE
9
CMRR (dB)
VDD = 3V
SINGLE-ENDED MODE
8
80
VDD = 3V
DIFFERENTIAL MODE
70
04751-013
7
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VREF (V)
Figure 11. AD7938-6 ENOB vs. VREF
VDD = 5V
–0.5
–1.0
VDD = 3V
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
SINGLE-ENDED MODE
0
0.5
1.0
1.5
2.0
VREF (V)
2.5
3.0
04751-014
OFFSET (LSB)
–1.5
60
0
200
400
600
800
RIPPLE FREQUENCY (kHz)
1000
Figure 14. CMRR vs. Input Frequency with VDD = 5 V and 3 V
0
–5.0
90
04751-017
EFFECTIVE NUMBER OF BITS
DIFFERENTIAL MODE
3.5
Figure 12. AD7938-6 Offset vs. VREF
Rev. D | Page 10 of 32
1200
Data Sheet
AD7938-6
TERMINOLOGY
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, 1 LSB below
the first code transition, and full scale, 1 LSB above the last code
transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00…000) to
(00…001) from the ideal (that is, AGND + 1 LSB).
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage,
(that is, VREF).
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100…000) to (100…001) from the ideal
(that is, −VREF + 1 LSB) after the zero-code error has been
adjusted out.
Negative Gain Error Match
This is the difference in negative gain error between any
two channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × VREF,
while the signal amplitude is at 1 × VREF. See Figure 5.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, f S. The frequency
of the noise varies from 1 kHz to 1 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Zero-Code Error Match
This is the difference in zero-code error between any two channels.
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011…110) to (011…111) from the ideal (that
is, +VREF − 1 LSB) after the zero-code error has been adjusted out.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency, f S.
Positive Gain Error Match
This is the difference in positive gain error between any
two channels.
where:
CMRR (dB) = 10 log(Pf/PfS)
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Rev. D | Page 11 of 32
AD7938-6
Data Sheet
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal to Noise and Distortion Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fSAMPLE/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
The theoretical SINAD ratio for an ideal N-bit converter with a
sine wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938-6, it is defined as:
 V 2 2  V 3 2  V 4 2  V 5 2  V6 2
THD dB   20 log 

V1





where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
The AD7938-6 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are
specified separately. The intermodulation distortion is
calculated per the THD specification, as the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals, expressed in dB.
Rev. D | Page 12 of 32
Data Sheet
AD7938-6
ON-CHIP REGISTERS
The AD7938-6 has two on-chip registers that are necessary for
the operation of the device. These are the control register, which
is used to set up different operating conditions, and the shadow
register, which is used to program the analog input channels to
be converted.
pins. The control register is shown in Table 6 and the functions
of the bits are described in Table 7. At power-up, the default bit
settings in the control register are all 0s. When writing to the
control register between conversions, ensure that CONVST
returns high before the write is performed.
CONTROL REGISTER
The control register on the AD7938-6 is a 12-bit, write-only
register. Data is written to this register using the CS and WR
Table 6. Control Register Bits
MSB
DB11
PM1
DB10
PM0
DB9
CODING
DB8
REF
DB7
ADD2
DB6
ADD1
DB5
ADD0
DB4
MODE1
DB3
MODE0
DB2
SHDW
DB1
SEQ
LSB
DB0
RANGE
Table 7. Control Register Bit Function Description
Bit No.
11, 10
Mnemonic
PM1, PM0
9
CODING
8
REF
7 to 5
ADD2 to
ADD0
4, 3
MODE1,
MODE0
2
SHDW
1
SEQ
0
RANGE
Description
Power Management Bits. These two bits are used to select the power mode of operation. The user can choose
between either normal mode or various power-down modes of operation as shown in Table 8.
This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight
(natural) binary. If this bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an
external reference should be applied to the VREF pin. If this bit is Logic 1, the internal reference is selected. See the
Reference section.
These three address bits are used to either select which analog input channel is converted in the next conversion if
the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used as
described in Table 10. The selected input channel is decoded as shown in Table 9.
The two mode pins select the type of analog input on the eight VIN pins. The AD7938-6 can have either eight singleended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential inputs. See
Table 9.
The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and
access the SHDW register. See Table 10.
The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and
access the SHDW register. See Table 10.
This bit selects the analog input range of the AD7938-6. If it is set to 0, then the analog input range extends from
0 V to VREF. If it is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, VDD must
be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains
within the supply rails. See the Analog Inputs section for more information.
Table 8. Power Mode Selection using the Power Management Bits in the Control Register
PM1
0
0
PM0
0
1
Mode
Normal Mode
Autoshutdown
1
0
Autostandby
1
1
Full Shutdown
Description
When operating in normal mode, all circuitry is fully powered up at all times.
When operating in autoshutdown mode, the AD7938-6 enters full shutdown mode at the end of each
conversion. In this mode, all circuitry is powered down.
When the AD7938-6 enters this mode, all circuitry is powered down except for the reference and reference
buffer. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 µs (or 600 ns if
an external reference is used). See the Power Modes of Operation section for more information.
When the AD7938-6 enters this mode, all circuitry is powered down. The information in the control register
is retained.
Rev. D | Page 13 of 32
AD7938-6
Data Sheet
Table 9. Analog Input Type Selection
Channel Address
ADD2 ADD1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
ADD0
0
1
0
1
0
1
0
1
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
MODE0 = 1, MODE1 = 1
Eight Single-Ended
Input Channels
VIN+
VIN−
V IN0
AGND
V IN1
AGND
V IN2
AGND
V IN3
AGND
V IN4
AGND
V IN5
AGND
V IN6
AGND
V IN7
AGND
Four Fully Differential
Input Channels
VIN+
VIN−
V IN0
V IN1
V IN1
V IN0
V IN2
V IN3
V IN3
V IN2
V IN4
V IN5
V IN5
V IN4
V IN6
V IN7
V IN7
V IN6
Four Pseudo Differential Input
Channels (Pseudo Mode 1)
VIN+
VIN−
V IN0
V IN1
V IN1
V IN0
V IN2
V IN3
V IN3
V IN2
V IN4
V IN5
V IN5
V IN4
V IN6
V IN7
V IN7
V IN6
Seven Pseudo Differential
Input Channels (Pseudo Mode 2)
VIN+
VIN−
V IN0
V IN7
V IN1
V IN7
V IN2
V IN7
V IN3
V IN7
V IN4
V IN7
V IN5
V IN7
V IN6
V IN7
Not Allowed
Not Allowed
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control
register allows the user to select a particular mode of operation
of the sequencer function. Table 10 outlines the four modes of
operation of the sequencer.
Writing to the Control Register to Program the
Sequencer
The AD7938-6 needs 13 full CLKIN periods to perform a
conversion. If the ADC does not receive the full 13 CLKIN
periods, the conversion aborts. If a conversion is aborted after
applying 12.5 CLKIN periods to the ADC, ensure that a rising
edge of CONVST or a falling edge of CLKIN is applied to the
part before writing to the control register to program the
sequencer. If these conditions are not met, the sequencer will
not be in the correct state to handle being reprogrammed for
another sequence of conversions and the performance of the
converter is not guaranteed.
SHADOW REGISTER
The shadow register on the AD7938-6 is an 8-bit, write-only
register. Data is loaded from DB0 to DB7 on the rising edge of
WR. The eight LSBs load into the shadow register. The
information is written into the shadow register provided that
the SEQ and SHDW bits in the control register were set to 0 and
1, respectively, in the previous write to the control register. Each
bit represents an analog input from Channel 0 through Channel 7.
A sequence of channels can be selected through which the
AD7938-6 cycles with each consecutive conversion after the
write to the shadow register.
To select a sequence of channels to be converted, if operating in
single-ended mode or Pseudo Mode 2, the associated channel
bit in the shadow register must be set for each required analog
input. When operating in fully differential mode or Pseudo
Mode 1, the associated pair of channel bits must be set for each
pair of analog inputs required in the sequence.
With each consecutive CONVST pulse after the sequencer has
been set up, the AD7938-6 progresses through the selected
channels in ascending order, beginning with the lowest channel.
This continues until a write operation occurs with the SEQ and
SHDW bits configured in any way except 1, 0 (see Table 10).
When a sequence is set up in differential mode or Pseudo
Mode 1, the ADC does not convert on the inverse pairs (that is,
VIN1, VIN0). The bit functions of the shadow register are
outlined in Table 11. See the Analog Input Selection section for
further information on using the sequencer.
Rev. D | Page 14 of 32
Data Sheet
AD7938-6
Table 10. Sequence Selection
SEQ
SHDW
0
0
0
1
1
0
1
1
Sequence Type
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7938-6 selects the next channel for conversion.
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge (see the Shadow Register section and Table 11).
If the SEQ and SHDW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
Table 11. Shadow Register Bit Functions
MSB
DB7
VIN 7
DB6
VIN 6
DB5
VIN 5
DB4
VIN 4
DB3
VIN 3
Rev. D | Page 15 of 32
DB2
VIN 2
DB1
VIN 1
LSB
DB0
VIN 0
AD7938-6
Data Sheet
CIRCUIT INFORMATION
The AD7938-6 has eight analog input channels that can be
configured to be eight single-ended inputs, four fully differential
pairs, four pseudo differential pairs, or seven pseudo differential
inputs with respect to one common input. There is an on-chip
user-programmable channel sequencer that allows the user to select
a sequence of channels through which the ADC can progress and
cycle with each consecutive falling edge of CONVST.
The analog input range for the AD7938-6 is 0 V to VREF or 0 V to
2 × VREF depending on the status of the RANGE bit in the control
register. The output coding of the ADC can be either straight
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938-6 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming the
power management bits, PM1 and PM0, in the control register.
CONVERTER OPERATION
The AD7938-6 is a successive approximation ADC based
around two capacitive digital-to-analog converters. Figure 15
and Figure 16 show simplified schematics of the ADC in
acquisition and conversion phase, respectively. The ADC
comprises control logic, an SAR, and two capacitive digital-toanalog converters. Both figures show the operation of the ADC
in differential/pseudo differential mode. Single-ended mode
operation is similar but VIN− is internally tied to AGND. In
acquisition phase, SW3 is closed, SW1 and SW2 are in Position
A, the comparator is held in a balanced condition and the
sampling capacitor arrays acquire the differential signal on the
input.
CAPACITIVE
DAC
A
B
CONTROL
LOGIC
CS
COMPARATOR
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7938-6 is either straight binary or
twos complement, depending on the status of the CODING bit
in the control register. The designed code transitions occur at
successive LSB values (that is, 1 LSB, 2 LSBs, and so on) and the
LSB size is VREF/4096. The ideal transfer characteristics of the
AD7938-6 for both straight binary and twos complement
output coding are shown in Figure 17 and Figure 18,
respectively.
111...111
111...110
111...000
011...111
1 LSB = VREF /4096
000...010
000...001
000...000
SW1
CONTROL
LOGIC
SW2
0V
1 LSB
+VREF – 1 LSB
ANALOG INPUT
CS
VREF
SW2
CAPACITIVE
DAC
CS
SW3
VIN–
A
B
NOTE: VREF IS EITHER VREF OR 2 × VREF
COMPARATOR
CAPACITIVE
DAC
Figure 15. ADC Acquisition Phase
Rev. D | Page 16 of 32
Figure 17. AD7938-6 Ideal Transfer Characteristic
with Straight Binary Output Coding
04751-025
A
SW1
VREF
04751-023
VIN+
A
SW3
VIN–
CAPACITIVE
DAC
B
CS
B
VIN+
04751-024
The AD7938-6 provides the user with an on-chip track-and-hold,
an accurate internal reference, an analog-to-digital converter, and
a parallel interface housed in a 32-lead LFCSP or TQFP package.
When the ADC starts a conversion (see Figure 16), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
ADC CODE
The AD7938-6 is a fast, 8-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter. The part
can operate from a 2.7 V to 5.25 V power supply and features
throughput rates up to 625 kSPS.
Data Sheet
AD7938-6
ANALOG INPUT STRUCTURE
1 LSB = 2 × VREF /4096
Figure 20 shows the equivalent circuit of the analog input
structure of the AD7938-6 in differential/pseudo differential
mode. In single-ended mode, VIN− is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
011...111
000...001
000...000
111...111
100...010
100...001
–VREF + 1 LSB
VREF
+VREF – 1 LSB
04751-026
100...000
Figure 18. AD7938-6 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 19 shows a typical connection diagram for the
AD7938-6. The AGND and DGND pins are connected together
at the device for good noise suppression. The VREFIN/VREFOUT pin
is decoupled to AGND with a 0.47 μF capacitor to avoid noise
pickup if the internal reference is used. Alternatively, VREFIN/VREFOUT
can be connected to an external reference source. In this case,
the reference pin should be decoupled with a 0.1 μF capacitor.
In both cases, the analog input range can either be 0 V to VREF
(RANGE bit = 0) or 0 V to 2 × VREF (RANGE bit = 1). The
analog input configuration can be either eight single-ended
inputs, four differential pairs, four pseudo differential pairs, or
seven pseudo differential inputs (see Table 9). The VDD pin is
connected to either a 3 V or 5 V supply. The voltage applied to
the VDRIVE input controls the voltage of the digital interface and
here, it is connected to the same 3 V supply of the microprocessor
to allow a 3 V logic interface (see the Digital Inputs section).
0.1µF
The C1 capacitors in Figure 20 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC sampling capacitors and
typically have a capacitance of 45 pF.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
VDD
D
VIN+
C1
3V/5V
SUPPLY
10µF
VIN–
C1
MICROCONTROLLER/
MICROPROCESSOR
W/B
CLKIN
CS
0 TO VREF /
0 TO 2 × VREF
RD
WR
BUSY
VIN7
CONVST
DB0
AGND
DGND
0.1µF
10µF
3V
SUPPLY
0.1µF EXTERNAL VREF
0.47µF INTERNAL VREF
04751-027
2.5V
VREF
VDRIVE
C2
D
Figure 20. Equivalent Analog Input Circuit,
Conversion Phase: Switches Open, Track Phase: Switches Closed
DB11/DB9
VREFIN/VREFOUT
R1
VDD
AD7938-6
VIN0
C2
D
D
VDD
R1
04751-028
ADC CODE
011...110
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 21 and Figure 22 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and VDD = 3 V in single-ended mode
and differential mode, respectively.
Figure 19. Typical Connection Diagram
Rev. D | Page 17 of 32
AD7938-6
Data Sheet
–40
FIN = 50kHz
–45
ANALOG INPUTS
VDD = 3V
The AD7938-6 has software-selectable analog input
configurations. The user can choose either eight single-ended
inputs, four fully differential pairs, four pseudo differential
pairs, or seven pseudo differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 9).
–50
–60
VDD = 5V
–65
–70
–75
Single-Ended Mode
–80
The AD7938-6 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An op amp suitable for this function is
the AD8021. The analog input range can be programmed to be
either 0 V to VREF or 0 V to 2 × VREF.
04751-018
–85
–90
10
100
1k
10k
RSOURCE (Ω)
Figure 21. THD vs. Source Impedance in Single-Ended Mode
–60
FIN = 50kHz
–65
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
–70
THD (dB)
–75
–80
–85
VDD = 3V
–90
VDD = 5V
04751-019
–95
–100
10
100
1k
10k
RSOURCE (Ω)
Figure 24 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7938-6. In cases where the analog input
amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7938-6 is a signal ranging from 0 V to 5 V. In this case,
the 2 × VREF mode can be used.
R
Figure 22. THD vs. Source Impedance in Differential Mode
Figure 23 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 625 kHz with
an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
+1.25V
0V
–1.25V
VIN
R
3R
VIN0
VIN7
VREFOUT
VDD = 3V
SINGLE-ENDED MODE
–60
0.47µF
VDD = 5V
SINGLE-ENDED MODE
–70
THD (dB)
0V
AD7938-6*
–50
–80
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 24. Single-Ended Mode Connection Diagram
VDD = 5V/3V
DIFFERENTIAL MODE
–90
Differential Mode
–110
04751-020
–100
–120
+2.5V
FSAMPLE = 625kSPS
RANGE = 0 TO VREF
0
100
200
300
400
500
INPUT FREQUENCY (kHz)
600
700
Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages
The AD7938-6 can have four fully differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 25 defines the fully differential analog
input of the AD7938-6.
Rev. D | Page 18 of 32
04751-031
THD (dB)
–55
Data Sheet
AD7938-6
4.5
TA = 25°C
VIN+
4.0
*ADDITIONAL PINS OMITTED FOR CLARITY.
04751-032
COMMON-MODE
VOLTAGE
VIN–
Figure 25. Differential Input Definition
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN− pins in each differential
pair (that is, VIN+ − VIN−). VIN+ and VIN− should be simultaneously
driven by two signals each of amplitude VREF (or 2 × VREF,
depending on the range chosen) that are 180° out of phase. The
amplitude of the differential signal is therefore −VREF to +VREF
peak-to-peak (that is, 2 × VREF). This is regardless of the
common mode (CM). The common mode is the average of the
two signals (that is, (VIN+ + VIN−)/2) and is therefore the voltage
on which the two inputs are centered. This results in the span of
each input being CM ± VREF/2. This voltage has to be set up
externally and its range varies with the reference value VREF.
As the value of VREF increases, the common-mode range
decreases. When driving the inputs with an amplifier, the
actual common-mode range is determined by the amplifier’s
output voltage swing.
Figure 26 and Figure 27 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 V
to VREF range or 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of the
AD7938-6.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the
2 × VREF range is used, the input signal amplitude extends from
−2 VREF to +2 VREF after conversion.
3.5
TA = 25°C
COMMON-MODE RANGE (V)
3.0
2.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
VREF (V)
Figure 27. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Since not
all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-todifferential conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7938-6. The
circuit configurations shown in Figure 28 and Figure 29 show
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
that can be used in this configuration to provide differential
drive to the AD7938-6 is the AD8022.
It is advisable to take care when choosing the op amp; the
selection depends on the required power supply and system
performance objectives. The driver circuits in Figure 28 and
Figure 29 are optimized for dc coupling applications requiring
best distortion performance.
2.0
1.5
1.0
04751-033
0.5
0
3.5
04751-034
AD7938-6*
VREF
p-p
COMMON-MODE RANGE (V)
VREF
p-p
0
0.5
1.0
1.5
VREF (V)
2.0
2.5
3.0
Figure 26. Input Common-Mode Range vs. VREF (0 V to VREF Range, VDD = 5 V)
The differential op amp driver circuit in Figure 28 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
The circuit configuration shown in Figure 29 converts a
unipolar, single-ended signal into a differential signal.
Rev. D | Page 19 of 32
AD7938-6
Data Sheet
220Ω
is −0.1 V to +0.4 V; however, typically this range can extend to
−0.3 V to +0.7 V when VDD = 3 V, or −0.3 V to +1.8 V when
VDD = 5 V. Figure 30 shows a connection diagram for pseudo
differential mode.
2 × VREF p-p
V+
27Ω
V–
220Ω
3.75V
2.5V
1.25V
VIN+
220Ω
AD7938-6
VREF p-p
VIN+
220Ω
V+
20kΩ
27Ω
V–
VREF
AD7938-6*
VIN–
VREF
0.47µF
10kΩ
DC INPUT
VOLTAGE
04751-035
A
3.75V
2.5V
1.25V
VIN–
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
0.47µF
04751-037
440Ω
GND
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. Pseudo Differential Mode Connection Diagram
220Ω
ANALOG INPUT SELECTION
VREF p-p
440Ω
V+
27Ω
GND
V–
3.75V
2.5V
1.25V
As shown in Table 9, the user can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
VIN+
220Ω
AD7938-6
220Ω
A
20kΩ
27Ω
V–
10kΩ
3.75V
2.5V
1.25V
VIN–
VREF
Traditional Multichannel Operation (SEQ = 0, SHDW = 0)
0.47µF
04751-036
V+
Figure 29. Dual Op Amp Circuit to Convert a Single-Ended
Unipolar Signal into a Differential Signal
Another method of driving the AD7938-6 is to use the AD8138
(or equivalent) differential amplifier. The AD8138 can be used
as a single-ended-to-differential amplifier or as a differential-todifferential amplifier. The device is as easy to use as an op amp
and greatly simplifies differential signal amplification and driving.
Any one of eight analog input channels or four pairs of channels
can be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 31 shows a flow chart of this
mode of operation. The channel configurations are shown in
Table 9.
POWER ON
Pseudo Differential Mode
The AD7938-6 can have four pseudo differential pairs (Pseudo
Mode 1) or seven pseudo differential inputs (Pseudo Mode 2)
by setting the MODE0 and MODE1 bits in the control register
to 1, 0 and 1, 1, respectively. In the case of the four pseudo
differential pairs, VIN+ is connected to the signal source, which
must have an amplitude of VREF (or 2 × VREF depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to the VIN− pin. The voltage applied to this
input provides an offset from ground or a pseudo ground for
the VIN+ input. In the case of the seven pseudo differential
inputs, the seven analog input signals inputs are referred to a dc
voltage applied to VIN7.
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground allowing
dc common-mode voltages to be cancelled. The specified
voltage range for the VIN− pin while in pseudo differential mode
Rev. D | Page 20 of 32
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
04751-038
VREF
Figure 31. Traditional Multichannel Operation Flow Chart
Data Sheet
AD7938-6
The AD7938-6 can be configured to automatically cycle through a
number of selected channels using the on-chip programmable
sequencer by setting SEQ = 0 and SHDW = 1 in the control
register. The analog input channels to be converted are selected
by setting the relevant bits in the shadow register to 1 (see
Table 11).
control register is written to, the next conversion is on Channel
0, then Channel 1, and so on until the channel selected by the
address bits (ADD2 to ADD0) is reached. The cycle begins
again provided the WR input is tied high. If low, the SEQ and
SHDW bits must be set to 1, 0 to allow the ADC to continue its
preprogrammed sequence uninterrupted. Figure 33 shows the
flow chart of the consecutive sequence mode.
POWER ON
Once the shadow register has been programmed with the required
sequence, the next conversion executed is on the lowest channel
programmed in the SHDW register. The next conversion
executed is on the next highest channel in the sequence, and so
on. When the last channel in the sequence is converted, the
internal multiplexer returns to the first channel selected in the
shadow register and commences the sequence again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted.
If the control register is written to at any time during the
sequence, ensure that the SEQ and SHDW bits are set
to 1, 0 to avoid interrupting the conversion sequence. The
sequence program remains in force until such time as the
AD7938-6 is written to and the SEQ and SHDW bits are
configured with any bit combination except 1, 0. Figure 32
shows a flow chart of the programmable sequence operation.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = 0 SHDW = 1.
INITIATE A WRITE CYCLE.
THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.
SET RELEVANT BITS TO SELECT
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
WITH EACH CONVST PULSE
BUT ALLOWS THE RANGE,
CODING, ANALOG INPUT TYPE,
ETC BITS IN THE CONTROL
REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC BITS IN THE
CONTROL REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
Figure 33. Consecutive Sequence Mode Flow Chart
REFERENCE
The AD7938-6 can operate with either the on-chip reference or
external reference. The internal reference is selected by setting
the REF bit in the internal control register to 1. A block diagram
of the internal reference circuitry is shown in Figure 34. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal
reference, the VREFIN/VREFOUT pin should be decoupled to AGND
with a 0.47 μF capacitor. This internal reference not only
provides the reference for the analog-to-digital conversion, but
it can also be used externally in the system. It is recommended
that the reference output be buffered using an external precision
op amp before applying it anywhere in the system.
BUFFER
REFERENCE
VREFIN/
VREFOUT
ADC
Figure 32. Programmable Sequence Flow Chart
AD7938-6
04751-041
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
IN THE SHADOW REGISTER
WITH EACH CONVST PULSE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
04751-039
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ = 1 SHDW = 1.
04751-040
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1 )
Figure 34. Internal Reference Circuit Block Diagram
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register.
This is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. In this mode, once the
Alternatively, an external reference can be applied to the
VREFIN/VREFOUT pin of the AD7938-6. An external reference input
is selected by setting the REF bit in the internal control register
to 0. The external reference input range is 0.1 V to VDD. It is
important to ensure that, when choosing the reference value,
the maximum analog input range (VIN MAX) is never greater than
VDD + 0.3 V to comply with the maximum ratings of the device.
Rev. D | Page 21 of 32
AD7938-6
Data Sheet
For example, if operating in differential mode and the reference
is sourced from VDD, the 0 V to 2 × VREF range cannot be used.
This is because the analog input signal range now extends to 2 ×
VDD, which exceeds maximum rating conditions. In the pseudo
differential modes, the user must ensure that VREF + VIN− ≤ VDD
when using the 0 V to VREF range, or when using the 2 × VREF
range that 2 × VREF +VIN− ≤ VDD.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 10 to Figure 12. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7938-6 transfer function and add to specified full-scale
errors on the part.
Table 12 lists examples of suitable voltage references from
Analog Devices that can be used. Figure 35 shows a typical
connection diagram for an external reference.
Output
Voltage
2.5/3
2.5
2.048
Initial Accuracy
(% Maximum)
0.04
0.04
0.05
Operating
Current (µA)
1000
500
500
NC
0.1µF
10nF
0.1µF
1
Another advantage of the digital inputs not being restricted by
the VDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before VDD,
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to VDD.
VDRIVE Input
The AD7938-6 has a VDRIVE feature. VDRIVE controls the voltage
at which the parallel interface operates. VDRIVE allows the ADC
to easily interface to 3 V and 5 V processors.
AD7938-6*
AD780
VDD
The digital inputs applied to the AD7938-6 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs.
For example, if the AD7938-6 is operated with an AVDD of 5 V
and the VDRIVE pin is powered from a 3 V supply, the AD7938-6
has better dynamic performance with a VDD of 5 V while still
being able to interface directly to 3 V processors. Care should
be taken to ensure VDRIVE does not exceed VDD by more than
0.3 V (see the Absolute Maximum Ratings section).
Table 12. Examples of Suitable Voltage References
Reference
AD780
ADR421
ADR420
Digital Inputs
O/PSELECT 8
2
+VIN
3
TEMP VOUT 6
4
GND
7
TRIM 5
NC
VREF
NC
2.5V
NC
0.1µF
*ADDITIONAL PINS OMITTED FOR CLARITY.
04751-042
NC = NO CONNECT
Figure 35. Typical VREF Connection Diagram
Rev. D | Page 22 of 32
Data Sheet
AD7938-6
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 12 bits of conversion data.
When power supplies are first applied to the device, a rising
edge on CONVST is necessary to put the track-and-hold into
track. The acquisition time of 125 ns minimum must be allowed
before CONVST is brought low to initiate a conversion. The
ADC then goes into hold on the falling edge of CONVST and
back into track on the 13th rising edge of CLKIN after this (see
Figure 36). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
each conversion, a rising edge on the CONVST signal is used to
power up the device.
PARALLEL INTERFACE
The AD7938-6 has a flexible, high speed, parallel interface. This
interface is 12-bits wide and is capable of operating in either
word (W/B tied high) or byte (W/B tied low) mode. The
CONVST signal is used to initiate conversions, and when
operating in autoshutdown or autostandby mode, it is used to
initiate power-up.
A falling edge on the CONVST signal is used to initiate
conversions and it puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
B
t1
A
CONVST
1
CLKIN
BUSY
2
3
4
tCONVERT
5
12
13
14
t2
t20
t3
t9
INTERNAL
TRACK/HOLD
tACQUISITION
CS
t10
RD
t12
t13
DB0 TO DB11
THREE-STATE
t11
t14
DATA
THREE-STATE
tQUIET
DB0 TO DB11
OLD DATA
DATA
Figure 36. AD7938-6 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)
Rev. D | Page 23 of 32
04751-004
WITH CS AND RD TIED LOW
AD7938-6
Data Sheet
The CS and RD signals are gated internally and the level is
triggered active low. In either word mode or byte mode, CS and
RD can be tied together as the timing specifications for t10 and
t11 are 0 ns minimum. This means the bus would be constantly
driven by the AD7938-6.
Reading Data from the AD7938-6
With the W/B pin tied logic high, the AD7938-6 interface operates
in word mode. In this case, a single read operation from the
device accesses the conversion data-word on Pin DB0 to Pin
DB11. The DB8/HBEN pin assumes its DB8 function. With the
W/B pin tied to logic low, the AD7938-6 interface operates in
byte mode. In this case, the DB8/HBEN pin assumes its HBEN
function. Conversion data from the AD7938-6 must be accessed
in two read operations with eight bits of data provided on DB0
to DB7 for each of the read operations. The HBEN pin determines
whether the read operation accesses the high byte or the low
byte of the12-bit word. For a low byte read, DB0 to DB7 provide
the eight LSBs of the 12-bit word. For a high byte read, DB0 to
DB3 provide the four MSBs of the 12-bit word, DB4 to DB6
provide the Channel ID and DB7 is always a 0. Figure 36 shows
the read cycle timing diagram for a 12-bit transfer. When operating
in word mode, the HBEN input does not exist, and only the first
read operation is required to access data from the device. When
operating in byte mode, the two read cycles shown in Figure 37
are required to access the full data-word from the device.
The data is placed onto the data bus a time, t13, after both CS
and RD go low. The RD rising edge can be used to latch data
out of the device. After a time, t14, the data lines become
three-stated.
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time this causes
a degradation in linearity performance of approximately 0.25 LSB.
Reading during conversion by way of tying CS and RD low does
not cause any degradation.
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
t13
DB0 TO DB7
t14
LOW BYTE
HIGH BYTE
Figure 37. AD7938-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
Rev. D | Page 24 of 32
04751-005
RD
Data Sheet
AD7938-6
does not exist and only one write operation is required to write
the word of data to the device. Data should be provided on DB0
to DB11. When operating in byte mode, the two write cycles
shown in Figure 39 are required to write the full data-word to
the AD7938-6. In Figure 39, the first write transfers the lower
eight bits of the data-word from DB0 to DB7, and the second
write transfers the upper four bits of the data-word. When
writing to the AD7938-6, the top four bits in the high byte must
be 0s.
Writing Data to the AD7938-6
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938-6. The DB8/HBEN pin assumes its DB8 function. Data
written to the AD7938-6 should be provided on the DB0 to
DB11 inputs with DB0 being the LSB of the data-word. With
W/B tied logic low, the AD7938-6 requires two write operations
to transfer a full 12-bit word. DB8/HBEN assumes its HBEN
function. Data written to the AD7938-6 should be provided on
the DB0 to DB7 inputs. HBEN determines whether the byte
written is high byte or low byte data. The low byte of the dataword should be written first with DB0 being the LSB of the full
data-word. For the high byte write, HBEN should be high and
the data on the DB0 input should be Bit 8 of the 12-bit word. In
both word mode and byte mode, a single write operation to the
shadow register is always sufficient since it is only 8-bits wide.
The data is latched into the device on the rising edge of WR.
The data needs to be set up a time, t7, before the WR rising edge
and held for a time, t8, after the WR rising edge. The CS and
WR signals are gated internally. CS and WR can be tied
together as the timing specifications for t4 and t5 are 0 ns
minimum (assuming CS and RD have not already been tied
together).
Figure 38 shows the write cycle timing diagram of the AD7938-6
in word mode. When operating in word mode, the HBEN input
CS
t5
t6
t8
t7
DB0 TO DB11
04751-002
t4
WR
DATA
Figure 38. AD7938-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
t7
DB0 TO DB11
t8
LOW BYTE
HIGH BYTE
Figure 39. AD7938-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
Rev. D | Page 25 of 32
04751-003
WR
AD7938-6
Data Sheet
POWER MODES OF OPERATION
Autostandby (PM1 = 1; PM0 = 0)
The AD7938-6 has four different power modes of operation.
These modes are designed to provide flexible power
management options. Different options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 8. When power is first applied to the
AD7938-6 an on-chip, power-on reset circuit ensures that the
default power-up condition is normal mode.
In this mode of operation, the AD7938-6 automatically enters
standby mode at the end of each conversion, which is shown as
Point A in Figure 36. When this mode is entered, all circuitry
on the AD7938-6 is powered down except for the reference and
reference buffer. The track-and-hold goes into hold at this point
also and remains in hold as long as the device is in standby. The
part remains in standby until the next rising edge of CONVST
powers up the device. The power-up time required depends on
whether the internal or external reference is used. With an
external reference, the power-up time required is a minimum of
600 ns, while when using the internal reference, the power-up
time required is a minimum of 7 μs. The user should ensure this
power-up time has elapsed before initiating another conversion
as shown in Figure 40. This rising edge of CONVST also places
the track-and-hold back into track mode.
Note that, after power-on, the track-and-hold is in hold mode
and the first rising edge of CONVST places the track-and-hold
into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance. The user does not have to worry about any
power-up times associated with the AD7938-6 because it
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7938-6 automatically enters
full shutdown at the end of each conversion, which is shown at
Point A in Figure 36 and Figure 40. In shutdown mode, all
internal circuitry on the device is powered down. The part
retains information in the control register during shutdown.
The track-and-hold also goes into hold at this point and
remains in hold as long as the device is in shutdown. The
AD7938-6 remains in shutdown mode until the next rising
edge of CONVST (see Point B in Figure 36 and Figure 40). In
order to keep the device in shutdown for as long as possible,
CONVST should idle low between conversions, as shown in
Figure 40. On this rising edge, the part begins to power-up and
the track-and-hold returns to track mode. The power-up time
required is 10 ms minimum regardless of whether the user is
operating with the internal or external reference. The user
should ensure that the power-up time has elapsed before
initiating a conversion.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the AD7938-6
is powered down upon completion of the write operation, that
is, on the rising edge of WR. The track-and-hold enters hold
mode at this point. The part retains the information in the
control register while the part is in shutdown. The AD7938-6
remains in full shutdown mode, with the track-and-hold in
hold mode, until the power management bits (PM1 and PM0)
in the control register are changed. If a write to the control
register occurs while the part is in full shutdown mode, and the
power management bits are changed to PM0 = PM1 = 0, that is,
normal mode, the part begins to power-up on the WR rising
edge and the track-and-hold returns to track. To ensure the part
is fully powered up before a conversion is initiated, the powerup time of 10 ms minimum should be allowed before the next
CONVST falling edge; otherwise, invalid data is read.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
04751-049
CLKIN
BUSY
Figure 40. Autoshutdown/Autostandby Mode
Rev. D | Page 26 of 32
Data Sheet
AD7938-6
7
POWER vs. THROUGHPUT RATE
TA = 25°C
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938-6 remains in standby for a
greater length of time in every cycle. Additionally, the current
consumption, when converting, would be lower than the
specified maximum of 1.5 mA with VDD = 5 V, or 1.2 mA with
VDD = 3 V.
Figure 42 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and
VDD = 3 V. Again, when using an external reference, the current
consumption when converting will be lower than the specified
maximum. In both plots, the figures apply when using the
internal reference.
VDD = 5V
5
4
3
VDD = 3V
2
1
0
04751-030
For example, if the device runs at a throughput rate of 10 kSPS,
then the overall cycle time would be 100 μs. If the maximum
CLKIN frequency of 10 MHz is used, the conversion time accounts
for only 1.315 μs of the overall cycle time while the AD7938-6
remains in standby mode for the remainder of the cycle.
6
POWER (mW)
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938-6 is only powered up for
the duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 41 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V.
0
100
200
300
400
500
THROUGHPUT (kSPS)
600
700
Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7938-6 to ADSP-21xx Interface
Figure 43 shows the AD7938-6 interfaced to the ADSP-21xx
series of DSPs as a memory mapped device. A single wait state
may be necessary to interface the AD7938-6 to the ADSP-21xx
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family User’s Manual for
details). The following instruction reads from the AD7938-6:
MR = DM (ADC)
where ADC is the address of the AD7938-6.
DSP/USER SYSTEM
2.0
TA = 25°C
A0 TO A15
1.6
DMS
ADDRESS
DECODER
CS
1.2
IRQ2
1.0
WR
WR
RD
RD
0.8
0.6
DB0 TO DB11
D0 TO D23
0.4
0.2
0
BUSY
VDD = 3V
04751-029
POWER (mW)
AD7938-6*
ADSP-21xx*
VDD = 5V
1.4
CONVST
ADDRESS BUS
0
20
40
60
80
THROUGHPUT (kSPS)
100
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
120
Figure 41. Power vs. Throughput in Autostandby
Mode Using Internal Reference
Rev. D | Page 27 of 32
Figure 43. Interfacing to the ADSP-21xx
04751-045
1.8
AD7938-6
Data Sheet
DSP/USER SYSTEM
AD7938-6 to ADSP-21065L Interface
Figure 44 shows a typical interface between the AD7938-6 and
the ADSP-21065L SHARC® processor. This interface is an
example of one of three DMA handshake modes. The MSx
control line is actually three memory select lines. Internal
ADDR25 to 24 are decoded into MS3 to 0, these lines are then
asserted as chip selects. The DMAR1 (DMA request 1) is used in
this setup as the interrupt to signal the end of conversion. The
rest of the interface is a standard handshaking operation.
A0 TO A15
TMS32020/
TMS320C25/
TMS320C50*
IS
CONVST
ADDRESS BUS
AD7938-6*
ADDRESS
EN DECODER
CS
READY
TMS320C25
ONLY
MSC
STRB
WR
R/W
DSP/USER SYSTEM
RD
INTX
BUSY
DMD0 TO DMD15
MSX
ADDRESS
LATCH
AD7938-6*
ADDRESS
DECODER
DMAR1
Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x
CS
AD7938-6 to 80C186 Interface
BUSY
RD
RD
WR
WR
DB0 TO DB11
DATA BUS
04751-046
D0 TO D31
DB11 TO DB0
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADSP-21065L*
DATA BUS
04751-047
CONVST
ADDRESS BUS
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 44. Interfacing to the ADSP-21065L
AD7938-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7938-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 45. The memory mapped address chosen for the AD7938-6
should be chosen to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7938-6 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the RD
and the WR lines when interfacing to the TMS320C25, then
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
User’s Guide for details).
Figure 46 shows the AD7938-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
MICROPROCESSOR/
USER SYSTEM
AD0 TO AD15
A16 TO A19
ALE
ADDRESS/DATA BUS
CONVST
ADDRESS
LATCH
AD7938-6*
ADDRESS BUS
80C186*
ADDRESS
DECODER
DRQ1
Q
CS
R
S
BUSY
RD
RD
WR
WR
DATA BUS
Data is read from the ADC using the following instruction
*ADDITIONAL PINS OMITTED FOR CLARITY
IN D, ADC
Figure 46. Interfacing to the 80C186
where:
D is the data memory address.
ADC is the AD7938-6 address.
Rev. D | Page 28 of 32
DB0 TO DB11
04751-048
A0 TO A23
Data Sheet
AD7938-6
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7938-6 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Generally, a
minimum etch technique is best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the ground pins on the
AD7938-6 as possible. Avoid running digital lines under the
device as this couples noise onto the die. The analog ground
plane should be allowed to run under the AD7938-6 to avoid
noise coupling. The power supply lines to the AD7938-6 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best performance
from these decoupling components, they must be placed as
close as possible to the device, ideally right up against the
device. The 0.1 µF capacitors should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types or surface-mount types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the chip scale package has a thermal pad. The
thermal pad on the printed circuit board should be at least as
large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided. Thermal vias can be used on the printed
circuit board thermal pad to improve thermal performance of
the package. If vias are used, they should be incorporated in the
thermal pad at 1.2 mm pitch grid. The via diameter should be
between 0.3 mm and 0.33 mm, and the via barrel should be
plated with 1 oz. copper to plug the via. The user should
connect the printed circuit board thermal pad to AGND.
EVALUATING THE AD7938-6 PERFORMANCE
The recommended layout for the AD7938-6 is outlined in the
evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7938-6
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7938-6.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7938-6.
The software and documentation are on the CD that ships with
the evaluation board.
Rev. D | Page 29 of 32
AD7938-6
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
PIN 1
INDICATOR
0.30
0.25
0.18
1
24
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
9
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
112408-A
0.80
0.75
0.70
8
16
0.50
0.40
0.30
TOP VIEW
PIN 1
INDICATOR
32
25
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00 BSC SQ
25
32
24
1
PIN 1
7.00
BSC SQ
TOP VIEW
0° MIN
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
VIEW A
17
8
9
VIEW A
0.80
BSC
LEAD PITCH
ROTATED 90° CCW
16
0.45
0.37
0.30
COMPLIANT TO JEDEC STANDARDS MS-026-AB A
Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
Rev. D | Page 30 of 32
020607-A
1.05
1.00
0.95
0.15
0.05
(PINS DOWN)
Data Sheet
AD7938-6
ORDERING GUIDE
Model 1
AD7938BCPZ-6
AD7938BCPZ-6REEL7
AD7938BSUZ-6
AD7938BSUZ-6REEL7
1
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Linearity Error (LSB) 2
±1
±1
±1
±1
Z = RoHS Compliant Part.
Linearity error here refers to integral linearity error.
Rev. D | Page 31 of 32
Package Description
32-Lead LFCSP
32-Lead LFCSP
32-Lead TQFP
32-Lead TQFP
Package Option
CP-32-7
CP-32-7
SU-32-2
SU-32-2
AD7938-6
Data Sheet
NOTES
©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04751-0-1/17(D)
Rev. D | Page 32 of 32