Samsung K4Y50024UC 512mbit xdr tm dram(c-die) Datasheet

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDRTM DRAM
TM
512Mbit XDR
DRAM(C-die)
Revision 1.1
August 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
XDR is a trademark of Rambus Inc.
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Change History
Revision
Month
Year
History
1.0
December
2005
- First Copy
- Based on the Rambus XDRTM DRAM Datasheet Version 0.88
1.1
August
2006
- Add comment on page 5
- Add TMIN on Table13, page 57
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0.0 Overview
The XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications,
including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.
The 512Mb XDR DRAM device is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling
Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s.
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The device’s eight banks support up
to four interleaved transactions.
1.0 Features
♦ Highest pin bandwidth available
- 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
♦ Bi-directional differential RSL(DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
♦ On-chip termination
- Adaptive impedance matching
- Reduced system cost and routing complexity
♦ Highest sustained bandwidth per DRAM device
- Up to 8000 MB/s sustained data rate
- Eight banks : bank-interleaved transaction at full bandwidth
- Dynamic request scheduling
- Early-read-after-write support for maximum efficiency
- Zero overhead refresh
♦ Low Latency
- 2.0/2.5/3.33ns request packets
- Point-to-point data interconnect for fastest possible flight time
- Support for low-latency, fast-cycle cores
♦ Low Power
- 1.8V VDD
- Programmable small-swing I/O signaling(DRSL)
- Low power PLL/DLL design
- Powerdown self-refresh support
- Per pin I/O powerdown for narrow-width operation
♦ 0.49us refresh intervals(32K/16ms refresh)
♦ RoHS compliant
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2.0 Key Timing Parameters/Part Numbers
Organization
32Mx16
64Mx8
128Mx4
256Mx2
Bandwidth (1/tBIT)a
Latency(tRAC)b
Binc
Part Number
2400
36
A
K4Y50164UC-JCA2
3200
35
B
K4Y50164UC-JCB3
4000
28
C
K4Y50164UC-JCC4
2400
36
A
K4Y50084UC-JCA2
3200
35
B
K4Y50084UC-JCB3
4000
28
C
K4Y50084UC-JCC4
2400
36
A
K4Y50044UC-JCA2
3200
35
B
K4Y50044UC-JCB3
4000
28
C
K4Y50044UC-JCC4
2400
36
A
K4Y50024UC-JCA2
3200
35
B
K4Y50024UC-JCB3
4000
28
C
K4Y50024UC-JCC4
a.Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 58 and “ Timing Characteristics” on page 60.
Note that tBIT=tCYCLE/8
b.Read access time tRAC (= tRCD-R+tCAC) measured in ns. See “Timing Parameters” on page 61.
c.Timing parameter bin. See “Timing Parameters” on page 61. This is a measure of the number of interleaved read transactions needed
for maximum efficiency (the value Ceiling(tRC-R/tRR-D). For bin A, tRC-R/tRR-D=4, and for bin B, tRC-R/tRR-D=5 for bin C, tRC-R/tRR-D =6.
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3.0 General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal
memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a
signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus.
There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows on each signal,
while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) command. This
causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second request packet at
clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense
amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command. This causes the data packet
D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and tWRP . In
addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing of the CFM/
CFMN clock edges is constrained by tCYCLE.
Figure 1 : XDR DRAM Device Write and Read Transactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
WR
WR
RQ11..0 ACT
a0 a1
a2
tRCD-W tCC
DQ15..0
tCWD
DQN15..0
D(a1)
tCYCLE
PRE
a3
tWRP
D(a2)
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0 ACT
a0
DQ15..0
DQN15..0
RD
a1
tRCD-R
RD
a2
tCC
tRDP
tCAC
Transaction a: RD
tCYCLE
PRE
a3
a0 = {Ba,Ra}
Q(a1)
Q(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command.
This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet
at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final
request packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and tRDP . In
addition, the spacing between the request and data packets are constrained by the tCAC parameter.
* Any system or application incorporating random access memory products should be properly designed, tested and qualified to ensure
proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or
addresses may result in reduction of product life.
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4.0 Pinouts and Definitions
The following table shows the pin assignment of 512Mb x16 XDR DRAM Package. The mechanical dimensions of this package are
shown on page 72. Note - Pin #1 is at the A1 postion.
Table 1-1 : x16 Package Pinout(Top View) : 104ball FBGA Package
16
DQ10
DQ0
SDO
15
DQN10
DQN0
RST
VDD
GND
VDD
VDD
GND
DQ1
DQ11
SCK
DQN1
DQN11
14
DQ6
DQ12
GND
RQ2
RQ5
RQ6
RQ8
CMD
DQ13
DQ7
13
DQN6
DQN12
VDD
RQ1
VREF
RQ7
RQ9
VDD
DQN13
DQN7
GND
VDD
GND
GND
VDD
GND
VDD
VDD
GND
GND
GND
12
VDD
GND
11
GND
VTERM
6
GND
GND
5
VDD
VDD
VTERM
VDD
GND
GND
VDD
VTERM
GND
GND
GND
VDD
VDD
10
9
8
7
VDD
VTERM
4
DQ14
DQ4
GND
RQ3
RSRV
CFMN
RQ11
GND
DQ5
DQ15
3
DQN14
DQN4
RQ0
RQ4
RSRV
CFM
RQ10
VDD
DQN5
DQN15
2
DQ2
DQ8
GND
VDD
DQ9
DQ3
1
DQN2
DQN8
SDI
VDD
GND
Top View
A
B
C
D
E
F
VDD
GND
VDD
DQN9
DQN3
G
H
J
K
L
ROW
COL
Top View
SAMSUNG
SAMSUNG 520
401
040
K4Y50164UCK4Y5017UM - JCB3
K4R
JCC4
PC
Chip
The pin #1(ROW1, COLA) is located at the A1
position on the top side and the A1 position is
marked by the marker “ ”.
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XDRTM DRAM
The following table shows the pin assignment of 512Mb x8 XDR DRAM Package. The mechanical dimensions of this package are
shown on page 72. Note - Pin #1 is at the A1 postion.
Table 1-2 : x8 Package Pinout(Top View) : 104ball FBGA Package
16
RSRV
DQ0
SDO
15
RSRV
DQN0
RST
14
DQ6
RSRV
GND
RQ2
RQ5
RQ6
RQ8
CMD
RSRV
DQ7
13
DQN6
RSRV
VDD
RQ1
VREF
RQ7
RQ9
VDD
RSRV
DQN7
GND
VDD
GND
GND
VDD
GND
VDD
VDD
GND
GND
GND
12
VDD
GND
11
GND
VTERM
6
GND
GND
5
VDD
VDD
VTERM
VDD
GND
VDD
VDD
VDD
GND
DQ1
RSRV
SCK
DQN1
RSRV
GND
GND
VDD
VTERM
GND
GND
GND
VDD
VDD
10
9
8
7
VDD
VTERM
4
RSRV
DQ4
GND
RQ3
RSRV
CFMN
RQ11
GND
DQ5
RSRV
3
RSRV
DQN4
RQ0
RQ4
RSRV
CFM
RQ10
VDD
DQN5
RSRV
2
DQ2
RSRV
GND
VDD
RSRV
DQ3
1
DQN2
RSRV
SDI
VDD
GND
Top View
A
B
C
D
E
F
VDD
GND
VDD
RSRV
DQN3
G
H
J
K
L
ROW
COL
Top View
520
SAMSUNG
SAMSUNG
040
401
K4Y50164UC
K4Y50084UC
K4Y5017UM - PC
K4R
JCC4
JCB3
Chip
The pin #1(ROW1, COLA) is located at the A1
position on the top side and the A1 position is
marked by the marker “ ”.
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XDRTM DRAM
The following table shows the pin assignment of 512Mb x4 XDR DRAM Package. The mechanical dimensions of this package are
shown on page 72. Note - Pin #1 is at the A1 postion.
Table 1-3 : x4 Package Pinout(Top View) : 104ball FBGA Package
16
RSRV
DQ0
SDO
15
RSRV
DQN0
RST
VDD
GND
VDD
VDD
GND
DQ1
RSRV
SCK
DQN1
RSRV
14
RSRV
RSRV
GND
RQ2
RQ5
RQ6
RQ8
CMD
RSRV
RSRV
13
RSRV
RSRV
VDD
RQ1
VREF
RQ7
RQ9
VDD
RSRV
RSRV
GND
VDD
GND
GND
VDD
GND
VDD
VDD
GND
GND
GND
12
VDD
GND
11
GND
VTERM
VDD
GND
GND
VDD
VTERM
GND
10
9
8
7
6
GND
GND
5
VDD
VDD
VTERM
4
RSRV
RSRV
GND
RQ3
RSRV
CFMN
3
RSRV
RSRV
RQ0
RQ4
RSRV
CFM
2
DQ2
RSRV
GND
1
DQN2
RSRV
SDI
VDD
GND
Top View
A
B
C
D
E
GND
GND
VTERM
VDD
VDD
RQ11
GND
RSRV
RSRV
RQ10
VDD
RSRV
RSRV
VDD
RSRV
DQ3
VDD
F
VDD
GND
VDD
RSRV
DQN3
G
H
J
K
L
ROW
COL
Top View
SAMSUNG
SAMSUNG 520
401
040
K4Y50164UCK4Y50044UCK4Y5017UM - PC
K4R
JCC4
JCB3
Chip
The pin #1(ROW1, COLA) is located at the A1
position on the top side and the A1 position is
marked by the marker “ ”.
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The following table shows the pin assignment of 512Mb x2 XDR DRAM Package. The mechanical dimensions of this package are
shown on page 72. Note - Pin #1 is at the A1 postion.
Table 1- 4: x2 Package Pinout(Top View) : 104ball FBGA Package
16
RSRV
DQ0
SDO
15
RSRV
DQN0
RST
VDD
GND
VDD
VDD
GND
DQ1
RSRV
SCK
DQN1
RSRV
14
RSRV
RSRV
GND
RQ2
RQ5
RQ6
RQ8
CMD
RSRV
RSRV
13
RSRV
RSRV
VDD
RQ1
VREF
RQ7
RQ9
VDD
RSRV
RSRV
GND
VDD
GND
GND
VDD
GND
VDD
VDD
GND
GND
GND
12
VDD
GND
11
GND
VTERM
VDD
GND
GND
VDD
VTERM
GND
10
9
8
7
6
GND
GND
5
VDD
VDD
VTERM
4
RSRV
RSRV
GND
RQ3
RSRV
CFMN
3
RSRV
RSRV
RQ0
RQ4
RSRV
CFM
2
RSRV
RSRV
GND
1
RSRV
RSRV
SDI
VDD
GND
Top View
A
B
C
D
E
GND
GND
VTERM
VDD
VDD
RQ11
GND
RSRV
RSRV
RQ10
VDD
RSRV
RSRV
VDD
RSRV
RSRV
VDD
F
VDD
GND
VDD
RSRV
RSRV
G
H
J
K
L
ROW
COL
Top View
520
SAMSUNG
SAMSUNG
040
401
K4Y50164UC
K4Y50024UC
K4Y5017UM - PC
K4R
JCC4
JCB3
Chip
The pin #1(ROW1, COLA) is located at the A1
position on the top side and the A1 position is
marked by the marker “ ”.
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5.0 Pin Description
Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These
include VDD and GND for the core and interface logic, VREF for receiving input signals, and VTERM for the driving output signals.
The next group of pins are used for high bandwidth memory accesses. These include DQ15 ... DQ0 and DQN15 ... DQN0 for carrying
read and write data signals, RQ11 ... RQ0 for carrying request signals, and CFM and CFMN for carrying timing information used by the
DQ, DQN and RQ signals.
The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the state of
the device, CMD for carrying command signals, SDI and SDO for carrying register read data, and SCK for carrying the timing information
used by the RST, SDI, SDO, and CMD signals.
Table 2 : Pin Description
Signal
I/O
Type
No. of pins
VDD
-
-
22
Supply voltage for the core and interface logic of the device.
GND
-
-
24
Ground reference for the core and interface logic of the device.
VREF
-
-
1
Logic threshold reference voltage for RSL signals.
VTERM
-
-
4
Termination voltage for DRSL signals.
I/O
DRSLa
16b
Positive data signals that carry write or read data to and from the device.
I/O
DRSLa
16b
Negative data signals that carry write or read data to and from the device.
RQ11..0
I
RSLa
12
Request signals that carry control and address information to the device.
CFM
I
DIFFCLKa
1
Clock from master — Positive interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
CFMN
I
DIFFCLKa
1
Clock from master — Negative interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
RST
I
RSLa
1
Reset input — This pin is used to initialize the device.
CMD
I
RSLa
1
Command input — This pin carries command, address, and control register write
data into the device.
SCK
I
RSLa
1
Serial clock input — Clock source used for reading from and writing to the control
registers.
SDI
I
RSLa
1
Serial data input — This pin carries control register read data through the device.
This pin is also used to initialize the device.
SDO
O
CMOSa
1
Serial data output — This pin carries control register read data from the device. This
pin is also used to initialize the device.
RSRVb
-
-
2b
Reserved pins — Follow Rambus XDR system design guidelines for connecting
RSRV pins
DQ15..0b
DQN15..0b
Total pin count per package
Description
104
a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
b. The number of DQ pins changes by I/O configuration. See the table below.
x16
Singnal
x8
No. of pins
Singnal
x4
No. of pins
Singnal
x2
No. of pins
Singnal
No. of pins
DQ15...0
DQN15...0
16
16
DQ7...0
DQN7...0
8
8
DQ3...0
DQN3...0
4
4
DQ1...0
DQN1...0
2
2
RSRV
2
RSRV
18
RSRV
26
RSRV
30
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6.0 Block Diagram
A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals : 1/tCYCLE,
2/tCYCLE, and 16/tCC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These virtual signals show
the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual memory component.
The RQ11 ... RQ0 pins receive the request packet. Two 12-bit words are received in one tCYCLE interval. This is indicated by the 2/tCYCLE
clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request packet. These 24bits are loaded into a register(clocked by the 1/tCYCLE clocking signal) and decoded by the Decode Block. The VREF pin supplies a reference voltage used by the
RQ receivers.
Three sets of control signals are produced by the Decode Block. These include the bank(BA) and row(R) addresses for an activate(ACT)
command, the bank(BR) and row(REFr) addresses for a refresh activate(REFA) command, the bank(BP) address for a precharge(PRE)
command, the bank(BR) adddress for a refresh precharge(REFP) command, and the bank(BC) and column(C and SC) addresses for a
read(RD) or write(WR or WRM) command. In addition, a mask(M) is used for a masked write(WRM) command.
These commands can all be optionally delayed in increments of tCYCLE under control of delay fields in the request. The control signals of
the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined
by core timing parameters, in this case 1/tRR, 1/tPP, and 1/tCC(1/4, 1/4, and 1/2 the frequency of CFM in the -3200 component). These
registers may be loaded at any tCYCLE rising edge. Once loaded, they should not be changed until a tRR, tPP, or tCC time later because
timing paths of the memory core need time to settle.
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associated sense
amp array for the bank. Sensing a row is also referred to as “Opening a page”for the bank.
Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to a state in
which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank.
After a bank is given an ACT command and before it is given a PRE command, it may receive read(RD) and write(WR) column commands.
These commands permit the data in the bank’s associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank is written
with the data received from the DQ15 ... DQ0 pins.
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is read. The
data is transmitted onto the DQ15 ... DQ0 pins.
The DQ15 ... DQ0 pins receive the write data packet(D) for a write transaction. 16 sixteen-bit words are received in one tCC interval. This
is indicated by the 16/tCC clocking signal connected to the 1:16 Demux Block that assembles the 16x16-bit write data packet. The write
data is then driven to the selected Sense Amp Array Bank.
16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15 ... DQ0 pins transmit the read
data packet(Q) in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 16:1 Mux Block. The VTERM pin supplies
a termination voltage for the DQ pins.
The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and conrol needed to write the
control registers. The read data for these registers is accessed through the SDO/SDI pins. These pins are also used to initialize the device.
The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and receive
circuits of the device. The control registers also supply bank(REFB) and row(REFr) address for refresh operations.
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Figure 2 : 512Mb (8x4Mx16) XDR DRAM Block Diagram
1:2 Demux
12
1/tCYCLE
2/tCYCLE
12
Control Registers
16/ tCC
reg
12
RST,SCK,CMD,SDI SDO
4
1
CFM CFMN
1/tCYCLE
12
Power Mode Logic
Calibration Logic
Refresh Logic
Initialization Logic
Decode
1/tRR
BA,BR,REFB
23
3
1
...
{0..1}*tCYCLE
decode
ACT delay
WIDTH
R,REFr
1
ACT
ROW
1
PRE
1
Bank 0
PRE
16x16*26
16x16*26
...
1
1
R/W
6
COL
Sense Amp 0
COL
4
16x16
8
M
16x16*26
...
SC
Sense Amp Array
R/W
Sense Amp (23 - 1)
16x16
S[15:0][15:0]
16x16
16x16
WIDTH
Byte Mask (WR)
Width Demux (WR)
16x16
...
C
3
decode
BC
23
...
1/tCC
Bank (23 - 1)
...
3
ROW
23
16x16*26*212
...
BP,BR,REFB
reg
1/tPP
Bank
Array
Bank 0
ACT
12
...
{0..3}*tCYCLE
decode
PRE delay
3
reg
12
reg
{0..1}*tCYCLE
3
reg
RD,WR
delay
3
...
6+4
REFB,REFr
ACT logic
...
7
PRE logic
Width Mux (RD)
Q[15:0][15:0]
D[15:0][15:0]
...
COL logic
16x16
16
...
2/tCYCLE
VREF
1
...
RQ11..0
12
16/tCC
16
1:16 Demux
16:1 Mux
16/tCC
16
16
termination
16
2
VTERM
DQ15..0
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7.0 Request Packets
A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet
formats, field encodings and packet interactions.
7.1 Request Packet Formats
There are five types of request packets:
1. ROWA — specifies an ACT command
2. COL — specifies RD and WR commands
3. COLM — specifies a WRM command
4. ROWP — specifies PRE and REF commands
5. COLX — specifies the remaining commands
Table 3 describes fields within different request packet types. Various request packet type formats are illustrated in Figure3.
Each packet type consists of 24 bits sampled on the RQ11..0 pins on two successive edges of the CFM/CFMN clock. The request packet
formats are distinguished by the OP3..0 field. This field also specifies the operation code of the desired command.
In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the activate (ACT) command.
In the COL packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC), and sub-opcode
(WRX) are specified for the read (RD) and write (WR) commands.
In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), and mask field (M) are specified for the
masked write (WRM) command.
In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP) are specified for the
precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the refresh (REF) commands.
In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands.
Table 3 : Request Field Description
Field
OP3..0
Packet Types
ROWA/ROWP
/COL/COLM/COLX
Description
4-bit operation code that specifies packet format.
(Encoded commands are in Table 4 on page 15.)
DELA
ROWA
Delay the associated row activate command by 0 or 1 tCYCLE .
BA2..0
ROWA
3-bit bank address for row activate command.
R11..0
ROWA
12-bit row address for row activate command.
SR1..0
ROWA
2-bit sub-row address for sub-row sensing (see “Sub-Row (Sub-Page) Sensing” on page 50)
WRX
COL
Specifies RD (=0) or WR (=1) command.
DELC
COL
Delay the column read or write command by 0 or 1 tCYCLE .
BC2..0
COL/COLM
3-bit bank address for column read or write command.
C9..4
COL/COLM
6-bit column address for column read or write command.
SC3..0
COL/COLM
4-bit subcolumn address for column read or column write command for x2/x4/x8 DQ widths.
M7..0
COLM
8-bit mask for masked-write command WRM.
POP2..0
ROWP
3-bit operation code that specifies row precharge command with a delay of 0 to 3 tCYCLE.
(Encoded commands are in Table 6 on page 16).
BP2..0
ROWP
3-bit bank address for row precharge command.
ROP2..0
ROWP
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 5 on page 15).
RA7..0
ROWP
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value)
XOP3..0
COLX
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 7 on page 16).
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Figure 3 : Request Packet Formats
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
tCYCLE
ACT
a0
RD
a1
WRM
a2
PRE
a3
PDN
-
DQ15..0
DQN15..0
ROWA Packet
COL Packet
tCYCLE
COLM Packet
tCYCLE
tCYCLE
ROWP Packet
tCYCLE
COLX Packet
tCYCLE
CFM
CFMN
RQ11
OP
3
DEL
A
OP
3
DEL
C
OP
3
M
7
OP
3
POP
2
OP
3
rsrv
RQ10
OP
2
R
8
OP
2
rsrv
M
3
M
6
OP
2
ROP
2
OP
2
rsrv
RQ9
R
9
R
7
OP
1
rsrv
M
2
M
5
OP
1
ROP
1
OP
1
rsrv
RQ8
R
10
R
6
OP
0
rsrv
M
1
M
4
OP
0
ROP
0
OP
0
rsrv
RQ7
R
11
R
5
WR
X
C
7
M
0
C
7
POP
1
RA
7
rsrv
rsrv
rsrv
R
4
C
8
C
6
C
8
C
6
POP
0
RA
6
rsrv
rsrv
rsrv
R
3
C
9
C
5
C
9
C
5
rsrv
RA
5
rsrv
rsrv
rsrv
R
2
rsrv
C
4
rsrv
C
4
rsrv
RA
4
rsrv
rsrv
rsrv
R
1
rsrv
SC
3
rsrv
SC
3
rsrv
RA
3
XOP
3
rsrv
RQ2
BA
2
R
0
BC
2
SC
2
BC
2
SC
2
BP
2
RA
2
XOP
2
rsrv
RQ1
BA
1
SR
1
BC
1
SC
1
BC
1
SC
1
BP
1
RA
1
XOP
1
rsrv
RQ0
BA
0
SR
0
BC
0
SC
0
BC
0
SC
0
BP
0
RA
0
XOP
0
rsrv
RQ6
RQ5
RQ4
RQ3
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7.2 Request Field Encoding
Operation code fields are encoded within different packet types to specify commands. Table4 through Table7 provides packet type and
encoding summaries.
Table4 shows the OP field encoding for five packet types. The COLM and ROWA packets each specify a single command : ACT and
WRM. The COL, COLX, and ROWP packets each use additional fields to specify multiple commands : WRX, XOP, and POP/ROP,
respectively. The COLM packet specifies the masked write command WRM. This is like the WR unmasked write command, except that
a mask field M7...0 indicates whether each byte of the write data packet is written or not written. The ROWA packet specifies the row
activate command ACT. The COL packet uses the WRX field to specify the column read and column write(unmasked) commands.
Table 4 : OP Field Encoding Summary
OP [3:0]
0000
0001
0010
Packet Command
-
No operation.
RD
Column read (WRX=0). Column C9..4 of sense amp in bank BC2..0 is read to DQ bus after
DELC*tCYCLE.
WR
Column write (WRX=1). Write DQ bus to column C9..4 of sense amp in bank BC2..0 after
DELC*tCYCLE.
COL
COLX
Description
NOP
CALy
XOP3..0 specifies a calibrate or powerdown command — see Table 7 on page 16.
PREx
POP2..0 specifies a row precharge command — see Table 6 on page 16.
REFy,LRRr
ROP2..0 specifies a row refresh command or load REFr register command — see Table 5
on page 15.
0011
ROWP
01xx
ROWA
ACT
Row activate command. Row R11..0 of bank BA2..0 is placed into the sense amp of the
bank after DELA*tCYCLE.
1xxx
COLM
WRM
Column write command (masked) — mask M7..0 specifies which bytes are written.
Encoding of the ROP field in the ROWP packet is shown in Table5. The first encoding specifies a NOPR (no operation) command. The
REFP command uses the RA field to select a bank to be precharged. The REFA and REFI commands use the RA field and REFH/M/L
registers to select a bank and row to be activated for refresh. The REFI command also increments the REFH/M/L register. The REFP,
REFA, and REFI commands may also be delayed by up to 3*tCYCLE using the RA[7:6] field. The LRR0, LRR1, and LRR2 commands
load the REFH/M/L registers from the RA[7:0] field.
Table 5 : ROP Field Encoding Summary
ROP[2:0]
Command
Description
000
NOPR
No operation
001
REFP
Refresh precharge command. Bank RA2..0 is precharged.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
010
REFA
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into
sense amp.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
011
REFI
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into
sense amp.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
R[11:0] field of REFH/M/L register is incremented after the activate command has completed.
100
LRR0
Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field.
101
LRR1
Load Refresh Middle Row register (REFM). RA[3:0] is stored in R[11:8] field.
110
LRR2
Load Refresh High Row register — not used with this device.
111
-
Reserved
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The REFH/M/L registers are also refreshed to as the REFr registers. Note that only the bits that are needed for specifying the refresh
row(11 bits in all) are implemented in the REFr registers - the rest are reserved. Note also that the RA2 ... RA0 field that specifies the
refresh bank address is also referred to as BR2...0. See “Refresh Transactions” on page 42.
Table6 shows the POP field encoding in the ROWP packet. The first encoding specifies a NOPP(no operation) command. There are four
variations of PRE(precharge) command. Each uses the BP field to specify the bank to be precharged. Each also specifies a different
delay of up to 3*tCYCLE using the POP[1:0] field. A precharge command may be specified in addition to a refresh command using the
ROP field.
Table 6 : POP Field Encoding Summary
POP [2:0] Command
Description
000
NOPP
No operation.
001
-
Reserved.
010
-
Reserved.
011
-
Reserved.
100
PRE0
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 0*tCYCLE.
101
PRE1
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 1*tCYCLE.
110
PRE2
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 2*tCYCLE.
111
PRE3
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 3*tCYCLE.
Table7 shows the XOP field encoding in the COLX packet. This field encodes the remaining commands.
The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See “Calibration Transactions”
on page 44.
The PDN command causes the device to enter a power-down state. See”Power State Management” on page 45.
Table 7 : XOP Field Encoding Summary
XOP
[3:0]
Command
Command and Description
XOP
[3:0]
Command
0000
-
Reserved.
1000
CALC
0001
-
Reserved.
1001
CALZ
Impedance calibration command.
0010
-
Reserved.
1010
CALE
End calibration command (CALC).
Command and Description
Current calibration command.
0011
-
Reserved.
1011
-
0100
-
Reserved.
1100
PDN
Reserved.
0101
-
Reserved.
1101
-
Reserved.
Enter powerdown power state.
0110
-
Reserved.
1110
-
Reserved.
0111
-
Reserved.
1111
-
Reserved.
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7.3 Request Packet Interactions
A summary of request packet interaction is shown in Table8. Each case is limited to request packets with commands that perform
memory operations(including refresh commands). This includes all commands in ROWA, ROWP, COL, and COLM packets. The
commands in COLX packets are described in later sections. See “Maintenance Operations” on page 42.
Request packet/command “a” is followed by request/ command “b”. The minimum possible spacing between these two packet/command
is 0*tCYCLE. However, a larger time interval may be needed because of a resource interaction between the two packet/commands. If the
minimum possible sapcing is 0*tCYCLE, then an entry of “No limit” is shown in the table.
Note that the spacing values shown in the table are relative to the effective beginning of a packet/command. The use of the delay field
with a command will delay the position of the effective packet/command from the position of the actual packet/command. See “Dynamic
Request Scheduling” on page 23 .
Any of the packet/command encoding under one of the four operation types is equivalent in terms of the resource constraints. Therefore.
both the horisontal columns(packet “a”) and vertical rows(packet “b”) of the interaction table are divided into four major groups.
The four possible operation types for request packet a and b include :
: [A] Active Row
ROWA/ACT
ROWP/REFA
ROWP/REFI
: [R] Read Column
: [W] Write Column
COL/RD
COL/WR
COLM/WRM
: [P] Precharge Row ROWP/PRE
ROWP/REFP
Table 8 : Packet Interaction Summary
Second packet/command to bank Bb
Activate Row [A]
First packet/command to bank Ba
Read Column [R]
Write Column [W]
Precharge Row [P]
ROWA - ACT Bb
ROWP - REFA Bb
ROWP - REFI Ba
COL - RD Bb
COL - WR Bb
COLM - WRM Bb
ROWP - PRE Bb
ROWP - REFP Bb
Activate Row [A]
ROWA - ACT Ba
ROWP - REFA Ba
ROWP - REFI Ba
Ba,Bb different
Case AAd: tRR
Case ARd: No limit
Case AWd: No limit
Case APd: No limit
Ba,Bb same
Case AAs: tRC
Case ARs: tRCD-R
Case AWs: tRCD-W
Case APs: tRAS
Read Column [R]
COL - RD Ba
Ba,Bb different
Case RAd: No limit
Case RRd: tCC
Case RWd:a t∆RW
Case RPd: No limit
Ba,Bb same
Case
Write Column [W]
COL - WR Ba
COLM - WRM Ba
Ba,Bb different
Precharge Row [P]
ROWP - PRE Ba
ROWP - REFP Ba
See Examples:
RAs:b
a
Case RRs: tCC
Case RWs: t∆RW
Case RPs: tRDP
Case WAd: No limit
Case WRd:c t∆WR
Case WWd: tCC
Case WPd: No limit
Ba,Bb same
Case WAsb:tWRP+tRP
Case WRs:c t∆WR
Case WWs: tCC
Case WPs: tWRP
Ba,Bb different
Case PAd: No limit
Case PRd: No limit
Case PWd: No limit
Case PPd: tPP
Ba,Bb same
Case PAs: tRP
tRDP+tRP
Case PRs:d tRP+tRCDR
Figure 4
Figure 5
Case PWs:d tRP+tRCD-W Case PPs: tRC
Figure 6
Figure 7
a. t∆RW is equal to tCC + tRW-BUB,XDRDRAM+ tCAC - tCWD and is defined in Table 18. This also depends upon propagation delay - See “Propagation Delay” on page 32.
b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands.
c. t∆RW is defined in Table 18.
d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.
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The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis at the top
of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the same, or they may be
different. These two subcases for each interaction are shown along the vertical axis on the letf.
There are 32 possible interaction cases altogether. The table gives each case a label of the form “xyz”, where “x” and “y” are one of the
four operation types(“A” for Activate, “R” for Read, “W” for Write, or “P” for Precharge) for the first and second request, respectively, and
“z” indicates the same bank(“s”) or different bank(“d”).
Along the horizontal axis at the bottom of the table are cross references to four figures(Figure4 through Figure7). Each figure illustrates
the eight cases in the corresponding vertical column. Thus, Figure4 shows the eight cases when the second request is an activate operation(“A”). In the following discussion of the cases, only those in which the interaction interval is greater than tCYCLE will be described.
7.4 Request Interactions Cases
In Figure4. the interaction interval for the AAd case is tRR. This parameter is the row-to-row time and is the minimum interval between
activate commands to different banks of a device.
The interaction interval for the AAs case is tRC. This is the row cycle time parameter and is the minimum interval between activate
commands to same banks of a device. A precharge operation must be inserted between the two activate operations.
The interaction interval for the RAs case is tRDP + tRP. A precharge operation must be inserted between the read and activate operation.
The minimum interval between a read and a precharge operation to a bank is tRDP. The minimum interval between a precharge and an
activate operation to a bank is tRP.
The interaction interval for the WAs case is tWDP + tRP. A precharge operation must be inserted between the read and the activate operation. The minimum interval between a write and a precharge operation to a bank is tWDP. The minimum interval between a precharge
and an activate operation to a bank is tRP.
The interaction interval for the PAs case is tRP. The minimum interval between a precharge and an activate operation to a bank is tRP.
In Figure5, the interaction interval for the ARs case is tRCD-R. This is the row-to-column-read time parameter and represents the
minimum interval between an activate operation and a read operation to a bank.
The interaction interval for the RRd and RRs cases is tCC. This is the column-to-column time parameter and represents the minimum
interval between two read operations.
The interaction interval for the WRd and WRs cases is t∆WR. This is the write-to-read time parameter and represents the minimum
interval between a write and a read operation to any banks. See “Read/Write Interaction” on page 31.
The interaction interval for the PRs case is tRP + tRCD-R. An activate operation must be inserted between the precharge and the read
operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval between an activate and a read operation to a bank is tRCD-R.
In Figure6. the interaction interval for the AWs case is tRCD-W. This is the row-to-column-write timing parameter and represents the
minimum interval between an activate operation and a write operation to a bank.
The interaction interval for the RWd and RWs cases is t∆RW. This is the read-to-write time parameter and represents the minimum
interval between a read and a write operation to any banks. See “Read/Write Interaction” on page 31.
The interaction interval for the WWd and WWs cases is tCC. This is the column-to-column time parameter and represents the minimum
interval between two write operations.
The interaction interval for the PWs case is tRP + tRCD-W. An activate operation must be inserted between the precharge and the write
operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval between an activate and a write operation to a bank is tRCD-W.
In Figure7, the interaction interval for the APs case is tRAS. This parameter is the minimum activate-to-precharge time to a bank.
The interaction interval for the RPs and WPs cases are tRDP and tWDP, respectively. These are the read-or write-to-precharge time
parameters to a bank.
Ths interaction interval for the PPd case is tPP. This parameter is the precharge-to-precharge time and the minimum interval between
precharge commands to different banks of a device.
The interaction interval for the PPs case is tRC. This is the row cycle time parameter and the minimum interval between precharge
commands to same banks of a device. An activate operation must be inserted between the two activate operations. This activate operation must be placed a time tRP after the first, and a time tRAS before the second precharge.
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Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT
a
ACT
b
tRR
tRAS
ACT
a
tRC
PRE
a
tRP
ACT
b
DQ15..0
DQ15..0
DQN15..0
DQN15..0
AAd Case (activate-activate-different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
T0
T1
T2
T3
T4
T5
T6
T7
T8
AAs Case (activate-activate-same bank)
a: ROWA Packet with ACT,Ba,Ra
Ba = Bb
b: ROWA Packet with ACT,Bb,Rb
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD ACT
a
b
DQ15..0
DQ15..0 No
DQN15..0
DQN15..0
RD
a
PRE
a
tRP
tRDP+tRP
ACT
b
limit
RAd Case (read-activate-different bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
T0
tRDP
T1
T2
T3
T4
T5
RAs Case (read-activate-same bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ15..0 No
DQ15..0
DQN15..0
DQN15..0
tWRP
tWRP+tRP
WR
a
WR ACT
a
b
tRP
ACT
b
limit
WAd Case (write-activate-different bank)
a: COL Packet with WR,Ba,Ca
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
T0
PRE
a
T1
T2
T3
T4
T5
T6
T7
T8
WAs Case (write-activate-same bank)
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ15..0
DQ15..0
DQN15..0
DQN15..0
PRE ACT
a
b
PRE
a
tRP
ACT
b
No limit
PAd Case (precharge-activate-different bank)
a: ROWP Packet with PRE,Ba
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
PAs Case (precharge-activate-same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: ROWA Packet with ACT,Bb,Rb
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Figure 5 : ACT-, RD-, WR-, PRE-to-RD Packet Interactions
CFM
CFMN
CFM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFMN
RQ11..0
RQ11..0
ACT RD
a
b
DQ15..0
DQN15..0
DQ15..0
No limit
ACT
a
RD
b
tRCD-R
DQN15..0
ARd Case (activate-read different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
T6
T7
T8
ARs Case (activate-read same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with RD,Bb,Cb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD
a
tCC
RD
a
RD
b
tCC
RD
b
DQ15..0
DQ15..0
DQN15..0
DQN15..0
RRd Case (read-read different bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
RRs Case (read-read same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR
a
RD
b
t∆WR
WR
a
RD
b
t∆WR
DQ15..0
DQ15..0
DQN15..0
DQN15..0
WRd Case (write-read different bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
WRs Case (write-read same bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
PRE RD
a
b
DQ15..0
DQ15..0 No
DQN15..0
DQN15..0
PRE
a
tRP
tRP+tRCD-R
ACT
B
tRCD-R
RD
b
limit
PRd Case (precharge-read different bank)
a: ROWP Packet with PRE,Ba
Ba =/ Bb
b: COL Packet with RD,Bb,Cb
PRs Case (precharge-read same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: COL Packet with RD,Bb,Cb
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Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT WR
a
b
ACT WR
a
b
tRCD-W
No limit
DQ15..0
DQ15..0
DQN15..0
DQN15..0
AWd Case (activate-write different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
T5
T6
T7
T8
AWs Case (activate-write same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
t∆RW
RD
a
DQ15..D0
DQ15..0
DQN15..0
DQN15..0
WR
b
Q(a)
tCAC
RWd Case (read-write-different bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
RD
a
tCWD
T5
D(b)
tCC tCYCLE
Ba =/ Bb
T6
T7
T8
T9
t∆RW
WR
b
tCWD
Q(a)
tCAC
RWs Case (read-write-same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
D(b)
tCC tCYCLE
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR
a
tCC
WR
a
WR
b
tCC
WR
b
DQ15..0
DQ15..0
DQN15..0
DQN15..0
WWd Case (write-write different bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
T5
WWs Case (write-write same bank)
a: COP Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
Ba = Bb
tRCD-W
PRE WR
a
b
PRE
a
tRP
tRP+tRCD-W
ACT WR
B
b
No limit
DQ15..0
DQ15..0
DQN15..0
DQN15..0
PWd Case (precharge-write different bank)
a: ROWP Packet with PRR,Ba
Ba =/ Bb
b: COL Packet with WR,Bb,Cb
PWs Case (precharge-write same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: COP Packet with WR,Bb,Cb
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Figure 7 : ACT-, RD-, WR-, PRE-to-PRE Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT PRE
a
b
ACT
a
PRE
b
tRAS
No limit
DQ15..0
DQ15..0
DQN15..0
DQN15..0
APd Case (activate-precharge different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
APs Case (activate-precharge same bank)
a: ROWA Packet with ACT,Ba,Ra
Ba = Bb
b: ROWP Packet with PRR,Bb
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD PRE
a
b
RD
a
tRDP
PRE
b
No limit
DQ15..0
DQ15..0
DQN15..0
DQN15..0
RPd Case (read-precharge different bank)
a: COL Packet with RD,Ba,Ca
Ba=/ Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
RPs Case (read-precharge same bank)
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRR,Bb
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR PRE
a
b
WR
a
tWRP
PRE
b
No limit
DQ15..0
DQ15..0
DQN15..0
DQN15..0
WPd Case (write-precharge different bank)
a: COL Packet with WR,Ba,Ca
Ba=/ Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
WPs Case (write-precharge same bank)
a: COL Packet with WR,Ba,Ca
Ba = Bb
b: ROWP Packet with PRE,Bb
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
PRE
a
tPP
PRE
b
PRE
a
tRP
ACT
b
tRAS
PRE
b
tRC
DQ15..0
DQ15..0
DQN15..0
DQN15..0
PPd Case (precharge-precharge different bank)
a: ROWP Packet with PRE,Ba
Ba # Bb
b: ROWP Packet with PRE,Bb
PPs Case (precharge-precharge same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: ROWP Packet with PRE,Bb
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7.5 Dynamic Request Scheduling
Delay fields are present in the ROWA, COL, and ROWP packet. They permit the associated command to optionally wait for a time of one
(or more) tCYCLE before taking effect. This allows a memory controller more scheduling flexibility when issuing request packets. Figure8
illustrates the use of the delay fields.
In the first timing diagram, a ROWA packet with an ACT command is present at cycle T0. The DELA field is set to “1”. This request
packet will be equivalent to a ROWA packet with an ACT command at cycle T1 with the DELA field is set to “0”. This equivalence should
be used when analyzing request packet interactions.
In the second timing diagram, a COL packet with a RD command is present at cycle T0. The DELC field is set to “1”. This request packet
will be equivalent to a COL packet with an RD command at cycle T1 with the DELC field is set to “0”. This equivalence should be used
when analyzing request packet interactions.
In a similar fashion, a COL packet with a WR command is present at cycle T12. The DELC field is set to”1”. This request packet will be
equivalent to a COL packet with a WR command at cycle T13 with the DELC field is set to “0”. This equivalence should be used when
analyzing request packet interactions.
In the COL packet with a RD command example, the read data delay, tCAC is measured between the Q read data packet and the virtual
COL packet at cycle T1.
Likewise, for the example with the COL packet with a WR command, the write data delay, tCWD is measured between the D write data
packet and the virtual COL packet at cycle T13.
In the third timing diagram, a ROWP packet with a PRE command is present at cycle T0. The DEL field(POP[1:0]) is set to “11”. This
request packet will be equivalent to a ROWP packet with a PRE command at cycle T1 with the DEL field is set to “10”, it will be equivalent to a ROWP packet with a PRE commmand at cycle T2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet
with a PRE command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet interactions.
In the fourth timing diagram, a ROWP packet with a REFP command is present at cycle T0. The DEL field(RA[7:6] ) is set to “11”. This
request packet will be equivalent to a ROWP packet with a REFP command at cycle T1 with the DEL field is set to “10”, it will be equivalent to a ROWP packet with a REFP command at cycle T2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet
with a REFP command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet
interactions.
The two examples for the REFA and REFI commands are identical to the example just described for the REFP command.
The ROWP packet allows two independent operations to be specified. A PRE precharge command uses the POP and BP fields, and the
REFP, REFA, or REFI commands use the ROP and RA fields. Both operations have an optional delay field(the POP field for the PRE
command and the RA field with the REFP, REFA, or REFI commands). The two delay mechanisms are independent of one another. The
POP field does not affect the timing of the REFP, REFA, or REFI commands, and the RA field does not affect the timing of the PRE
command.
When the interactions of a ROWP packet are analyzed, it must be remembered that there are two independent commands specified,
both of which may affect how soon the next request packet can be issued. The constraints from both commands in a ROWP packet must
be considered, and the one that requires the longer time interval to the next request packet must be used by the memory controller.
Furthermore, the two commands within a ROWP packet may not reference the same bank in the BP and RA fields.
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Figure 8 : Request Scheduling Examples
ACT w/DEL=1 at T0 is equivalent
to ACT w/DEL=0 at T1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tCYCLE
ACT ACT
DEL1 DEL0
DQ15..0
DQN15..0
Note DEL value is specified by DELA field.
ROWA/ACT Command
WR w/DEL=1 at T12 is equivalent
to WR w/DEL=0 at T13
RD w/DEL=1 at T0 is equivalent
to RD w/DEL=0 at T1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
RD RD
DEL1 DEL0
tCYCLE
WR WR
DEL1 DEL0
DQ15..0
DQN15..0
Q
tCAC
D
tCWD
Note DEL value is specified by DELC field.
COL/RD and COL/WR Commands
PRE w/DEL=3 at T0 is equivalent to PRE w/DEL
=2 at T1 or PRE w/DEL=1 at T2 or PRE w/DEL=0 at T3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tCYCLE
PRE PRE PRE PRE
DEL3 DEL2 DEL1 DEL0
DQ15..0
DQN15..0
Note DEL value is specified by {POP1, POP0} field.
ROWP/PRE Command
REFP w/DEL=3 at T0 is equivalent to REFP w/DEL=2
at T1 or REFP w/DEL=1 at T2 or REFP w/DEL=0 at T3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
REFI w/DEL=3 at T13 is equivalent to REFI w/DEL=2
at T14 or REFI w/DEL=1 at T15 or REFI w/DEL=0 at T16
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
REFP REFP REFP REFP
DEL3 DEL2 DEL1 DEL0
REFA REFA REFA REFA
DEL3 DEL2 DEL1 DEL0
REFI REFI REFI REFI
DEL3 DEL2 DEL1 DEL0
tCYCLE
REFA w/DEL=3 at T6 is equivalent to REFA w/DEL=2
at T7 or REFA w/DEL=1 at T8 or REFA w/DEL=0 at T9
Note DEL value is specified by {RA7, RA6} field.
ROWP/REFP,REFA,REFI Commands
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8.0 Memory Operations
8.1 Write Transactions
Figure9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated data
packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how
many request packets are needed to perform the access.
The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a row is already present in
the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed
(a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba.
In this case, write data may be directly written into the sense amp array for the bank, and row operations(activated or precharge) are not
needed. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T0, and a second COL packet with WR
command to column Ca1 of bank Ba is presented on edge T2. Two write data packets D(a1) and D(a2) follow these COL packets after
the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data
packet.
The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is already open (a row is
already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of
the row already sensed (a page miss). This comparsion must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An activate
command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with WR command to column Ca1 of bank
Ba is presented on edge T7 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on
edge T9. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are
separated by the column-cycle time tCC. This is also the length of each write data packet.
The third timing diagram shows an example of a page-empty wirte transaction. In this case, the selected bank is already closed (no row
is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still
remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to access the requested row
(activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with WR command to column Ca1
of bank Ba is presented on edge T1 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented
on edge T3. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are
separated by the column-cycle time tCC. This is also the length of each write data packet. After the final write command, it may be necessary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T14 a time tWRP after the last
COL packet with a WR command. The decision whether to close the bank or leave it open is made by memory controller and its page
policy.
The fourth timing diagram shows another example of a page-empty write transaction. This is similar to the previous example except that
only a single write command is presented, rather than two write commands. This example shows that even with a minimum length write
transaction, tRAS parameter will not be a constraint. The tRAS measures the minimum time between an activate command and a
precharge command to a bank. This time interval is also constrained by the sum tRCD-W + tWRP which will be larger for a write transaction. These two constraints (tRAS and tRCD-W + tWRP) will be a function of the memory device’s speed bin and the data transfer length (the
number of write commands issued between the activate and precharge commands), and the tRAS parameter could become a constraint
for future speed bins. In this example, the sum tRCD-W + tWRPs is greater than tRAS by the amount ∆tRAS.
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Figure 9 : Write Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
tCYCLE
WR
a2
tCC
DQ15..0
DQN15..0
D(a1)
tCWD
D(a2)
Page-hit Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
a3
ACT WR
a0
a1
tRP
DQ15..0
DQN15..0
tRCD-W
tCYCLE
WR
a2
tCC
tCWD
Transaction a: WR
D(a1)
a0 = {Ba,Ra}
D(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0
a1
DQ15..0 tRCD-W
DQN15..0
WR
a2
tCWD
tDP
tCC
D(a1)
tCWD
tCYCLE
PRE
a3
tWRP
D(a2)
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tRAS
ACT WR
a0
a1
DQ15..0 tRCD-W
DQN15..0
Bb = Ba
∆tRAS
tWRP
tCWD
PRE
a3
tRP
tCYCLE
ACT
b0
D(a1)
Transaction a: WR
Transaction b: WR
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Page-empty Write Example - Core Limited
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8.2 Read Transactions
Figure10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated data
packets) needed to perform a memory access. The state of the memory core and the address of memory access determine how many
request packets are needed to perform the access.
The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row is already present in
the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed
(a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba.
In this case, read data may be directly read from the sense amp array for the bank and no row operations (actiavate or precharge) are
needed. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T0 and a second COL packet with RD
command to column Ca2 of bank Ba is presented on edge T2. Two read data packets Q(a1) and Q(a2) follow these COL packets after
the read data delay tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data
packet.
The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is already open (a row is
already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of
the row already sensed(a page miss). This comparison must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An activate
command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with RD command to column Ca1 of bank
Ba is presented on edge T11 a time tRCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on
edge T13. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay tCAC. The two COL packets are
separated by the column-cycle time tCC. This is also the length of each read data packet.
The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed (no row
is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still
remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access the requested row (activated). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with RD command to column Ca1 of
bank Ba is presented on edge T5 a time tRCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on
edge T7. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay tCAC. The two COL packets are
separated by the column-cycle time tCC. This is also the length of each read data packet. After the final read command, it may be necessary to close the present row (precharge). A precharge command - PRE to bank Ba - is presented on edge T10 a time tRDP after the last
COL packet with a RD command. Whether the bank is closed or left open depends on the memory controller and its page policy.
The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the previous example except that
it uses one read command instead of two read commands. In this case, the core parameter tRAS may also be a constraint upon when the
precharge command may be issued.
The tRAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is also
constrained by the sum tRCD-R + tRDP and must be set to whichever is larger. These two constraints (tRAS and tRCD-R + tRDP) will be a
function of the memory device’s speed bin and the data transfer length (the number of read commands issued between the activate and
precharge commands). In this example, the tRAS is greater than the sum tRCD-R + tRDP by the amount ∆tRDP.
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Figure 10 : Read Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
RD
a1
tCYCLE
RD
a2
tCC
DQ15..0
DQN15..0
Q(a1)
tCAC
Transaction a: RD
Q(a2)
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-hit Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
a3
ACT
a0
RD
a1
tRP
DQ15..0
DQN15..0
tRCD-R
tCYCLE
RD
a2
tCC
Q(a1)
tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Q(a2)
a3 = {Ba}
Page-miss Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT
a0
RD
a1
tRCD-R
DQ15..0
DQN15..0
RD
a2
tCC
Q(a1)
tCAC
Transaction a: RD
tCYCLE
PRE
a3
tRDP
a0 = {Ba,Ra}
Q(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tRAS
ACT
a0
RD
a1
tRCD-R
DQ15..0
DQN15..0
tRDP
∆tRDP
Transaction a: RD
Transaction b: RD
tCYCLE
ACT
b0
Q(a1)
tCAC
Bb = Ba
tRP
PRE
a3
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Page-empty Read Example - Core Limited
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8.3 Interleaved Transactions
Figure11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transaction is
started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty access; that is,
a bank is in a closed state prior to an access and is precharged after the access. With this assumption, each transaction requires the
same number of request packets at the same relative positions. If bank were allowed to be in an open state, then each transaction would
require a different number of request packets depending upon whether the transaction was page-empty, page-hit or page-miss. This situation is more complicated for the memory controller and will not be analyzed in this document.
In the interleaved page-empty write example, there are four sets of request pins RQ11...0 shown along the left side of the timing diagram.
The first three show the timing slots used by each of the three requests packet types (ACT, COL and PRE), and the fourth set (ALL)
shows the previous three merged together. This allows the pattern used for allocating request slots for the different packets to be seen
more clearly.
The slots at {T0, T4, T8, T12 ...} are used for ROWA packets with ACT commands. This spacing is determined by the tRR parameter.
There should not be interference between the interleaved transactions due to resource conflicts because each bank address - Ba, Bb,
Bc, Bd and Be - is assumed to be different from another. If two of the bank addresses are the same, the later transaction would need to
wait until the earlier transaction had completed its precharge operation. Five different banks are needed because the effective tRC (tRC +
∆tRC) is 20*tCYCLE.
The slots at {T1, T3, T5, T7, T9, T11, ...} are used for COL packets with WR commands. This frequency of the COL packet spacing is
determined by the tCC parameter and by the fact that there are two column accesses per row access. The phasing of the COL packet
spacing is determined by the tRCD-W parameter. If the value of tRCD-W required the COL packets to occupy the same request slots as the
ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the COL packet one tCYCLEs earlier.
The DQ bus slots at {T7, T9, T11, T13, ...} carry the write data packets {D(a1), D(a2), D(b1), D(b2), ...}. Two write data packets are written
to a bank in each transaction. The DQ bus is completely filled with write data; no idle cycles need to be introduced because there are no
resource conflicts in this example.
The slots at {T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet spacing is determined
by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tWRP paramter. If the value of tWRP required the
ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown), the delay field
in the ROWP packet could be used to place the ROWP packet one or more tCYCLE earlier.
There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets of request pins
RQ11...0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different packets to
be seen more clearly.
The slots at {T0, T4, T8, T12, ...} are used for ROWA packets with ACT command. This spacing is determined by the tRR parameter. There
should not be interference between the interleaved transactions due to resource conflicts because each bank address - Ba, Bb, Bc and
Bd - is assumed to be different from another. Four different banks are needed because the effective tRC is 16 * tCYCLE.
The slots at {T5, T7, T9, T11, ...} are used for COL packets with RD commands. This frequency of the COL packet spacing is determined
by the tCC paramter and by the fact that there are two column accesses per row access. The phasing of the COL packet spacing is determined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy the same request slots as the ROWA packets
(this case is not shown), the DELC field in the COL packet could be used to place the packet one tCYCLE earlier.
The DQ bus slots at {T11, T13, T15, T17, ...} carry the read data packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}, Two read data packets are read
from a bank in each transaction. The DQ bus is completely filled with read data - That is, no idle cycles need to be introduced because
there are no resource conflicts in this example.
The slots at {T10, T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of the ROWP packet spacing is
determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tRDP parameter. If the value of tRDP
required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown),
the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs earlier.
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Figure 11 : Interleaved Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
The effective tRC time is increased by 4 tCYCLE
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
ACT
a0
RQ11..0
(COL)
WR
a1
DQ15..0 tRCD-W
DQN15..0
RQ11..0
(PRE)
RQ11..0
(ALL)
tRC
ACT
b0
tRR
WR
a2
WR
b1
ACT
c0
WR
b2
D(a1)
ACT WR
a0
a1
D(a2)
WR
c2
WR
d1
D(b1)
D(b2)
WR
d2
D(c1)
WR
e1
WR ACT WR
a2
b0
b1
D(c2)
∆tWRP
tWRP
D(d2)
tRP
PRE
a3
WR
f1
WR
e2
D(d1)
tCYCLE
ACT
f0
WR
f2
D(e1)
D(e1)
PRE
b3
PRE
c3
WR ACT WR PRE WR ACT WR PRE WR ACT WR PRE WR
f1
f2
c2
d0
d1
a3
d2
e0
e1
b3
e2
f0
c3
WR ACT WR
b2
c0
c1
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
Bf = Ba
WR
c1
∆tRC
ACT
e0
tCC
tCWD
Ba,Bb,Bc,Bd,Be
are different
banks.
ACT
d0
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
e0 = {Bf,Rf}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
f1 = {Bf,Cf1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
a2 = {Bd,Cd2}
e2 = {Be,Ce2}
f2 = {Bf,Cf2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
f3 = {Bf}
Interleaved Page-empty Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
ACT
a0
RQ11..0
(COL)
tRR
DQ15..0
DQN15..0
tRCD-R
ACT
a0
Ba,Bb,Bc,Bd are
different banks.
Be = Ba
RD
a1
ACT
c0
RD
a2
ACT
d0
RD
b1
RD
b2
ACT
e0
RD
c1
RD
c2
tCYCLE
ACT
f0
RD
d1
RD
d2
RD
e1
RD
e2
tCAC
Q(a1)
tCC
RQ11..0
(PRE)
RQ11..0
(ALL)
tRC
ACT
b0
ACT RD
b0
a1
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
tRDP
Q(a2)
tRP
PRE
a3
PRE
b3
Q(b1)
Q(b2)
PRE
c3
Q(c1)
Q(c2)
PRE
d3
RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD
a2
c0
b1
a3
b2
d0
c1
b3
c2
e0
d1
c3
d2
f0
e1
d3
e2
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
a2 = {Bd,Cd2}
e2 = {Be,Ce2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
Interleaved Page-empty Read Example
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8.4 Read/Write Interaction
The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will describe
the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts.
Figure12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two COL packets with WR
commands are presented on cycles T0 and T2. The write data packets are presented a time tCWD later on cycles T4 and T6. The device
requires a time t∆WR after the second COL packet with a WR command before a COL packet with a RD command may be presented.
Two COL packets with RD commands are presented on cycles T11 and T13. The read data packets are returned a time tCAC later on
cycles T17 and T19. The time t∆WR is required for turning around internal bi-directional interconnections (inside the device). This time
must be observed regardless of whether the write and read commands are directed to same banks or different banks. A gap tWRBUB,XDRDRAM will appear on the DQ bus between the end of the D(a2) packet and the beginning of the Q(b1) packet (measured at the
appropriate packet reference points). The size of this gap can be evaluated by calculating the difference between cycles T2 and T17
using the two timing paths :
tWR-BUB, XDRDRAM = t∆WR + tCAC - tCWD - tCC
In this example, the value of tWR-BUB,XDRDRAM is greater than its minimum value of tWR-BUB,XDRDRAM,MIN. The values of t∆WR and tCAC
are equal to their minimum values.
In the second case, the timing diagram displayed at the bottom of Figure12 illustrates a read transaction followed by a write transaction.
Two COL packets with RD commands are presented on cycles T0 and T2. The read data packets are returned a time tCAC later on cycles
T6 and T8. The device requires a time t∆RW after the second COL packet with a RD command before a COL packet with a WR command
may be presented. Two COL packets with WR commands are presented on cycles T10 and T12. The write data packets are presented a
time tCWD later on cycles T13 and T15. The time t∆RW is required for turning around the external DQ bi-directional interconnections
(outside the device). This time must be observed regardless whether the read and write commands are directed to the same banks or
different banks. The time t∆RW depends upon four timing parameters. and may be evaluated by calculating the difference between cycles
T2 and T13 using the two timing paths :
t∆RW + tCWD = tCAC + tCC + tRW-BUB, XDRDRAM or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB, XDRDRAM
In this example, the values of t∆RW, tCAC, tCWD, tCC, and tRW-BUB, XDRDRAM are equal to their minimum values.
Figure 12 : Write/Read Interaction
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
WR
a2
tCWD
tDR
RD
b1
t∆WR
DQ15..0
DQN15..0
D(a1)
RD
b2
tCYCLE
tCAC
D(a2)
tCWD
Q(b1)
Q(b2)
tWR-BUB,XDRDRAM
tCC
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Write/Read Turnaround Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
RD
a1
RD
a2
WR
b1
t∆RW
tCAC
Q(a1)
WR
b2
Q(a2)
tCC
tCYCLE
tCWD
D(b1)
D(b2)
tRW-BUB,XDRDRAM
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Read/Write Turnaround Example
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8.5 Propagation Delay
Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory component and the
memory controller.
The timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory component. In this
case, the timing will be identical to what has already been shown in the previous sections; i,e. with all timing measured at the pins of the
memory component. This timing diagram was produced by merging portions of the top and bottom timing diagrams in Figure12.
The example shown is that of a single COL packet with a write command, followed by a single COL packet with a read command,
followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank.
A timing interval t∆WR is required between the first WR command and the RD command, and a timing interval t∆RW is required between
the RD command and the second WR command. There is a write data delay tCWD between each WR command and the associated write
data packet D. There is a read data delay tCAC between the RD command and the associated read data packet Q. In this example, all
timing parameters have assumed their minimum values except tWR-BUB, XDRDRAM.
The lower timing diagram in the figure shows the case where timing skew is present between the memory controller and the memory
component. This skew is the result of the propagation delay of signal wavefronts on the wire carrying the signals.
The example in the lower diagram assumes that there is a propagation delay of tPD-RQ along both the RQ wires and the CFM/CFMN
clock wires between the memory controller and the memory component (the value of tPD-RQ used here is 1*tCYCLE). Note that in an
actual system the tPD-RQ value will be different for each memory component connected to the RQ wires.
In addition, it is assumed that there is a propagation delay tPD-D along the DQ/DQN wires between the memory controller and the
memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay tPD-Q along the
DQ/DQN wires between the memory component and the memory controller (the direction in which read data travels). The sum of these
two propagation delays is also denoted by the timing parameter tPD,CYC = tPD-D + tPD-Q.
As a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are measured at
the pins of the memory controller or the pins of memory component. For example, the CFM/CFMN signals at the points of the memory
component are tPD-RQ later than at the pins of the memory controller. This is shown by the cycle numbering of the CFM/CFMN signals at
the two locations - in this example cycle T1 at the memory controller aligns with cycle T0 at the memory component.
All the request packets on the RQ wires will have a tPD-RQ skew at the memory component relative to the memory controller in this
example. Because the tPD-D propagation delay of write data matches the tPD-RQ propagation delay of the write command, the controller
may issue the write data packet D(a0) relative to the COL packet with the first write command “WR(a0)” with normal write data delay
tCWD. If the propagation delays between the memory controller and memory component were different for the RQ and DQ buses (not
shown in this example), the write data delay at the memory controller would need to be adjusted.
A propagation delay is seen by the read command - that is, the read command will be delayed by a tPD-RQ skew at the memory component relative to the memory controller. The memory componet will return the read data packet Q(b0) relative to this read command with
the normal read data delay tCAC (at the pins of the memory componet).
The read data packet will be skewed by an additional propagation delay of tPD-Q as it travels from the memory component back to the
memory controller. The effective read data delay measured between the read command and the read data at the memory controller will
be tCAC + tPD-RQ + tPD-Q.
tPD-RQ factor is casued by the propagaion delay of the request packets as they travel from memory controller to memory component. The
tPD-Q factor is casued by the propagation delay of the read data packets as they travel from memory componet to memory controller.
All timing parameters will be equal to their minimum values except tWR-BUB,XDRDRAM (as in the top diagram), and the timing parameters
tRW-BUB,XDRDRAM and t∆RW. These will be larger than their minimum values by the amount (tPD,CYC - tPD,CYC,MIN), where tPD,CYC = tPDD + tPD-Q. This may be seen by evaluating the two timing paths between cycle T9 at th controller and cycle T21 at the XDR DRAM:
t∆RW + tPD-RQ + tCWD = tPD-RQ + tCAC + tCC + tRW-BUB,XDRDRAM or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB,XDRDRAM
The following relationship was shown for Figure12.
t∆RW, MIN = (tCAC - tCWD) + tCC + tRW-BUB, XDRDRAM, MIN or (t∆RW - t∆RW, MIN) = (tRW-BUB, XDRDRAM - tRW-BUB, XDRDRAM, MIN)
In other words, the two timing parameters tRW-BUB,XDRDRAM and t∆RW will change together. The relationship of this change to the propagation delay tPD,CYC (=tPD-D + tPD-Q) can be derived by looking at the two timing paths from T15 to T21 at the XDR DRAM:
tPD-Q + tCC + tRW-BUB,XIO + tPD-D = tCC + tRW-BUB,XDRDRAM or tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD-D + tPD-Q or tRW-BUB,XDRDRAM = tRWBUB,XIO + tPD,CYC
In a system with minimum propagation delays: tRW-BUB,XDRDRAM,MIN = tRW-BUB,XIO + tPD,CYC,MIN
and since tRW-BUB,XIO is equal to tRW-BUB,XIO,MIN in the both cases, the following is true: (tPD,CYC - tPD,CYC,MIN) = (tRW-BUB,XDRDRAM tRW-BUB,XDRDRAM,MIN) = (t∆RW - t∆RW,MIN)
In other words, the values of the tRW-BUB,XDRDRAM,MIN and t∆RW,MIN timing parameters correspond to the value of tPD,CYC,MIN for the
system (this is equal to one tCYCLE). As tPD,CYC is increased from this minimum value, tRW-BUB,XDRDRAM and t∆RW increase from their
minimum values by an equivalent amount.
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Figure 13 : Propagation Delay
XDR DRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a0
DQ15..0
DQN15..0
RD
b0
t∆WR
D(a0)
tCWD
tCAC
tCC
tWR-BUB,XDRDRAM
T1
T2
T3
T4
T5
T6
T7
tCWD
Q(b0)
D(c0)
tCC
tRW-BUB,XDRDRAM
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Transaction a: WR
Transaction b: RD
Transaction c: WR
Controller T0
tCYCLE
WR
c0
t∆RW
Write-Read-Write at XDR DRAM
(portions of top and bottom timing diagrams of Figure 12 merged)
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a0
DQ15..0
DQN15..0
tDRW
RD
b0
tDWR
tCC
D(a0)
XDR DRAMT
-1
T0
T1
T2
T3
T5
T6
T7
T8
T9
tCYCLE
tRW-BUB,XIO
Q(b0)
tPD-Q
T4
WR
c0
D(c0)
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CFM
CFMN
tPD-RQ
tCWD
tPD-RQ
D(a0)
Transaction a: WR
Transaction b: RD
Transaction c: WR
tPD-RQ
RD
b0
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Q(b0)
tCAC
WR
c0
tPD-D
tCWD
tRW-BUB,XDRDRAMD(c0)
tCC
Write-Read-Write at Controller and XDR DRAM
w/ tPD-RQ = tPD-Q = tPD-D = 1*tCYCLE
tPD-RQ
...
DQ15..0
DQN15..0
tCYCLE
tPD-D
RQ
Controller
tPD-D
RQ
DQ
DQ
tPD-Q
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XDR DRAM
...
RQ11..0
WR
a0
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9.0 Register Operations
9.1 Serial Transactions
The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The other four
pins use RSL signaling levels. RST, CMD, SDI and SDO use a timing window which surrounds the falling edge of SCK. The RST pin is
used for initialization.
Figure14 and Figure15 show examples of a serial write transaction and a serial read transaction. Each transaction starts on cycle S4 and
requires 32 SCK edges. The next serial transaction can begin on cycle S36. SCK does not need to be asserted if there is no transaction.
9.2 Serial Write Transactions
The serial device write transaction in Figure14 begins with the Start [3:0] field. This consists of bits “1100” on the CMD pin. This indicates
to the XDR DRAM that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD[1:0] field. This field contains the serial command, the bits 00 in the case of a serial device write transaction.
The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field. This field contains the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register.
The next eight bits on the CMD pin is the SWD[7:0] field. this is the write data that is placed into the selected control register.
A final bit”0” is driven on the CMD pin to finish the serial write transaction.
A serial broadcast write is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices perform the
register write. The SDI and SDO pins are not used during either serial write transaction.
9.3 Serial Read Transactions
The serial device read transaction in Figure15 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This indicates
that the remaining 28 bits constitute a serial transaction.
The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of a serial device read
transaction.
The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being accessed.
The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn on the SDO output driver.
The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin are the SRD [7:0] field.
This is the read data that is accessed from the selected control register. Note the output timing convention here: bit SRD [7] is driven
from a time tQ,SI,MAX after edge S26 to a time tQ,SI,MIN after edge S27. The bit is sampled in the controller by the edge S27.
A final bit “0” is driven on the CMD pin to finish the serial read transaction.
A serial forece read is identical except that the contents of the SID [5:0] field in the transaction is ignored and all devices perform the
register read. This is used for device testing.
Figure16 shows the response of a DRAM to a serial device read transaction when its internal SID [5:0] register field doesn’t match the
SID [5:0] field of the transaction. Instead of driving read data from an internal register for cycle edges S27 through S34 on the SDO output
pin, it passes the input data from the SDI input pin to the SDO output pin during this same period.
Table 9: SCMD Field Encoding Summary
SCMD[1:0]
Command
DESCRIPTION
00
SDW
Serial device write-one device is written, the one whose SID[5:0] register matches the SID[5:0]
field of the transaction.
01
SBW
Serial broadcast write - all devices are written, regardless of the contents of the SID [5:0] register
and the SID [5:0] transaction field.
10
SDR
Serial device read - one device is read, the one whose SID[5:0] register matches the SID[5:0]
field of the transaction.
11
SFR
Serial forced read - all devices are read, regardless of the contents of the SID[5:0] register and
the SID[5:0] transaction field
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Figure 14 : Serial Write Transaction
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
tCYC,SCK
RST
Start
CMD
transaction
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’‘0’ ‘0’ 5
4
3
2
SADR[7:0]
1
0
7 6
5
4
3 2
SWD[7:0]
1
0 ‘0’ 7
6
5 4
3
2
1
0 ‘0’
SDI
(input)
SDO
(output)
Figure 15 : Serial Read Transaction — Selected DRAM
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
tCYC,SCK
RST
Start
CMD
transaction
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
4
3
2
SADR[7:0]
1
0
7 6
5
4
3 2
8’h00
1
0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
SDI
(input)
SDO
(output)
SRD[7:0]
7
6
5 4
3
2
1
0
Figure 16 : Serial Read Transaction — Non-selected DRAM
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
S28
tCYC,SCK
RST
CMD
Start
SCMD
SDI
transaction
2’h0,SID[5:0]
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
4
3
2
SADR[7:0]
1
0
7 6
5
4
3 2
tP,SI
8’h00
1
0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
SDI
(input)
7 6
5
SDO
(output)
7
5 4
SRD[7:0]
4
3 2
1
0
1
0
SRD[7:0]
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9.4 Register Summary
Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for configuring the
component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibration operations.
A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bits must be
written as 0 and must be ignored when read. Write-only fields must be ignored when read .
Each figure displays the following register information:
1. Register name
2. Register mnemonic
3. Register address (SADR [7:0] value needed to access it)
4. Read-only, write-only or read-write
5. Initialization state
6. Description of each defined register field
Figure17 shows the Serial Identification register. The register contains the SID [5:0] (serial identification field). This field contains the
serial identification value for the deice. The value is compared to the SID[5:0] field of a serial transaction to determine if the serial transaction is directed to this device. The serial identification value is set during the initialization sequence.
Figure18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field allows the number of DQ/DQN
pins used for memory read and write accesses to be adjusted. The SLE field enables data to be written into the memory through the
serial interface using the WDSL register.
Figure19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field is written with a “1”, the
memory component transactions from powerdown to active state. It is usually unnecessary to write a “0” into this field; this is done automatically by the PDN command in a COLX packet. The PST field indicates the current power state of the memory component.
Figure20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial Interface.
Figure23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is read-write and contains
the bank address used by self-refresh during the powerdown state. The MBR field controls how many banks are refreshed during each
refresh operation. Figure24, Figure25 and Figure26 show different fields of the Refresh Row Register (high, middle and low). This readwrite field contains the row address used by self- and auto-refresh. See”Refresh Transactions” on page 42 for more details.
Figure28 and Figure29 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and CCVALUE1 fields, respectively.
These are read-write fields which control the amount of IOL current driven by the DQ and DQN pins during a read transaction. The
Current Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Current Calibration 1 controls the odd-numbered
DQ and DQN pins.
Figure30 and Figure31 show the Impedance Calibration 0 and 1 registers. They contain the ZCVALUE0 and ZCVALUE1 field, respectively. These are read-write fields that control the impedance of the on-chip termination components in the DQ and DQN pins. The
Impedance Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Impedance Calibration 1 controls the oddnumbered DQ and DQN pins.
Figure 36 through Figure 41 and Figure 43 shows the test registers. This includes the TEST, DLL, PLL0, PLL1, IFT, DA and PARTn
registers. These are used during device testing. They are not to be read or written during normal operation.
Figure42 shows the DLY register. This is used to set the value of tCAC and tCWD used by the component. See “Timing Parameters” on
page 61.
Figure 17 : Serial Identification (SID) Register
7
6
reserved
5
4
3
2
SID[5:0]
1
0
Serial Identification Register
SADR[7:0]: 000000012
Read-only register
SID[7:0] resets to 000000002
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transaction to determine if the serial transaction is directed to this
device. The serial identification value is set during the initialization sequence.
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Figure 18 : Configuration (CFG) Register
7
6
SP[1:0]
5
4
3
rsrv
SLE
rsrv
2
1
0
WIDTH[2:0]
Configuration Register
SADR[7:0]: 000000102
Read/write register
CFG[7:0] resets to 000001002
WIDTH[2:0] - Device interface width field.
0002 - Reserved.
0012 - x2 device width
SLE - Serial Load enable field.
0102 - x4 device width
02 - WDSL-path-to-memory disabled
0112 - x8 device width
12 - WDSL-path-to-memory enabled
1002 - x16 device width
1012, 1102, 1112 - Reserved
SP[1:0] - Sub page activation field.(used with SR[1:0]field in ROWA packet)
002 - Full Page Activation (x16,x8,x4 and x2 WIDTH)
012 - Half Page Activation (x2 WIDTH only)
102 - Reserved
112 - Reserved
Figure 19 : Power Management (PM) Register
7
6
5
4
PST[1:0]
3
2
1
0
PX
reserved
Power Management Register
SADR[7:0]: 000000112
Read/write register
PM[7:0] resets to 000000002
PX - Powerdown exit field.(write-one-only, read=zero)
02 - Powerdown entry - do not write zero - use PDN command
12 - Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
002 - Powerdown (with self-refresh)
012 - Active/active-idle
102 - reserved
112 - reserved
Figure 20 : Write Data Serial Load (WDSL) Control Register
7
6
5
4
3
2
1
0
WDSD[7:0]
Write Data Serial Load Control Register
Read/write register
SADR[7:0]: 000001002
WDSL[7:0] resets to 000000002
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 2). Writing to this register “2x16” times accumulates a full
“tCC” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 36) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shifting order of the write data is shown in Table 11.
Figure 21 : RQ Scan High (RQH) Register
7
6
5
reserved
4
3
2
1
RQH[3:0]
0
RQ Scan High Register
SADR[7:0]: 000001102
Read/write register
RQH[7:0] resets to 000000002
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
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Figure 22 : RQ Scan Low (RQL) Register
7
6
5
4
3
2
1
0
RQL[7:0]
RQ Scan Low Register
SADR[7:0]: 000001112
Read/write register
RQL[7:0] resets to 000000002
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
Figure 23 : Refresh Bank (REFB) Control Register
7
6
5
MBR[1:0]
4
3
2
1
0
BANK[2:0]
reserved
Read/write register
Refresh Bank Control Register
REFB[7:0] resets to 000000002
SADR[7:0]: 000010002
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh
operation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
002 - Single-bank refresh.
102 - Reserved
012 - Reserved
112 - Reserved
Figure 24 : Refresh High (REFH) Row Register
7
6
5
4
3
2
1
0
R[18:16]
reserved
Refresh High Row Register
SADR[7:0]: 000010012
Read/write register
REFH[7:0] resets to 000000002
reserved - Refresh row field.
This field contains the high-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for autorefresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Figure 25 : Refresh Middle (REFM) Row Register
7
6
5
reserved
4
3
2
1
R[11:8]
0
Refresh Middle Row Register
Read/write register
SADR[7:0]: 000010102
REFM[7:0] resets to 000000002
R[11:8] - Refresh row field.
This field contains the middle-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for autorefresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
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Figure 26 : Refresh Low (REFL) Row Register
7
6
5
4
3
2
1
0
R[7:0]
Refresh Low Row Register
SADR[7:0]: 000010112
Read/write register
REFL[7:0] resets to 000000002
R[7:0] - Refresh row field.
This field contains the low-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 27 : IO Configuration (IOCFG) Register
7
6
5
4
3
2
1
0
ODF[1:0]
reserved
IO Configuration Register
SADR[7:0]: 000011112
Read/write register
IOCFG[7:0] resets to 000000002
ODF[1:0] - Overdrive Function field.
00 - Nominal VOSW,DQ range
01 - reserved
10 - reserved
11 - reserved
Figure 28 : Current Calibration 0 (CC0) Register
7
6
5
4
3
2
1
0
CCVALUE0[5:0]
reserved
Current Calibration 0 Register
SADR[7:0]: 000100002
Read/write register
CC0[7:0] resets to vvvvvvvv2
(vendor-dependent reset value)
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-numbered DQ and DQN pins.
Figure 29 : Current Calibration 1 (CC1) Register
7
6
5
4
3
2
1
0
CCVALUE1[5:0]
reserved
Current Calibration 1 Register
SADR[7:0]: 000100012
Read/write register
CC1[7:0] resets to vvvvvvvv2
(vendor-dependent reset value)
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-numbered DQ and DQN pins.
Figure 30 : Impedance Calibration 0 (ZC0) Register
7
6
5
4
3
2
1
0
ZCVALUE0[5:0]
reserved
reserved
Read/write register
Impedance Calibration 0 Register
ZC0[7:0] resets to 000000002
SADR[7:0]: 000100102
reserved
Figure 31 : Impedance Calibration 1 (ZC1) Register
7
6
reserved
5
4
3
2
ZCVALUE1[5:0]
reserved
1
0
Impedance Calibration 1 Register
Read/write register
SADR[7:0]: 000100112
ZC1[7:0] resets to 000000002
reserved
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Figure 32 : Current Fuse Setting 0 (FZC0) Register
7
6
5
4
3
2
1
0
FZCVALUE0[5:0]
reserved
reserved
Current Fuse Setting Register
SADR[7:0]: 000101002
Read-only register
FZC0[7:0] resets to vvvvvvvv
(vendor-dependent reset value)
reserved
Figure 33 : Current Fuse Setting 1 (FZC1) Register
7
6
5
4
3
2
1
0
FZCVALUE1[5:0]
reserved
reserved
Current Fuse Setting Register
SADR[7:0]: 000101012
Read-only register
FZC1[7:0] resets to vvvvvvvv
(vendor-dependent reset value)
reserved
Figure 34 : Read Only Memory 0 (ROM0) Register
7
6
5
4
3
VENDOR[3:0]
reserved
2
1
0
MASK[3:0]
Read Only Memory 0 Register
Read-only register
SADR[7:0]: 000101102
ROM0[7:0] resets to vvvvmmmm
MASK[3:0] - Version number of mask (00012 is first version).
VENDOR[3:0] - Vendor number for component:
0000 - reserved
0100-1111-reserved
0001 - Toshiba
0010 - Elpida
0011 - SEC
Figure 35 : Read Only Memory 1 (ROM1) Register
7
6
5
BB[1:0]
4
3
2
RB[2:0]
1
0
CB[2:0]
Read Only Memory 1 Register
SADR[7:0]: 000101112
Read-only register
ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits:
#bits = 10 +RB[2:0]
BB[2:0] - Bank address bits:
#bits = 2 +BB[2:0]
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
Figure 36 : TEST Register
7
6
5
4
WTL WTE
3
2
1
0
reserved
TEST Register
SADR[7:0]: 000110002
Read/write register
TEST[7:0] resets to 000000002
WTE - Wire Test Enable
WTL - Wire Test Latch
Figure 37 : DLL Register
7
6
5
4
3
reserved
2
1
0
DLL Register
SADR[7:0]: 000110012
Read/write register
DLL[7:0] resets to 000000002
TBD
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Figure 38 : PLL0 Register
7
6
5
4
3
2
1
0
reserved
PLL0 Register
SADR[7:0]: 000110102
Read/write register
PLL0[7:0] resets to 000000002
TBD
Figure 39 : PLL1 Register
7
6
5
4
3
2
1
0
reserved
PLL1 Register
SADR[7:0]: 000110112
Read/write register
PLL1[7:0] resets to 000000002
TBD
Figure 40 : IFT Register
7
6
5
4
3
2
1
0
reserved
IFT Register
SADR[7:0]: 000111002
Read/write register
IFT[7:0] resets to 000000002
TBD
Figure 41 : DA Register
7
6
5
4
3
2
1
0
reserved
DA Register
SADR[7:0]: 000111012
Read/write register
DA[7:0] resets to 000000002
TBD
Figure 42 : Delay (DLY) Control Register
7
6
5
4
3
2
CWD[3:0]
1
0
CAC[3:0]
DLY Register
SADR[7:0]: 000111112
Read/write register
DLY[7:0] resets to 001101102
CAC[3:0] - Programmed value of tCAC timing parameter:
01102 - tCAC = 6*tCYCLE 10002 - tCAC = 8*tCYCLE
01112 - tCAC = 7*tCYCLE others - Reserved.
CWD[3:0] - Programmed value of tCWD timing parameter:
00112 - tCWD = 3*tCYCLE
01002 - tCWD = 4*tCYCLE others - Reserved.
Figure 43 : Partner-Definable (PART0-PARTF) Registers
6
5
4
3
2
1
0
reserved
7
6
5
4
3
2
1
PART0 Register
SADR[7:0]: 100000002
Read/write register
PART0[7:0] resets to 000000002
PART1 Register
SADR[7:0]: 100000012
Read/write register
PART1[7:0] resets to 000000002
0
7
6
5
4
3
reserved
2
1
•••
•••
reserved
0
PARTF Register
SADR[7:0]: 100011112
•••
7
Read/write register
PARTF[7:0] resets to 000000002
Note - The partner-definable registers should not be written or read; doing so will produce undefined results.
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10.0 Maintenance Operations
10.1 Refresh Transactions
Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP packet on clock edge T0.
The REFA command causes the row addressed by the REFr register (REFH/REFM/REFL) to be opened (sensed) and placed in the
sense amp array for the bank.
Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank address and delay value,
and both cause the selected bank to open (to become sensed.). The difference is that the ACT command is accompanied by a row
address in the ROWA packet, while the REFA and REFI commands use a row address in the REFr register (REFH/REFM/REFL).
After a time tRAS, a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be closed (precharged),
leaving the bank in the same state as when the refresh transaction began.
Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value, and both
cause the selected bank to close (to become precharged).
After a time tRP, another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the same in this example).
This starts a second refresh cycle. Each refresh transaction requires a total time tRC = tRAS + tRP, but refresh transactions to different
banks may be interleaved like normal read and write transactions.
Note that refresh transactions always perform full-page activation, regardless of the setting in the SP1..0 field of the Configuration
register. See "Configuration (CFG) Register" on page 37. Also, see "sub-Row (Sub-Page) Sensing" on page 50.
Each row of each bank must be refreshed once in every tREF interval. This is shown with the fourth ROWP packet with a REFA command
in the top timing diagram.
10.2 Interleaved Refresh Transaction
The lower timing diagram in Figure44 represents one way a memory controller might handle refresh maintenance in a real system.
A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are presented starting at edge T0.
The packets are spaced with intervals of tRR. Each REFA or REFI command is addressed to a different bank (Ba through Bh) but uses
the same row address from the REFr (REFH/REFM/REFL) register. The eighth REFI command uses this address and then increments it
so the next set of eight REFA/REFI commands will refresh the next set of rows in each bank.
A series of eight ROWP packets with REFP commands are presented effectively at edge T10 (a time tRAS after the first ROWP packet
with a REFA command). The packets are spaced with intervals of tPP. Like the REFA/REFI commands, each REFP command is
addressed to a different bank (Ba through Bh).
This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions may be interleaved with the refresh transactions before and after the burst to prevent any loss of bus efficiency. In other words, a ROWA packet with
ACT command for a read or write could have been presented at edge T4 (a time tRR before the first refresh transaction starts at edge T0).
Also, a ROWA packet with ACT command for a read or write could have been presented at edge T36 (a time tRR after the last refresh
transaction starts at edge T32). In both cases, the other request packets for the interleaved read or write accesses (the precharge
commands and the read or write commands) could be slotted in among the request packets for the refresh transaction.
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Figure 44 : Refresh Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tRAS
REFA
RQ11..0
tRP
REFP
a0
a1
tRC
DQ15..0
DQN15..0
REFA
REFA
b0
c0
tCYCLE
tREF
Bb = Ba
Bc/Rc = Ba/Ra
T0
T1
Transaction a: REF
Transaction b: REF
Transaction c: REF
T2
T3
T4
T5
a0 = {Ba,REFR}
a0 = {Ba,REFR}
c0 = {Bc,REFR}
T6
T7
T8
T9
a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
Refresh Transaction
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
REFA
tRR
a0
REFA
REFA
REFA
REFA
REFA
b0
c0
d0
e0
f0
RQ11..0
(PRE)
RQ11..0
(ALL)
REFP
REFP
REFP
REFP
a1
b1
c1
d1
REFA
REFA
REFA
REFP
REFA
REFP
REFA
REFP
REFA
REFP
a0
b0
c0
a1
d0
b1
e0
c1
f0
d1
DQ15..0
DQN15..0
T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CFM
CFMN
This REFI increments REFR
RQ11..0
(ACT)
REFA
REFI
REFA
g0
h0
i0
RQ11..0
(PRE)
RQ11..0
(ALL)
tCYCLE
REFP
REFP
REFP
REFP
e1
f1
g1
h1
REFA
REFP
REFA
REFP
REFA
REFP
REFP
g0
e1
h0
f1
i0
g1
h1
DQ15..0
DQN15..0
Ba,Bb,Bc,Bd,
Be,Bf,Bg and
Bh are
different banks.
Bi = Ba
Transaction a: REF
Transaction b: REF
Transaction c: REF
Transaction d: REF
Transaction e: REF
Transaction f: REF
Transaction g: REF
Transaction h: REF
Transaction i: REF
a0 = {Ba,REFR}
b0 = {Bb,REFR}
c0 = {Bc,REFR}
d0 = {Bd,REFR}
e0 = {Be,REFR}
f0 = {Bc,REFR}
g0 = {Bd,REFR}
h0 = {Be,REFR}
i0 = {Ba,REFR+1}
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a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
d1 = {Bd}
e1 = {Be}
f1 = {Bf}
g1 = {Bg}
h1 = {Bh}
i1 = {Bi}
Interleaved Refresh Example
Rev. 1.1 August 2006
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XDRTM DRAM
10.3 Calibration Transactions
Figure45 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported: calibration
of the output current level IOL, each DQi and DQNi pin.
The output current calibration sequence is shown in the upper diagram. It begins when a period of tCMD-CALC is observed after the last
RQ packet (with command “CMD a” in this example). No request packets should be issued in this period.
A COLX packet with a “CALC b” command is then issued to start the current calibration sequence. A period of tCALCE is observed after
this packet. No request packets should be issued during this period.
A COLX packet with a “CALE c” command is then issued to end the current calibration sequence. A period of tCALE-CMD is observed after
this packet. No request packets should be issued during this period. The first request packet may then be issued (with command “CMD
d” in this example).
A second current calibration sequence must be started within an interval of tCALC. In this example. the next COLX packet with a “CALC
e” command starts a subsequent sequence.
The dynamic termination calibration sequence is shown in the lower diagram. Note that this memory component does not use this
sequence; termination calibraion is performed during the manufacturing process. However, the termination sequence shown will be
issued by the controller for those memory component which do use a periodic calibration mechanism.
It begins when a period of tCMD-CALZC is observed after the packet edge T0(with command CMDa in this example). No request packets
should be issued in this period.
A COLX packet with a CALZ command is then issued at edge T3 to start the current calibration sequence. A second period of tCALZE is
ovserved after this packet. No request packets should be issued during this period.
A COLX packet with a CALE command is then issued at dege T6 to end the current calibration sequence. A third period of tCALE-CMD is
observed after this pakets. No request packets should be issued during this period. The first request pakcet may be issued at edge
T12(with command CMDd in this example).
A second current calibration sequence must be started within an interval of tCALZ. In this example, the next COLX pakcet with a CALZ
command occurs at edge T20.
Note that the labels for the CFM clock edges(of the form Ti) are not to scale, and are used to identify events in the diagrams.
Figure 45 : Calibration Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
CMD
CALC
a
tCALCE,
tCALE-CMD,
CALE
c
b
tCMD-CALC
DQ15..0
DQN15..0
CMD
CALC
d
e
tCALC
Packet a: Any CMD
Packet b: CALC
Packet c: CALE
Packet d: Any CMD
Packet e: CALC
T0
T1
T2
tCYCLE
T3
T4
T5
Current Calibration Transaction
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ15..0
DQN15..0
CMD
CALZ
a
b
tCALZE,
CALE
tCALE-CMD,
c
tCMD-CALZ
CMD
CALZ
d
e
tCYCLE
tCALZ
Packet a: Any CMD
Packet b: CALZ
Packet c: CALE
Packet d: Any CMD
Packet e: CALZ
Termination Calibration Transaction
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10.4 Power State Management
Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown
and Active. Powerdown state is to be used in applications in which it is necessary to shut down the CFM/CFMN clock signals. In this
state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine which performs periodic refresh
operations using the REFB and REFr control registers.
The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of XDR DRAM must be
precharged so they are left in a closed state. Also, all 23 banks must be refreshed using the current value of the REFr registers, and the
REFr registers must not be incremented with the REFI command at the end of this special set of refresh transactions. This ensures that
no matter what value has been left in the REFB register, no row of any bank will be skipped when automatic refresh is first started in
Powerdown. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown
entry process.
After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of tCMD-PDN is observed. No
request packets should be issued during this period.
A COLX packet with the PDN command is issued after this interval, causing the XDR DRAM to enter Powerdown state after an interval
of tPDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM). The CFM/
CFMN clock signals may be removed a time tPDN-CFM after the COLX packet with the PDN command. Also, the termination voltage
supply may be removed (set to the ground reference) from the Vterm pins a time tPDN-CFM after the COLX pakcet with the PDN
command. The voltage on the DQ/DQN pins will follow the voltae on the Vterm pins during Powerdonwn entry.
When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically generate internal refresh
transactions. It will cycle through all 23 state combinations of the REFB register. When the largest value is reached and the REFB value
wraps around, the REFr register is incremented to the next value. The REFB and REFr values select which bank and which row are
refreshed during the next automatic refresh transaction.
The lower diagram shows the sequence needed for Powerdown exit. The sequence is started with a serial broadcast write (SBW
command) transaction using the serial bus of the XDR DRAM. This transaction writes the value “00000001” to the Power Management
(PM) register (SADR = “00000011”) of all XDR DRAMs connected to the serial bus. This sets the PX bit of the PM register, causing the
XDR DRAMs to return to Active power state.
The CFM/CFMN clock signals must be stable a time tCFM-PDN before the end of the SBW transaction. Also, the termination voltage
supply must be restored to its normal operating point (VTERM,DRSL) on the Vterm pins a time tCFM-PDN before the end of the SWB transaction. The voltage on the DQ/DQN pins will follow the voltage on the Vterm pins during Powerdown exit.
The XDR DRAM will enter Active state after an interval of tPDN-EXIT has elapsed from the end of the SBW transaction (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM).
The first request packet may be issued after an interval of tPDN-CMD has elapsed from the end of the SBW transaction, and must contain
a “REFA” command in a ROWP packet. In this example, this packet is denoted with the command “REFA 1”. No other request packets
should be issued during this tPDN-CMD interval.
All “n” banks (in the example, n=23) must be refreshed using the current value of the REFr registers. The “nth” refresh transaction will
use a “REFI” command to inrement the REFr register (instead of a “REFR” command). This ensures that no matter what value has been
left in the REFB register, no row of any bank will be skipped when normal refresh is restarted in Active state. There may be some banks
at the current row value in the REFr registers that are refreshed twice during the Powerdown exit process.
Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the tPDN-CMD interval, no
internal refresh operations are performed. As a result, an additional burst of refresh transactions must be issued after the burst of “n”
transactions described above. This second burst consists of “m” refresh transactions:
m = ceiling[23*212*tPDN-CMD/tREF]
Where “212” is the number of rows per bank, and “23” is the number of banks. Every ”nth” refresh transaction (where n=23) will use a
“REFI” command (to increment the REFr register) instead of a “REFA” command.
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Figure 46 : Power State Management
CFM
CFMN
No signal
CMD
RQ11..0
tCYCLE
tPDN-CFM
PDN
ba
a
Powerdown State...
DQ15..0
DQN15..0
tPDN-ENTRY
tCMD-PDN
Transaction a: Last precharge command
Transaction b: PDN
S0
S2
S4
S6
S8
Powerdown Entry
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34
SCK
RST
CMD
tCYC,SCK
Power-up transaction
Start
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
5
4
3
2
SADR[7:0]
1
0
7
6 5
4 3
2
SWD[7:0]
1
0 ‘0’ 7
6
5
4
3
2
1
0 ‘0’
SDI
(input)
SDO
(output)
CFM
CFMN
No signal
tCFM-PDN
RQ11..0
tCYCLE
tPDN-EXIT
....Powerdown State
DQ15..0
DQN15..0
tPDN-CMD
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
REFA
REFA
REFI
REFP
1
2
n
n-2
REFP
REFP
n-1
n
tCYCLE
tPDN-CMD
Transaction 1: REFA
Transaction 2: REFA
The final REFA/REFI command increments the REFr register
Transaction n-1: REFA
Transaction n: REFI
Powerdown Exit
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10.5 Initialization
Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are transmitted by the controller and are received by each XDR DRAM device along the bus. The signals are terminated to the VTERM supply
through termination components at the end farthest from the controller. The SDI input of the XDR DRAM device furthest from the
controller is also terminated to VTERM. The SDO output of each XDR DRAM device is transmitted to the SDI input of the next XDR
DRAM device (in the direction of the controller). This SDO/SDI daisy chain topology continues to the controller, where it ends at the SRD
input of the controller. All the serial interface signals are low-true. All the signals use RSL signaling circuits, except for the SDO output
which uses CMOS signaling circuits.
Figure 47 : Serial Interface Systems Topology
RST CMD SCK
RST CMD SCK
SRD
SDO
Controller
SDI
VTERM
RST CMD SCK
...
SDO
XDR DRAM [63]
SDI
RST CMD SCK
...
SDO
XDR DRAM [j]
SDI
XDR DRAM [0]
Figure48 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown above. Prior to initialization, the RST is held at zero. The CMD input is not used here, and should also be held at zero. Note that the inputs are all sampled by
the negative edge of the SCK clock input. The SDI input for the XDR DRAM[0] device is zero, and is unknown for the remaining devices.
On negative SCK edge S8 the RST input is sampled one. It is sampled one on the next four edges, and is sampled zero on edge S12 a
time tRST-10 after it was first sampled one. The state of the control registers in the XDR DRAM device are set to their reset values after
the first edge (S8) in which RST is sampled one.
Figure 48 : Initialization Timing for XDR DRAM [k] Device
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
tCYC,SCK
tRST-10
RST
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDI,00 = k * tCYC,SCK
CMD
SDI
(input)
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
SDO
(output)
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDO,11
tSDI-SDO,00
The SDI inputs will be sampled one within a time tRST-SDO,11 after RST is first sampled one in all the XDR DRAMs except for XDR DRAM
[0]. XDR DRAM [0]’s SDI input will always be sampled zero.
XDR DRAM [k] will see its RST input sampled zero at S12, and will then see its SDI input sampled zero at S16 (after SDI had previously
been sampled one). This interval (measured in tCYC,SCK units) will be equal to the index [k] of the XDR DRAM device along the serial
interface bus. In this example, k is equal to 4.
This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time tSDI-SDO,00 after its SDI input is
sample zero.
In other words, the XDR DRAM [0] device will see RST and SDI both sampled zero on the same edge S12 (tRST-SDI,00 will be 0 *tCYC,SCK
units), and will drive its SDO to zero around the subsequent edge (S13).
The XDR DRAM [1] device will see SDI sampled zero on edge S13 (tRST-SDI,00 will be 1*tCYC,SCK units), and will drive its SDO to zero
around the subsequent edge (S14).
The XDR DRAM [2] device will see SDI sampled zero on edge S14 (tRST-SDI,00 will be 2* tCYC,SCK units), and will drive its SDO to zero
around the subsequent edge (S15).
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This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state machine
which measures the interval tRST-SDI,00 between the edges in which RST and SDI are both sampled zero, and uses this value to set the
SID [5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to be made to the individual
XDR DRAM devices.
Table 10 summarizes the range of the timing parameters used for initialization by the serial interface bus.
Table 10 : Initialization Timing Parameters
Symbol
Parameter
Min
Max
Unit
Figure (s)
tRST,10
Number of cycles between RST being sampled one and RST being sampled
zero
2
-
tCYC,SCK
-
tRST-SDO,11
Number of cycles between RST being sampled one and SDO being driven to
one
1
1
tCYC,SCK
-
tRST,SDI,00
Number of cycles between RST being sampled zero (after being sampled one
for tRST,10,MIN or more cycles) and SDI being sampled zero. This will be equal
to the index [k] of the XDR DRAM device along the serial interface bus
0
63
tCYC,SCK
-
tSDI-SDO,00
Number of cycles between SDI being sampled one (after RST has been sampled one for tRST,10,MIN or more cycles and is then sampled zero) and SDO
being driven to zero
1
1
tCYC,SCK
-
Asynchronous reset interval.
20
-
tCYC,SCK
-
tRST-SCK
10.6 XDR DRAM Initialization Overview
[1] Apply voltage to VDD, VTERM, and VREF pins. VTERM and VREF voltages must be less or equal to VDD voltage at all times. Wait a
time interval tCOREINIT. Power-on reset circuit in XDR DRAM places XDR DRAM into low-power state.
[2] Assert RST, SCK, SDI and CMD to logical zero, Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR DRAM into low-power state(identical to power-on reset)
- Perform remaining initialization sequence in Figure 48.
[3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure17 through Figure42.
[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure46. This includes the activity from SCK cycle S0 through the final REFP
command.
[6] Perform termination/current calibration. The CALZ /CALE sequence shown in Figure 45 is issued 128 times. After this, each
sequence is issued once every tCALZ or tCALC interval.
[7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each bank eight times. This
can be interleaved to save time. The row address for the activate operation will step through eight successive values of the REFr
registers. The sequence between cycles T0 and T32 in the Interleaved Refresh Example in Figure 44 could be performed eight times
to satisfy this conditioning requirement.
10.7 XDR DRAM Pattern Load with WDSL Register
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning Receive Timing
Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is called Write Data Serial Load (WDSL). A WDSL
packet sends one-byte of serial data which is serially shifted into a holding register within the XDR DRAM. Initialization software sends a
sequence of WDSL packets, each of which shifts the new byte in and advances the shifter by 8 positions. In this way, XDR DRAMs of
varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of data to the internal holding register of the target XDR DRAM. Depending
upon the ratio of native device width to programmed width, there may be more than one sub-column per column. After loading a full
column, a series of WR commands will be issued to sequentially transfer each sub-column of the column to the XDR DRAM core(s),
based upon the SC [3:0] bits.
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Table 11 : XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4/x2 XDR DRAM, BL = 16)
WDSL Core
Word Load Order
DQ Pins ‘
x16
x8
x4
x2
Core Word
x8
x16
WD[n][15:0]
SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:2] SC[3:1] SC[3:1] SC[3:1] SC[3:1] SC[3:1] SC[3:1] SC[3:1] SC[3:1]
=xx
= 0x
= 1x
= 00
= 01
= 10
= 11
= 000
= 001
= 010
= 011
= 100
= 101
= 110
= 111
x2
x4
DQ0
DQ0
DQ0
DQ0 WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
DQ1
DQ1
DQ1
DQ1 WD[1][15:0]
WDSL Word 7
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
DQ0
DQ2
DQ2
DQ2 WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
DQ1
DQ3
DQ3
DQ3 WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
DQ0
DQ0
DQ4
DQ4 WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
DQ1
DQ1
DQ5
DQ5 WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
DQ0
DQ2
DQ6
DQ6 WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
DQ1
DQ3
DQ7
DQ7 WD[7][15:0]
WDSL Word 1
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
DQ0
DQ0
DQ0
DQ8 WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
DQ1
DQ1
DQ1
DQ9 WD[9][15:0]
WDSL Word 6
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
DQ0
DQ2
DQ2
DQ10 WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
DQ1
DQ3
DQ3
DQ11 WD[11][15:0]
WDSL Word 2
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
DQ0
DQ0
DQ4
DQ12 WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
DQ1
DQ1
DQ5
DQ13 WD[13][15:0]
WDSL Word 4
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
DQ0
DQ2
DQ6
DQ14 WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
DQ1
DQ3
DQ7
DQ15 WD[15][15:0]
WDSL Word 0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
LOGICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
PHYSICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ14 WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
DQ6 WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
DQ10 WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
DQ2 WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
DQ12 WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
DQ4 WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
DQ8 WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
DQ0 WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
DQ1 WD[1][15:0]
WDSL Word 7
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
DQ9 WD[9][15:0]
WDSL Word 6
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
DQ5 WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
DQ13 WD[13][15:0]
WDSL Word 4
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
DQ3 WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
DQ11 WD[11][15:0]
WDSL Word 2
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
DQ7 WD[7][15:0]
WDSL Word 1
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
DQ15 WD[15][15:0]
WDSL Word 0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
DQ6
DQ2
DQ2
DQ0
DQ4
DQ0
DQ0
DQ1
DQ1
DQ5
DQ1
DQ3
DQ3
DQ7
Table 12 : Core Data Word-to-WDSL Formata
DQ Serialization Order
CFM/PCLK Cycle
Cycle 0
Cycle 1
Symbol (Bit) Time
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Bit Transmitted on DQ pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WDSL Byte/Bit Transfer Order
Core Word
Core Word WD[n][15:0]
WDSL Byte Order
WDSL Byte 0
WDSL Byte 1
SWD Field of Serial Packet
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Transmitted on CMD pin
D15
D11
D7
D3
D14
D10
D6
D2
D13
D9
D5
D1
D12
D8
D4
D0
a. Applies for first generation x16/x8/x4/x2 XDR DRAM with BL=16
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10.8 Sub-Row (Sub-Page) Sensing
The SP[1:0] field of the CFG register controls what fraction of a row is sensed during a ROWA activate operation. This permits the controller to reduce the amount of power consumed by normal transactions if a smaller row size can be tolerated by the application. Note
that the REFA and REFI activate operations always sense the full row, the SP[1:0] setting does not affect these operations. Refresh
operations during Powerdown are likewise unaffected by the SP[1:0] setting.
The permissible values of the SP[1:0] field are affected by the value programmed into the WIDTH[2:0] field of the CFG register. The table
in the following figure summarizes the allowed combinations of values.
In general the value of WIDTH[2:0] is chosen, and this then limits the possible values of SP[1:0] that can be used, as seen by the table in
the figure above. In other words, the combinations indicated by the gray boxes labeled “NO” may not be used, since this would allow
accessing of sense amplifier cells with invalid data.
If half-row activation is selected (with SP[1:0] = 01), then the value of SR[1] used in the ROWA packet for activation must be the same as
the value of SC[1] used in the COL/COLM packet for a read/write access.
XDR DRAM device will operate in half-activation mode, even when programmed for quarter-activation (with SP[1:0] = 10).
Figure 49 Sub-Row Example
Allowed combinations of
WIDTH[2:0]
WIDTH[2:0]
SP[1:0]
x4
x8
x16
001
010
010
010
SP[1:0]
SC[3:0]
SR[1:0]
x2
allowed
SR[1:0]
values for
each SP[1:0]
combination
full
00
OK
OK
OK
OK
xx
half
01
OK
NO
NO
NO
0x,1x
000x
00xx
allowed
SC[3:0]
values for
each WIDTH
combination
001x
010x
01xx
NOTE - for half-activation, the
following relationship must be
observed : SR[1]=SC[1]
0xxx
011x
100x
101x
110x
xxxx
10xx
11xx
1xxx
111x
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11.0 Special Feature Description
11.1 Write Masking
Figure 50 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This
masking logic permits individual byte of a write data packet to be written or not written according to the value of an eight bit write mask M
[7:0].
In Figure 50, there are 16 sets of 16 bit signals forming the D1[15:0] [15:0] input bus for the Byte Mask block. These are treated as 2 x 16
8-bit bytes:
D1 [15] [15.8]
D1 [15] [7:0]
...
D1 [1] [15:8]
D1 [1] [7:0]
D1 [0] [15:8]
D1 [0] [7:0]
The eight bits of each byte is compared to the value in the byte mask field (M[7:0]). If they are not equal (NE), then the corresponding
write enable signal (WE) is asserted and the byte is written into the sense amplifier. If they are equal, then corresponding write enable
signal (WE) is deasserted and the byte is not written into the sense amplifier.
In the example of Figure 50, a WRM command performs a masked write of a 64 byte data packet to all the memory devices connected
to the RQ bus (and receiving the command). It is the job of the memory controller to search the 64 bytes to find an eight bit data value
that is not used and place it into the M [7:0] field. This will always be possible because there are 256 possible 8-bit values and there are
only 64 possible values used in the bytes in the data packet.
Figure 50 : Byte Mask Logic
S[15][15:8]
S[15][7:0]
8
WE-MSB
[15]
1
NE
8
Compare
8
8
8
8
Compare
8
8
8
D1[15][15:8]
S[0][7:0]
8
WE-MSB
[0]
1
NE
8
WE-LSB
[0]
1
NE
8
Compare
8
8
8
Compare
8
8
D1[15][7:0]
D1[15][15:8]
M[7:0]
S[0][15:8]
WE-LSB
[15]
1
NE
D1[0][15:8]
8
8
D1[15][7:0]
D1[0][15:8]
D1[0][7:0]
8
D1[0][7:0]
S[15:0][15:0]
16x16
16x16
8
M[7:0]
4+3
WIDTH[2:0]
SC[3:0]
Byte Mask (WR)
16x16
D1[15:0][15:0]
Width Demux (WR)
4+3
Width Mux (RD)
16x16
WIDTH[2:0]
SC[3:0]
16x16
D[15:0][15:0]
Q[15:0][15:0]
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Note that other systems might use a data transfer size that is different than the 64 bytes per tCC interval per RQ bus that is used in the
example in Figure 50.
Figure 51 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two successive WR
commands in COL packets. The one difference is that the COLM packet includes a M[7:0] field that indicates the reserved bit pattern (for
the eight bits of each byte) that indicates that the byte is not to be written. This requires that the alignment of bytes within the data packet
be defined, and also that the bit numbering within each byte be defined (note that this was not necessary for the unmasked WR
command). In the figure, bytes are contained within a single DQ/DQN pin pair. Thus, each pin pair carries two bytes of each data packet.
Byte[0] is transferred earlier than byte[1], and bit[0] of each byte (corresponding to M [0]) is transferred first, followed by the remaining
bits in succession).
Figure 51 : Write-Masked (WRM) Transaction Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WRM
a1
DQ15..0
DQN15..0
WRM
a2
tCYCLE
RD
a1
tCC
tCWD
D(a1)
D(a2)
tCAC
Q(a1)
Bit- and Byte-numbering convention for write
and read data packets.
Byte [16+0]
Byte [0]
DQ0
DQN0
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Byte [1]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Byte [15]
DQ15
DQN15
[10] [11] [12] [13] [14] [15]
...
[0]
Byte [16+1]
...
DQ1
DQN1
[10] [11] [12] [13] [14] [15]
[0]
[1]
[2]
[3]
[4]
Byte [16+15]
[5]
[6]
[7]
[8]
[9]
52 of 76
[10] [11] [12] [13] [14] [15]
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11.2 Multiple Bank sets and the ERAW Feature
Figure 54 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the odd
bank set) according to the least-significant bit of the bank address field. This XDR DRAM supports a feature called “Early Read After
Write” (hereafter called “ERAW”)
The logic that accepts commands on the RQ11...0 signals is capable of operating these two bank sets independently. In addition, each
bank set connects to its own internal “S” data bus (called S0 and S1). The receive interface is able to drive write data onto either of these
internal data buses, and the transmit interface is able to sample read data from either of these internal data buses. These capabilities will
permit the delay between a write column operation and a read column operation to be reduced, thereby improving performance.
Figure 52 shows the timing previously presented in Figure12, but with the activity on the internal S data bus included. The write-to-read
parameter t∆WR ensures that there is adequate turnaround time on the S bus between D (a2) and Q (c1).
When ERAW is supported with odd and even bank sets, the t∆WR,MIN parameter must be obeyed when the write and read column operations are to the same bank set, but a second parameter t∆WR-D permits earlier column operations to the opposite bank set. Figure 53
shows how this is possible because there are two internal data buses S0 and S1. In this example, the four columns read operations are
made to the same bank Bb, but they could use different banks as long as they all belonged to the bank set that was different form the
bank set containing Ba (for the column write operations).
Figure 52 : Write/Read Interaction - No ERAW Feature
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
WR
a2
RD
c1
t∆WR
DQ15..0
DQN15..0
D(a1)
D(a2)
tCWD
RD
c2
tCYCLE
tCAC
Q(c1)
tWR-BUB,XDRDRAM
Q(c2)
tCC
turnaround
tCC
S[15:0]
[15:0]
D(a1)
D(a2)
Q(c1)
a1 = {Ba,Ca1}
c1 = {Bc,Cc1}
Transaction a: WR
Transaction c: RD
Q(c2)
a2 = {Ba,Ca2}
c2 = {Bc,Cc2}
Figure 53 : Write/Read Interaction - ERAW Feature
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
RD
b1
WR
a2
t∆WR-D
DQ15..0
DQN15..0
D(a1)
tCWD
tCAC
RD
b2
RD
b3
D(a2)
Q(b2)
D(a1)
Q(b1)
Transaction a: WR
Transaction b: RD
Transaction c: RD
Q(b3)
Q(b4)
D(a2)
Q(b2)
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
53 of 76
Q(c1)
tCC
turnaround
tCC tWR-BUB,XDRDRAM
S1[15:0]
[15:0]
tCYCLE
RD
c1
Q(b1)
S0[15:0]
[15:0]
Bank Restrictions
Bb is in different bank set than Ba
Bc is in same bank set as Ba
RD
b4
Q(c1)
Q(b3)
Q(b4)
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
b4 = {Bb,Cb4}
Rev. 1.1 August 2006
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XDRTM DRAM
Figure 54 : XDR DRAM Block Diagram with Bank Sets
RQ11..0
12
1:2 Demux
Reg
COL
decode
6
3
...
1
1
...
COL logic
1
3
Bank (2 -2)
16x16*26
16x16
R/W
COL
...
WR even
16x16*26
COL
16x16
...
WR odd
Sense Amp Array
R/W
Sense Amp 0
3
Sense Amp (2 -2)
...
6
6
Bank 0
PRE
...
...
ROW
PRE
1
6
6
COL
ROW
...
1
R/W
ACT
...
16x16
S0[15:0][15:0]
RD odd
RD even
16x16
16x16
Byte Mask (WR)
Width Demux (WR)
16x16
Width Mux (RD)
Q[15:0][15:0]
D[15:0][15:0]
16x16
16
16
1:16 Demux
16:1 Mux
16/tCC
16
...
......
16x16
S1[15:0][15:0]
...
1
...
-1)
1
ACT
16x16*26
...
Sense Amp(23
PRE logic
1
R/W
COL
Sense Amp 1
...
...
1
16x16*26
Sense Amp Array
...
12
12
PRE
16x16*26
1
12
ROW
12
PRE
Bank(23-1)
ACT logic
...
1
ACT
ROW
Even
Bank
Array
Bank 0
16x16*26*212
1
...
ACT
16x16*26
3
...
16x16*26*212
Bank 1
ACT
decode
3
12
...
Odd
Bank
Array
Bank 0
PRE
decode
16/tCC
16
16
DQ15..0
16
DQN15..0
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11.3 Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in Figure 54, another feature may be supported, in addition to ERAW. This feature
is simultaneous activation, and the timing of several cases is shown in Figure 55.
The tRR parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single bank set, or
between packets to the same bank set in a XDR DRAM with multiple bank sets. The tRR-D parameter specifies the minimum spacing
between packets with activation commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure 55, Case 4 shows an example when both tRR and tRR-D must be at least 4*tCYCLE. In such a case, activation commands to different bank sets satisfy the same constraint as activation commands to the same bank set.
In Figure 55, Case 2 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 2*tCYCLE. In such a case, an activation command to one bank set may be inserted between two activation commands to a different bank set.
In Figure 55, Case 1 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 1*tCYCLE. As in the previous
case, an activation command to one bank set may be inserted between two activation commands to a different bank set. In this case, the
middle activation command will not be symmetrically placed relative to the two outer activation commands.
In Figure 55, Case 0 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 0*tCYCLE. This means that two
activation commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two
commands. See “Dynamic Request Scheduling” on page 23. In the example shown, the packet with the REFA command is received one
cycle before the command with the ACT command, and the REFA command includes a one cycle delay. Both activation commands will
be issued internally to different bank sets on the same CFM clock edge.
Figure 55 : Simultaneous Activation — tRR-D Cases
Case 4: tRR-D = 4*tCYCLE
REFA & ACT have same tRR
T0
T1
T2
T3
T4
T5
T6
T7
T8
Case 2: tRR-D = 2*tCYCLE
REFA fits between two ACT
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT
REFA
ACT
ACT
tRR-D
tRR-D
REFA
tRR-D
DQ15..0
DQN15..0
tRR
T1
T2
T3
T4
T5
tCYCLE
note - REFA is directed to bank
set different from two ACT
Case 0: tRR-D = 0*tCYCLE
REFA simultaneous with ACT
(REFA uses delay=1*tCYCLE)
Case 1: tRR-D = 1*tCYCLE
REFA fits between two ACT
T0
ACT
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
ACT REFA
REFA ACT
ACT
ACT
tCYCLE
tRR-D
tRR-D
tRR
note - REFA is directed to bank
set different from two ACT
55 of 76
tRR
note - REFA is directed to bank
set different from ACT at T12
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XDRTM DRAM
11.4 Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in Figure54, another feature may be supported, in addition to ERAW. This feature
is simultaneous precharge, and the timing of several cases is shown in Figure56.
The tPP parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single bank set, or
between packets to the same bank set in a XDR DRAM with multiple bank sets. The tPP-D parameter specifies the minimum spacing
between packets with precharge commands to different bank sets in a XDR DRAM with multiple bank sets.
In Figure56, Case4 shows an example when both tPP and tPP-D must be at least 4*tCYCLE. In such a case, precharge commands to
different bank sets satisfy the same constraint as precharge commands to the same bank set.
In Figure56, Case2 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 2*tCYCLE. In such a case, a
precharge command to one bank set may be inserted between two precharge commands to a different bank set.
In Figure56, Case1 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 1*tCYCLE. As in the previous case,
a precharge command to one bank set may be inserted between two precharge commands to a different bank set. In this case, the
middle precharge command will not be symmetrically placed relative to the two outer precharge commands.
In Figure56, Case0 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 0*tCYCLE. This means that two
precharge commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two
commnads. See “Dynamic Request Scheduling” on page 23. It is also possibly by taking advantage of the fact that two independent
precharge commands may be encoded within a single ROWP packet. In the example shown, the ROWP packet contains both a REFP
command and a PRE command. Both precharge commands will be issued internally to different bank sets on the same CFM clock edge.
Figure 56 : Simultaneous Precharge — tPP-D Cases
Case 4: tPP-D = 4*tCYCLE
REFP & PRE have same tRR
T0
T1
T2
T3
T4
T5
T6
T7
T8
Case 2: tPP-D = 2*tCYCLE
REFP fits between two PRE
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
REFP
PRE
PRE
tPP-D
tPP-D
REFP
PRE
tPP-D
DQ15..0
DQN15..0
note - REFP is directed to bank
set different from two PRE
tPP
Case 0: tPP-D = 0*tCYCLE
REFP simultaneous with PRE
Case 1: tPP-D = 1*tCYCLE
REFP fits between two PRE
T0
T1
T2
T3
T4
T5
tCYCLE
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
PRE REFP
PRE
PRE
PRE
tCYCLE
REFP
tPP-D
tPP-D
tPP
note - REFP is directed to bank
set different from two PRE
56 of 76
tPP
note - REFP is directed to bank
set different from PRE at T12
Rev. 1.1 August 2006
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XDRTM DRAM
12.0 Operating Conditions
12.1 Electrical Conditions
Table13 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory component. The
first section of parameters is concerned with absolute voltage, storage and operating temperatures, and the power supply, reference,
and termination voltages.
The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must satisfy a
symmetry parameter with respect to the VREF, RSL.
The third section of parameters determines the input voltage levels for the RSL SI(serial interface) signals. The high and low voltages
must satisfy a symmetry parameter with respect to the VREF, RSL.
The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are specified
by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and low voltages are specified by a common-mode value and a swing value.
Table 13 : Electrical Conditions
Minimum
Maximum
Unit
VIN,ABS
Symbol
Voltage applied to any pin (except VDD) with respect to GND
Parameter
- 0.3
1.5
V
VDD,ABS
Voltage on VDD with respect to GND
- 0.5
2.3
V
TSTORE
Storage temperature
- 50
100
°C
TJ
Junction temperature under bias during normal operation
-
100
°C
0
TJ,MAX
°C
1.8 - 0.09
1.8 + 0.09
V
VTERM,RSL
- 0.450 - 0.025
VTERM,RSL
- 0.450 + 0.025
V
1.2 - 0.06
1.2 + 0.06
V
TMIN
Operating Temperature
VDD
Supply voltage applied to VDD pins during normal operation
VREF,RSL
RSL - Reference voltage applied to VREF pina
VTERM,DRSL
DRSL - Termination voltage applied to VTERM pins
VIL,RQ
RSL RQ inputs -low voltage
VREF,RSL - 0.45
VREF,RSL - 0.15
V
VIH,RQb
RSL RQ inputs -high voltage
VREF,RSL + 0.15
VREF,RSL + 0.45
V
RA,RQ
RSL RQ inputs - data asymmetry:
RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ)
0.8
1.2
V
VIL,SI
RSL Serial Interface inputs -low voltage
VREF,RSL - 0.45
VREF,RSL - 0.20
V
VIH,SIb
RSL Serial Interface inputs -high voltage
VREF,RSL + 0.20
VREF,RSL + 0.45
V
RA,SI
RSL Serial Interface inputs - data asymmetry:
RA,SI = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ)
0.8
1.2
V
VICM,CFM
CFM/CFMN input - common mode: VICM,CTM = (VIH,CFMb+VIL,CTM)/2 VTERM,DRSL-0.150
VTERM,DRSL-0.075
V
VISW,CFM
CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CTMb - VIL,CTM)
0.15
0.30
V
VICM,DQ
DRSL DQ inputs - common mode: VICM,DQ = (VIH,DQb+VIL,DQ)/2
VTERM,DRSL-0.150
VTERM,DRSL-0.025
V
0.05
0.30
V
VISW,DQ
DRSL DQ inputs - high-low swing: VISW,DQ =
(VIH,DQb
- VIL,DQ)
a.VTERM,RSL is typically 1.2V±0.06V. It connects to the RSL termination components, not to this DRAM component.
b.VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system.
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12.2 Timing Conditions
Table14 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is concerned
with parameters for the clock signals. The second section of parameters is concerned with parameters for the request signals. The third
section of parameters is concerned with parameters is concerned with parameters for the write data signals. The fourth section of parameters is concerned with parameters for the serial interface signals. The fifth section is concerned with all other parameters, including
those for refresh, calibration, power state transitions, and initialization.
Table 14 : Timing Conditions
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
2.00
2.50
3.33
3.83
3.83
3.83
ns
ns
ns
Figure 57
Figure 57
tCYCLE or tCYC,CTM
CFM RSL clock - cycle time
-4000
-3200
-2400
tR,CFM, tF,CFM
CFM/CFMN input - rise and fall time - use minimum for test.
0.08
0.20
tCYCLE
tH,CFM, tL,CFM
CFM/CFMN input - high and low times
40%
60%
tCYCLE
Figure 57
tR,RQ, tF,RQ
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
0.08
0.26
tCYCLE
Figure 58
tS,RQ, tH,RQ
RSL RQ input to sample points (set/hold)
@ 2.50 ns > tCYCLE ≥ 2.00 ns
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
0.170
0.200
0.275
-
ns
ns
ns
Figure 58
tIR,DQ, tIF,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
0.020
0.074
tCYCLE
Figure 59
tS,DQ, tH,DQ
DRSL DQ input to sample points (set/hold)
@ 2.50 ns > tCYCLE ≥ 2.00 ns
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
0.052
0.065
0.080
-
ns
ns
ns
Figure 59
tDOFF,DQ
DRSL DQ input delay offset (fixed) to sample points
-0.08
+0.08
tCYCLE
Figure 59
tCYC,SCK
Serial Interface SCK input - cycle time
20
-
ns
Figure 61
tR,SCK, tF,SCK
Serial Interface SCK input - rise and fall times
-
5.0
ns
Figure 61
tH,SCK, tL,SCK
Serial Interface SCK input - high and low times
40%
60%
tCYC,SCK
Figure 61
tIR,SI, tIF,SI
Serial Interface CMD,RST,SDI input - rise and fall times
-
5.0
ns
Figure 61
tS,SI,tH,SI
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
5
-
ns
Figure 61
tDLY,SI-RQ
Delay from last SCK clock edge for register write to first CFM edge with RQ
packet containing a command which uses the value in the register. Also, delay
from first CFM edge with RQ packet containing a command which modifies register value to the first SCK clock edge for register read to this register.
10
-
tCYC,SCK
-
tREF
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
-
16
ms
Figure 44
tREFA-REFA,AVG
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon tREF and the number of
banks and the number of rows: tREFI = tREF/(NB*NR) = tREF/(23*211).
ns
-
NREFA,BURST
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
tBURST-REFA
Refresh burst interval. The interval between a burst of NREFA,BURST,MAX ROWPREFA or ROWP-REFI commands and the next ROWP-REFA or ROWP-REFI
command.
tCOREINIT
Interval needed for core initialialization after power is applied.
tCALC
Current calibration interval
tCMD-CALC, tCMD-CALZ
tCALCE, tCALZE
tREFA-REFA,AVG = 488
-
128
commands
-
40
-
tCYCLE
-
-
1.5
ms
-
-
100
ms
Figure 45
Delay between packet with any command and CALC/CALZ packet
w/ PRE or REFP command
w/ any other command
4
16
-
tCYCLE
Figure 45
Delay between CALC/CALZ packet and CALE packet
12
-
tCYCLE
Figure 45
Figure 45
tCALE-CMD
Delay between CALE packet and packet with any command
24
-
tCYCLE
tCMD-PDN
Last command before PDN entry
16
-
tCYCLE
Figure 46
tPDN-CFM
RSL CFM/CFMN and VTERM stable after PDN entry
16
-
tCYCLE
Figure 46
tCFM-PDN
RSL CFM/CFMN and VTERM stable before PDN exit
16
-
tCYCLE
Figure 46
tPDN-CMD
First command after PDN exit (includes lock time for CFM/CFMN)
4096
-
tCYCLE
Figure 46
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13.0 Operating Characteristics
13.1 Electrical Characteristics
Table15 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory component. The only
exception is the supply current values(IDD) under different operating conditions covered in the Supply Current Profile section.
The first section of parameters is concerned with the thermal characteristics of the memory component.
Ther second section of parameters is concerned with the current needed by the RQ pins and VREF pin.
The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced by the DQ pins when
driving read data. This section is also concerned with the current needed by the VTERM pin, and with the resistance levels produced for
the internal termination components that attach to the DQ pins.
The fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals.
Table 15 : Electrical Characteristics
Symbol
Parameter
Minimum
Maximum
Units
ΘJC
Junction-to-case thermal resistance
°C/Watt
II,RSL
RSL RQ or Serial Interface input current @ ( VIN= VIH,RQ,MAX)
-10
10
uA
IREF,RSL
VREF,RSL current @ VREF,RSL,MAX flowing into VREF pin
-10
10
uA
VOSW,DQ
DRSL DQ outputs - high-low swing: VOSW,DQ=(VIH,DQ-VIL,DQN)
or (VIH,DQN-VIL,DQ)
0.200
0.400
V
RTERM,DQ
DRSL DQ outputs - termination resistance
40.0
60.0
Ω
VOL,SI
RSL serial interface SDO output - low voltage
0.0
0.25
V
VOH,SI
RSL serial interface SDO output - high voltage
VTERM,RSL - 0.25
VTERM,RSL
V
1.7
13.2 Supply Current Profile
In this section, Table16 summarizes the supply current (IDD) that characterizes this memory component. This parameter is shown under
different operating conditions.
Table 16 : Supply Current Profile
Symbol
Power State and Steady State
Transaction Rates
Maximum
@tCYCLE= 2.00 ns
x16
x8
x4
x2
Maximum
@tCYCLE= 2.50 ns
x16
x8
x4
Maximum
@tCYCLE= 3.33 ns
x2
x16
x8
x4
Units
x2
IDD,PDN
Device in PDN, self-refresh enabled. a
25
25
25
mA
IDD,STBY
Device in STBY. This is for a device in STBY
with no packets on the Channela
330
270
220
mA
IDD,ROW
ACT command every tRR,
PRE command every tPP.a
720
600
480
mA
IDD,WR
ACT command every tRR,
PRE command every tPP,
WR command every tCC.a
1260 1100 990
850
740
670 640
mA
IDD,RD
ACT command every tRR,
PRE command every tPP,
RD command every tCC.a,b
1500 1360 1270 1210 1300 1200 1100 1000 1050
980
900 820
mA
ITERM,DRSL,RD
RD command every tCC.c
170
90
40
20
170
90
40
20
170
90
40
20
mA
ITERM,DRSL,WR
tCC.c
100
50
30
15
100
50
30
15
100
50
30
15
mA
WR command every
940 1050 910
830
800
a. IDD current @ VDD,MAX flowing into VDD pins
b.This does not include the IOL,DQ sink current. The device dissipates IOL,DQ•VTERM,DQ in each DQ/DQN pair when driving data.
c. ITERM,DRSL current @ VTERM,DQ,MAX flowing into VTERM pins
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13.3 Timing Characteristics
Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parameters that are speed-bin dependent. Refer to the Timing Parameters section for more information.
The first section of parameters pertains to the timing of the DQ pins when driving read data.
The second section of parameters is concerned with the timing for the serial interface signals when driving register read data.
The third section of parameters is concerned with the time intervals needed by the interface to transition between power states.
Table 17 : Timing Characteristics
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
-0.052
-0.065
-0.080
+0.052
+0.065
+0.080
ns
ns
ns
Figure 60
tQ,DQ
DRSL DQ output delay (variation across 16 Q bits on each DQ
pin) from drive points - output delay
@ 2.50 ns > tCYCLE ≥ 2.00 ns
@ 3.33 ns > tCYCLE ≥ 2.50 ns
@ 3.83 ns ≥ tCYCLE ≥ 3.33 ns
tQOFF,DQ
DRSL DQ output delay offset (a fixed value for all 16 Q bits on
each DQ pin) from drive points - output delay
0.00
+0.20
tCYCLE
Figure 60
tOR,DQ, tOF,DQ
DRSL DQ output - rise and fall times (20%-80%).
0.02
0.04
tCYCLE
Figure 60
tQ,SI
Serial SCK-to-SDO output delay @ CLOAD,MAX = 15 pF
2
15
ns
Figure 62
tP,SI
Serial SDI-to-SDO propagation delay @ CLOAD,MAX = 15 pF
-
15
ns
Figure 62
tOR,SI, tOF,SI
Serial SDO output rise/fall (20%-80%) @ CLOAD,MAX = 15 pF
-
10
ns
Figure 62
Figure 46
Figure 46
tPDN-ENTRY
Time for power state to change after PDN entry
-
16
tCYCLE
tPDN-EXIT
Time for power state to change after PDN exit
0
-
tCYCLE
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13.4 Timing Parameters
Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parameters will
vary as a function of the component’s speed bin. The four sections deal with the timing intervals between packets with, respectively, rowrow commands, row-column commands, column-column commands, and column-row commands.
Table 18 : Timing Parameters
Symbol
Parameter and Other Conditions
tRC
tRC-R, 2tCC = tRCD-R + tCC+ tRDP + tRPa
tRC-W, 2tCC, noERAW = tRCD-W + tCC+ tWRP +tRPa
tRC-W, 2tCC, ERAW = tRCD-W + tCC+ tWRP + tRPa
Min
(A)
Min
(B)
Min
(C)
Units
Figure(s)
16
16
19
23
20
20
24
28
24
24
24
28
tCYCLE
Figure 4 Figure 7
tRC
Row-cycle time: interval between successive ROWAACT or ROWP-REFA or ROWP-REFI activate commands to the same bank.
tRAS
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command
and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
Note that tRAS,MAX is 64 us for all timing bins.
10
13
17
tCYCLE
Figure 4 Figure 7
tRP
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a ROWAACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
6
7
7
tCYCLE
Figure 4 Figure 7
tPP
Precharge-to-precharge time: interval between suctPP
cessive ROWP-PRE or ROWP-REFP precharge comtPP-Db
mands to different banks.
4
1
4
1
4
1
tCYCLE
Figure 4 Figure 7
tRR
Row-to-row time: interval between ROWA-ACT or
ROWP- REFA or ROWP-REFI activate commands to
different banks.
4
4
4
4
4
4
tCYCLE
Figure 4 Figure 7
tRCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD read command to the same bank.
5
7
7
tCYCLE
Figure 4 Figure 7
tRCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-WR or COLWRM write command to the same bank.
1
3
3
tCYCLE
Figure 4 Figure 7
tCAC
Column access delay: interval from COL-RD read command to Q read data
6
7
7
tCYCLE
Figure 10
tCWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write data.
3
3
3
tCYCLE
Figure 9
tCC
Column-to-column time: interval between successive COL-RD commands, or between successive COLWR or COLM-WRM commands.
2
2
2
tCYCLE
Figure 4 Figure 7
tRW-BUB,
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D write data
packet (the end of a data packet is the time interval tCC after its start).
3
3
3
tCYCLE
Figure 13
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read data packet
(the end of a data packet is the time interval tCC after its start).
3
3
3
tCYCLE
Figure 13
t∆RW
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-WRM write command.d
8
9
9
tCYCLE
Figure 12
t∆WR
Write-to-read time: interval between a COL-WR or
t∆WR
COLM-WRM write command and a COL-RD read comt∆WR-De
mand.
9
2
10
2
10
2
tCYCLE
Figure 12
tRDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE precharge command to the same bank.
3
4
4
tCYCLE
Figure 4 Figure 7
tWRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a ROWP-PRE
precharge command to the same bank.
10
12
12
tCYCLE
Figure 4 Figure 7
tDR
Write data-to-read time: interval between the start of D write data and a COL-RD read command to the
same bank.
6
7
7
tCYCLE
Figure 12
tDP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge command to the
same bank.
7
9
9
tCYCLE
Figure 9
tLRRn-LRRn
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command. f
16
20
24
tCYCLE
Table5
tREFx-LRRn
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
16
20
24
tCYCLE
Table5
tLRRn-REFx
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
16
20
24
tCYCLE
Table5
XDRDRAM
tWR-BUB,
XDRDRAM
tRR
tRR-Dc
a. The tRC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon
how many column accesses (each requiring tCC) are performed in each row access (tRC). The table lists the special cases (tRC-R, 2tCC, tRC-W, 2tCC, noERAW, tRC-W, 2tCC,
ERAW) in which two column accesses are performed in each row access. Note that tRC-W, 2tCC, ERAW uses a relaxed value of tRCD-W that is equal to tRCD-R,MIN. All
other parameters are minimum.
b. tPP-D is the tPP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 56.
c. tRR-D is the tRR parameter for activates to different bank sets. See “Simultaneous Activation” on page 55.
d. See “Propagation Delay” on page 32.
e. t∆WR-D is the t∆WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 53. Also, note that the value of
t∆WR-D may not take on the values {3,5,7} within the range{t∆WR-D,MIN, ... t∆WR,MIN-1}. tDWR-D may assume any value ≥ t∆WR,MIN.
f.ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,LOWP-LRR2}, ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI, LOWP-REFP},
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14.0 Receive/Transmit Timing
14.1 Clocking
Figure57 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magnified view of
these pins. This diagram shows only one clock cycle.
CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals - a low voltage represents a logical zero and a high voltage represents a logical one. There are two crossing points in each clock cycle. The primary crossing
point includes the high-voltage-to-low-voltage transition of CFM (indicated with the arrowhead in the diagram). The secondary crossing
point includes the low-voltage-to-high-voltage transition of CFM. All timing events on the RSL signals are referenced to the first set of
edges.
Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram, this is how the clockcycle time (tCYCLE or tCYC, CFM), clock-low time (tL, CFM) and clock-high time (tH, CFM) are measured.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR, CFM) and fall
time (tF, CFM) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, CFM + 0.2*(VIH, CFM - VIL, CFM)
80% = VIL, CFM + 0.8*(VIH, CFM - VIL, CFM)
Figure 57 : Clocking Waveforms
tCYCLE or tCYC,CFM
tL,CFM
logic 1
tH,CFM
CFM
VIH,CFM
80%
CFMN
20%
VIL,CFM
logic 0
tR,CFM
tF,CFM
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14.2 RSL RQ Receive Timing
Figure58 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified view of
the pins and only a few clock cycle (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/
CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition. The RQ11...0 signals are low- true: a high voltage
represents a logical zero and a low voltage represents a logical one. Timing events on the RQ11... 0 pins are measured to and from the
point that the signal reaches the level of the reference voltage VREF, RSL.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR, RQ) and fall
time (tF, RQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, RQ + 0.2*(VIH, RQ - VIL, RQ)
80% = VIL, RQ + 0.8*(VIH, RQ - VIL, RQ)
There are two data receiving windows defined for each RQ11...0 signal. The first of these (labeled “0”) and a set time, tS,RQ, and a hold
time, tH,RQ, measured around the primary CFM/CFMN crossing point. The second (labeled “1”) has a set time (tS, RQ) and a hold time
(tH, RQ) measured around a point 0.5*tCYCLE after the primary CFM/CFMN crossing point.
Figure 58 : RSL RQ Receive Waveforms
tCYCLE
CFM
CFMN
[1/2]•tCYCLE
tH,RQ
tS,RQ
RQ0
tS,RQ
0
logic 0
VIH,RQ
80%
VREF,RSL
1
20%
VIL,RQ
logic1
tF,RQ
...
tR,RQ
tH,RQ
[1/2]•tCYCLE
tH,RQ
tS,RQ
RQ11
0
tR,RQ
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tS,RQ
tH,RQ
1
tF,RQ
logic 0
VIH,RQ
80%
VREF,RSL
20%
VIL,RQ
logic 1
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14.3 DRSL DQ Receive Timing
Figure59 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents
a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured
to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low -voltage transition. The DQ15...0/
DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also differential - timing events on the DQ15...0/DQN15... 0 pins are measured to and from the point that each differential pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tIR, DQ) and
fall time (tIF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VIL, DQ + 0.2*(VIH, DQ - VIL, DQ)
80% = VIL, DQ + 0.8*(VIH, DQ - VIL, DQ)
There are 16 data receiving windows defined for each DQ15...0/DQN15... 0 pin pair. The receiving windows for a particular DQi/DQNi
pin pair is referenced to an offset parameter tDOFF,DQi (the index “i” may take on the values {0, 1, .. , 15} and refers to each of the DQ15...
0/DQN15... 0 pin pairs).
The tDOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin
pair. The 16 receiving windows are placed at times tDOFF,DQi + (j/8)*tCYCLE (the index “j” may take on the values {0, 1, .. , 15} and refers
to each of the receiving windows for the DQi/DQNi pin pair).
The offset values tDOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range
{tDOFF,MIN, tDOFF,MAX}. Furthermore, each offset value tDOFF,DQi is static and will not change during system operation. Its value can be
determined at initialization.
The 16 receiving windows (j = 0 ... 15) for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window has a set time (tS, DQ) and
a hold time (tH, DQ) measured around a point tDOFF,DQ0 + (j/8) *tCYCLE after the primary CFM/CFMN crossing point.
The 16 receiving windows (j = 0 ... 15) for the each of the other pairs DQi/DQNi are also labeled “0” through “15”. Each window has a set
time (tS, DQ) and a hold time (tH, DQ) measured around a point tDOFF,DQi + (j/8)*tCYCLE after the primary CFM/CFMN crossing point.
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Figure 59 : DRSL DQ Receive Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,3,4,5,...15}
tDOFF,MAX
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tDOFF,MIN
[(j)/8]•tCYCLE
tDOFF,DQ0
tS,DQ
logic 1
VIH,DQ
80%
tH,DQ
DQ0
0
1
2
3
4
5
...
6
...
j
14
15
20%
VIL,DQ
logic 0
DQN0
tIF,DQ
...
tIR,DQ
[(j)/8]•tCYCLE
tDOFF,DQi
logic 1
VIH,DQ
80%
tH,DQ
tS,DQ
DQi
0
1
2
3
4
5
...
6
...
j
14
15
20%
VIL,DQ
logic 0
DQNi
...
tIR,DQ
tIF,DQ
[(j)/8]•tCYCLE
tDOFF,DQ15
logic 1
VIH,DQ
80%
tH,DQ
tS,DQ
DQ15
0
1
2
3
4
5
6
DQN15
tIR,DQ
tIF,DQ
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...
j
...
14
15
20%
VIL,DQ
logic 0
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14.4 DRSL DQ Transmit Timing
Figure60 shows a timing diagram for transmitting read data on the DQ15...0/DQN15...0 data pins of the memory component. This
diagram represents a magnified view of these pins and only a few clock cycles are shown (CFM and CFMN are the clock signals).
Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low-voltage
transition. The DQ15...0/DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical
one. They are also differential - timing events on the DQ15...0/DQN15...0 pins are measured to and from the point that each differential
pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tOR, DQ) and fall
time (tOF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = VOL, DQ + 0.2*(VOH, DQ - VOL, DQ)
80% = VOL, DQ + 0.8*(VOH, DQ - VOL, DQ)
There are 16 data transmit windows defined for each DQ15...0/DQN15...0 pin pair. The transmitting windows for a particular DQi/DQNi
pin pair is referenced to an offset parameter tQOFF,DQi (the index “i” may take on the values {0, 1, .., 15} and refers to each of the DQ15...
0/DQN15...0 pin pairs).
The tQOFF,DQi + tQ,DQ,MAX expression determines the time between the primary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair.
The offset values tQOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range
{tQOFF,MIN, tQOFF,MAX}. Furthermore, each offset value tQOFF,DQi is static; its value will not change during system operation. Its value can
be determined at initialization time.
The 16 transmit windwos (j = 0 ... 15} for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window begins at the time
(tQOFF,DQ0 + tQ,DQ,MAX +((j+0.5)/8)*tCYCLE) and ends at the time (tQOFF,DQ0 + tQ,DQ,MIN +((j+1.5)/8)*tCYCLE) measured after the primary
CFM/CFMN crossing point.
The 16 transmit windwos (j = 0 ... 15} for the other pair DQi/DQNi are also labeled “0” through “15”. Each window begins at the time
(tQOFF,DQi + tQ,DQ,MAX +((j+0.5)/8)*tCYCLE) and ends at the time (tQOFF,DQi + tQ,DQ,MIN +((j+1.5)/8)*tCYCLE) measured after the primary
CFM/CFMN crossing point.
Note that when no read data is to be transmitted on the DQ/DQN pins(and no other component is transmitting on the external DQ/DQN
wires), then the voltage level on the DQ/DQN pins will follow the voltage reference value VTERM,DRSL on the VTERM pin. The logical
value of each DQ/DQN pin pair in this no-drive state will be “1/1”; when read data is driven, each DQ/DQN pin pair will have either the
logical value of “1/0” or “0/1”.
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Figure 60 : RSL DQ Transmit Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,3,4,5,...15}
tQOFF,MAX
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tQOFF,MIN
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
DQ0
tQOFF,DQ0
0
1
2
3
4
6
7
...
8
...
j
14
15
20%
VOL,DQ
logic “0”
DQN0
tOR,DQ
tOF,DQ
...
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
DQi
1
2
3
4
5
6
...
7
...
j
14
15
20%
VOL,DQ
logic “0”
DQni
tOR,DQ
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
tQOFF,DQi
0
tOF,DQ
...
[(j+0.5)/8]•tCYCLE
[(j-0.5)/8]•tCYCLE
DQ15
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
tQOFF,DQ15
0
1
2
3
4
5
6
DQN15
tOR,DQ
tOF,DQ
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7
...
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
j
...
14
15
20%
VOL,DQ
logic “0”
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14.5 Serial Interface Receive Timing
Figure61shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the
pins only a few clock cycles.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one.
Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is necessary to
constrain the slew rate of the signals. The rise time (tR,SCK and tRI,SI) and fall time (tF,SCK and tIF,SI) of the signals are measured from the
20% and 80% points of the full-swing levels.
20% = VIL,SI + 0.2 *(VIH,SI - VIL,SI)
50% = VIL,SI + 0.5 *(VIH,SI - VIL,SI)
80% = VIL,SI + 0.8 *(VIH,SI - VIL,SI)
There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has a set time (tS, RQ) and
a hold time (tH, RQ) measured around the falling edge of the SCK clock signal.
Figure 61 : Serial Interface Receive Waveforms
tCYC,SCK
logic 0
VIH,SI
tH,SCK
tL,SCK
80%
SCK
VREF,RSL
20%
VIL,SI
tF,SCK
logic 1
tR,SCK
tS,SI
tH,SI
logic 0
VIH,SI
80%
RST
CMD
SDI
VREF,RSL
20%
VIL,SI
tIR,SI
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tIF,SI
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14.6 Serial Interface Transmit Timing
Figure62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the
pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one.
Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is necessary to
constrain the slew rate of the signals. The rise time (tOR,SI) and fall time (tOF,SI) of the signals are measured from the 20% and 80%
points of the full-swing levels.
20% = VOL,SI + 0.2*(VOH,SI - VOL,SI)
50% = VOL,SI + 0.5*(VOH,SI - VOL,SI)
80% = VOL,SI + 0.8*(VOH,SI - VOL,SI)
There is one transmit window defined for the serial interface data signal (SDO pins). This window has a maximum delay time (tQ, SI,MAX)
from the falling edge of the SCK clock signal and a minimum delay time (tQ,SI,MIN) from the next falling edge of the SCK clock signal.
When the memory component is not selected during a serial device read transaction, it will simply pass the information on the SDI input
to the SDO output. This combinational propagation delay parameter is tP,SI. The tCYC,SCK will need to be increased during a serial read
transaction (relative to the tCYC,SCK value for a serial write transaction) because of the accumulated propagation delay through all of the
XDR DRAM devices on the serial interface.
During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the tCYC,SCK value can be set to
the same value as for serial write transactions. See “Initialization” on page 47.
Figure 62 : Serial Interface Transmit Waveforms
tCYC,SCK
logic 0
tH,SCK
tL,SCK
VIH,SI
80%
SCK
VREF,RSL
20%
tF,SCK
VIL,SI
logic 1
tR,SCK
tQ,SI,MAX
tQ,SI,MIN
logic 0
VOH,SI
80%
tP,SI
VREF,RSL
SDO
20%
VOL,SI
tOR,SI
tOF,SI
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
logic 1
logic 0
VIH,SI
80%
SDI
VREF,RSL
20%
VIL,SI
logic 1
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15.0 Package Description
15.1 Package Parasitic Summary
Table19 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory component. Most
of the parameters have maximum values only, however some have both maximum and minimum values.
The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance values.
The second group of parameters are for the RQ request pins. They include inductance, mutual inductance, capacitance, and resistance
values. There are also limits on the spread in inductance and capacitance values allowed in any one memory component.
The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance, capacitance, and resistance
values. There are limits on the spread in inductance and capacitance values allowed in any one memory component.
The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values.
Table 19 : Package RSL Parasitic Summary
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
LVTERM
VTERM pin - effective input inductance per four bits
-
2.2
nH
LI ,CFM
CFM/CFMN pins - effective input capacianceb
-
5.0
nH
CI ,CFM
CFM/CFMN pins - effective input capacianceb
1.8
2.4
pF
RI ,CFM
CFM/CFMN pins - effective input resistance
4
18
Ω
-
5.0
nH
RSL RQ pins - effective input
inductanceb
CI ,RQ
RSL RQ pins - effective input
capacitanceb
1.8
2.4
pF
RI ,RQ
RSL RQ pins - effective input resistance
4
18
Ω
L12,RQ
Mutual inductance between adjacent RSL RQ signals
-
0.6
nH
∆LI,RQ
Difference in LI,RQ between any RSL RQ pins of a single device
-
1.8
nH
∆CI,RQ
Difference in CI between CFM/CFMN average and RSL RQ pins of
single device
-0.12
+0.12
pF
ZPKG,DQ
DRSL DQ pins - package differential impednce
note - package trace length should be less than 10mm long.
70
130
Ω
CI ,DQ
DRSL DQ pins - effective input capacitancea
-
1.8
pF
-
0.06
pF
LI ,RQ
∆CI,DQ
Difference in CI between DQi and DQNi of each DRSL
RI ,DQ
DRSL DQ pins - effective input resistance
4
25
Ω
LI ,SI
Serial Interface effective input inductance
-
8.0
nH
CI ,SI
Serial Interface effective input capacitance
RST, SCK, CMD
SDI,SDO
1.7
-
3.0
7.0
pF
pF
paira
a. This is the effective die input capacitance, and does not include package capacitance.
b. CFM/RQ/SI should include package capacitance/Impedance, only DQ deos not include pacage capacitance. This value is a combination of the device I/O circuitry and package capacitance&inductance
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Figure 63 : Equivalent Circuits for Package Parasitic
Pad
RQ Pin
CI,RQ
LI,RQ
L12,RQ
RQ Pin
L12,RQ
RQ Pin
RI,RQ
GND Pin
Pad
Pad
CI,DQ
CI,DQ
RI,DQ
RI,DQ
ZPKG,DQ/2
DQ Pin
ZPKG,DQ/2
DQN Pin
GND Pin
Pad
Pad
CI,CFM
CI,CFM
RI,CFM
RI,CFM
ZPKG,CFM/2
CFM Pin
ZPKG,CFM/2
CFMN Pin
GND Pin
Pad
LI,SI
SCK,CMD,RST Pin
SDI,SDO Pin
CI,SI
GND Pin
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15.2 Package Dimensions (104-Ball FBGA)
(Unit : mm)
14.00 ± 0.10
A
12.00
0.80
MOLDING AREA
#A1 INDEX MARK
2.00
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
B
1
A
B
(Datum B)
C
1.27
F
G
1.27
H
12.70
E
14.50 ± 0.10
D
J
K
L
104- ∅0.45 Solder ball
( Post reflow 0.50 + 0.05 )
0.10 MAX
A B
14.00 ± 0.10
#A1
14.50 ± 0.10
0.2 M
(Datum A)
0.35 ± 0.05
1.03 ± 0.10
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Table of Contents
0.0 Overview ............................................................................................................................................................................................. 3
1.0 Features .............................................................................................................................................................................................. 3
2.0 Key Timing Parameters/Part Numbers ............................................................................................................................................. 4
3.0 General Description ........................................................................................................................................................................... 5
4.0 Pinouts and Definitions ..................................................................................................................................................................... 6
5.0 Pin Description ................................................................................................................................................................................. 10
6.0 Block Diagram .................................................................................................................................................................................. 11
7.0 Request Packets .............................................................................................................................................................................. 13
7.1 Request Packet Formats .............................................................................................................................................................. 13
7.2 Request Field Encoding ............................................................................................................................................................... 15
7.3 Request Packet Interactions ........................................................................................................................................................ 17
7.4 Request Interactions Cases ......................................................................................................................................................... 18
7.5 Dynamic Request Scheduling ...................................................................................................................................................... 23
8.0 Memory Operations ......................................................................................................................................................................... 25
8.1 Write Transactions ....................................................................................................................................................................... 25
8.2 Read Transactions ....................................................................................................................................................................... 27
8.3 Interleaved Transactions .............................................................................................................................................................. 29
8.4 Read/Write Interaction ................................................................................................................................................................. 31
8.5 Propagation Delay ........................................................................................................................................................................ 32
9.0 Register Operations ......................................................................................................................................................................... 34
9.1 Serial Transactions ...................................................................................................................................................................... 34
9.2 Serial Write Transactions ............................................................................................................................................................. 34
9.3 Serial Read Transactions ............................................................................................................................................................. 34
9.4 Register Summary ....................................................................................................................................................................... 36
10.0 Maintenance Operations ............................................................................................................................................................... 42
10.1 Refresh Transactions ................................................................................................................................................................ 42
10.2 Interleaved Refresh Transaction ............................................................................................................................................... 42
10.3 Calibration Transactions ........................................................................................................................................................... 44
10.4 Power State Management ......................................................................................................................................................... 45
10.5 Initialization ............................................................................................................................................................................... 47
10.6 XDR DRAM Initialization Overview ........................................................................................................................................... 48
10.7 XDR DRAM Pattern Load with WDSL Register ........................................................................................................................ 48
10.8 Sub-Row (Sub-Page) Sensing .................................................................................................................................................. 50
11.0 Special Feature Description .......................................................................................................................................................... 51
11.1 Write Masking ........................................................................................................................................................................... 51
11.2 Multiple Bank sets and the ERAW Feature ............................................................................................................................... 53
11.3 Simultaneous Activation ............................................................................................................................................................ 55
11.4 Simultaneous Precharge ........................................................................................................................................................... 56
12.0 Operating Conditions .................................................................................................................................................................... 57
12.1 Electrical Conditions .................................................................................................................................................................. 57
12.2 Timing Conditions ..................................................................................................................................................................... 58
13.0 Operating Characteristics ............................................................................................................................................................. 59
13.1 Electrical Characteristics ........................................................................................................................................................... 59
13.2 Supply Current Profile ............................................................................................................................................................... 59
13.3 Timing Characteristics ............................................................................................................................................................... 60
13.4 Timing Parameters .................................................................................................................................................................... 61
14.0 Receive/Transmit Timing ............................................................................................................................................................... 62
14.1 Clocking .................................................................................................................................................................................... 62
14.2 RSL RQ Receive Timing ........................................................................................................................................................... 63
14.3 DRSL DQ Receive Timing ........................................................................................................................................................ 64
14.4 DRSL DQ Transmit Timing ....................................................................................................................................................... 66
14.5 Serial Interface Receive Timing ................................................................................................................................................ 68
14.6 Serial Interface Transmit Timing ............................................................................................................................................... 69
15.0 Package Description ...................................................................................................................................................................... 70
15.1 Package Parasitic Summary ..................................................................................................................................................... 70
15.2 Package Dimensions (104-Ball FBGA) ..................................................................................................................................... 72
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List of Tables
Table 1-1. x16 Package Pinout(Top View) : 104ball FBGA Package .................................................................................................... 6
Table 1-2. x8 Package Pinout(Top View) : 104ball FBGA Package .................................................................................................... 7
Table 1-3. x4 Package Pinout(Top View) : 104ball FBGA Package .................................................................................................... 8
Table 1-4. x2 Package Pinout(Top View) : 104ball FBGA Package .................................................................................................... 9
Table 2. Pin Description ......................................................................................................................................................................... 10
Table 3. Request Field Description ....................................................................................................................................................... 13
Table 4. OP Field Encoding Summary .................................................................................................................................................. 15
Table 5. ROP Field Encoding Summary................................................................................................................................................ 15
Table 6. POP Field Encoding Summary ................................................................................................................................................ 16
Table 7. XOP Field Encoding Summary. ............................................................................................................................................... 16
Table 8. Packet Interaction Summary ................................................................................................................................................... 17
Table 9. SCMD Field Encoding Summary ............................................................................................................................................. 34
Table 10. Initialization Timing Parameters............................................................................................................................................ 48
Table 11. XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4/x2 XDR DRAM, BL=16).......................................... 49
Table 12. Core Data Word-to-WDSL Format ......................................................................................................................................... 49
Table 13. Electrical Conditions .............................................................................................................................................................. 57
Table 14. Timing Conditions .................................................................................................................................................................. 58
Table 15. Electrical Characteristics....................................................................................................................................................... 59
Table 16. Supply Current Profile............................................................................................................................................................ 59
Table 17. Timing Characteristics ........................................................................................................................................................... 60
Table 18. Timing Parameters ................................................................................................................................................................. 61
Table 19. Package RSL Parasitic Summary.......................................................................................................................................... 70
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List of Figures
1. XDR DRAM Device Write and Read Transactions............. 5
2. 512Mb (8x4Mx16)XDR DRAM Block Diagram .................. 12
3. Request Packet Formats ................................................... 14
4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions........... 19
5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions............. 20
6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions ............ 21
7. ACT-, RD-, WR-, PRE-to-PRE Packet Interactions........... 22
8. Request Scheduling Examples......................................... 23
9. Write Transactions............................................................. 26
10. Read Transactions ........................................................... 28
11. Interleaved Transactions ................................................. 30
12. Write/Read Interaction ..................................................... 31
13. Propagation Delay............................................................ 33
14. Serial Write Transaction .................................................. 35
15. Serial Read Transaction-Selected DRAM ...................... 35
16. Serial Read Transaction-Non-Selected DRAM .............. 35
17. Serial Identification(SID) Register .................................. 36
18. Configuration (CFG) Register ......................................... 37
19. Power Management(PM) Register .................................. 37
20. Write Data Serial Load(WDSL) Control Register ........... 37
21. RQ Scan High(RQH) Register ......................................... 37
22. RQ Scan Low(RQL) Register........................................... 38
23. Refresh Bank (REFB) Control Register.......................... 38
24. Refresh High (REFH) Row Register................................ 38
25. Refresh Middle(REFM) Row Register............................. 38
26. Refresh Low (REFL) Row Register................................. 39
27. IO Configuration (IOCFG) Register................................. 39
28. Current Calibration 0 (CC0) Register ............................. 39
29. Current Calibration 1 (CC1) Register ............................. 39
30. Impedance Calibration 0 (ZC0) Register ........................ 39
31. Impedance Calibration 1 (ZC1) Register ........................ 39
32. Current Fuse Setting 0 (FZC0) Register......................... 40
33. Current Fuse Setting 1 (FZC1) Register......................... 40
34. Read Only Memory 0 (ROM0) Register ......................... .40
35. Read Only Memory 1 (ROM1) Register .......................... 40
36. Test Register .................................................................... 40
37. DLL Register..................................................................... 40
38. PLL0 Register ................................................................... 41
39. PLL1 Register ................................................................... 41
40. IFT Register ...................................................................... 41
41. DA Register....................................................................... 41
42. Delay(DLY) Control Register........................................... 41
43. Partner-Definable (PART0-PARTF) Registers ............... 41
44. Refresh Transactions ...................................................... 43
45. Calibration Transactions ................................................. 44
46. Power State Management................................................ 46
47. Serial Interface Systems Topology ................................ 47
48. Initialization Timing for XDR DRAM [k] Device ............. 47
49. Sub-Row Example............................................................ 50
50. Byte Mask Logic............................................................... 51
51. Wirte-Masked (WRM) Transaction Example ...................... 52
52. Wirte/Read Interaction-No ERAW Feature ......................... 53
53. Write/Read Interaction-ERAW Feature............................... 53
54. XDR DRAM Block Diagram with Bank Sets ....................... 54
55. Simultaneous Activation-tRR-D Cased .............................. 55
56. Simultaneous Precharge-tPP-D Cases .............................. 56
57. Clocking Waveforms............................................................ 62
58. RSL RQ Receive Waveforms............................................... 63
59. DRSL DQ Receive Waveforms ........................................... .65
60. RSL DQ Transimit Waveforms ............................................ 67
61. Serial Interface Receive Waveforms .................................. 68
62. Serial Interface Transmit Waveforms................................. 69
63. Equivalent Circuits for Package Parasitic ......................... 71
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Copyright © Dec. 2005, Samsung Electronics.
All rights reserved.
Rambus and Rambus logo are trademarks or registered trademarks of Rambus Inc.
XDR is a trademark of Rambus Inc. in the United States and other countries.
This document contains advanced information that is subject to change by Samsung Electronics without notice
Document Version 1.0ver.
Samsung Electronics Co. Ltd.
San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, KOREA
Telephone: 82-31-208-6366
Fax: 82-31-208-6799
http://www.intl.samsungsemi.com
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