HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
1Gb DDR2 SDRAM
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
HY5PS1G431CFR
HY5PS1G831CFR
HY5PS1G1631CFR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Nov. 2008
1
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Revision Details
Rev.
History
Draft Date
0.1
Initial data sheet released
Nov. 2006
0.2
IDD Values added
Dec. 2006
0.3
Inserted Pin Description & Corrected typos
Mar. 2007
0.4
Adjusted IDD values & Corrected typos
May. 2007
0.5
Adjusted IDD values
Jun. 2007
0.6
Updated IDD values and Halogen-free added
Jul. 2008
0.7
Editorial change on TOPER
Nov. 2008
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Operating Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions(SSTL_1.8)
3.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC Output Parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
•
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VDD = 1.8 +/- 0.1V
VDDQ = 1.8 +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
8 banks
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 60ball FBGA(x4/x8), 84ball FBGA(x16)
Full strength driver option controlled by EMR
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
1.1.2 Ordering Information
Part No.
Configuration
Package
HY5PS1G431C(L)FP-XX*
256Mx4
HY5PS1G431CFR-XX*
60 Ball
HY5PS1G831C(L)FP-XX*
128Mx8
HY5PS1G831CFR-XX*
HY5PS1G1631C(L)FP-XX*
84 Ball
64Mx16
HY5PS1G1631CFR-XX*
Note:
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
Hynix lead-free products are compliant to RoHS.
1.1.3 Operating Frequency
Grade
tCK(ns)
CL
tRCD
tRP
Unit
E3
5
3
3
3
Clk
C4
3.75
4
4
4
Clk
Y5
3
5
5
5
Clk
S6
2.5
6
6
6
Clk
S5
2.5
5
5
5
Clk
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
1.2 Pin Configuration & Address Table
256Mx4 DDR2 Pin Configuration(Top view: see balls through package)
7
8
9
A
VSSQ
DQS
VDDQ
DM
B
DQS
VSSQ
NC
DQ1
VDDQ
C
VDDQ
DQ0
VDDQ
NC
VSSQ
DQ3
D
DQ2
VSSQ
NC
VDDL
VREF
VSS
E
VSSDL
CK
VDD
CKE
WE
F
RAS
CK
ODT
BA0
BA1
G
CAS
CS
A10
A1
H
A2
A0
A3
A5
J
A6
A4
A7
A9
K
A11
A8
A12
NC
L
NC
A13
1
2
3
VDD
NC
VSS
NC
VSSQ
VDDQ
BA2
VSS
VDD
VDD
VSS
ROW AND COLUMN ADDRESS TABLE
Rev. 0.7 / Nov. 2008
ITEMS
256Mx4
# of Bank
8
Bank Address
BA0,BA1,BA2
Auto Precharge Flag
A10/AP
Row Address
A0 - A13
Column Address
A0-A9, A11
Page size
1 KB
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
128Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
9
A
VSSQ
DQS
VDDQ
DM/RDQS
B
DQS
VSSQ
DQ7
DQ1
VDDQ
C
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
D
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
E
VSSDL
CK
VDD
CKE
WE
F
RAS
CK
ODT
BA0
BA1
G
CAS
CS
A10
A1
H
A2
A0
A3
A5
J
A6
A4
A7
A9
K
A11
A8
A12
NC
L
NC
A13
1
2
3
VDD
NU/RDQS
VSS
DQ6
VSSQ
VDDQ
BA2
VSS
VDD
VDD
VSS
ROW AND COLUMN ADDRESS TABLE
Rev. 0.7 / Nov. 2008
ITEMS
128Mx8
# of Bank
8
Bank Address
BA0, BA1, BA2
Auto Precharge Flag
A10/AP
Row Address
A0 - A13
Column Address
A0-A9
Page size
1 KB
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
7
8
9
A
VSSQ
UDQS
VDDQ
UDM
B
UDQS
VSSQ
DQ15
DQ9
VDDQ
C
VDDQ
DQ8
VDDQ
DQ12
VSSQ
DQ11
D
DQ10
VSSQ
DQ13
VDD
NC
VSS
E
VSSQ
LDQS
VDDQ
DQ6
VSSQ
LDM
F
LDQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
G
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
H
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
J
VSSDL
CK
VDD
CKE
WE
K
RAS
CK
ODT
BA0
BA1
L
CAS
CS
A10/AP
A1
M
A2
A0
A3
A5
N
A6
A4
A7
A9
P
A11
A8
A12
NC, A14
R
NC, A15
NC, A13
1
2
3
VDD
NC
VSS
DQ14
VSSQ
VDDQ
NC, BA2
VSS
VDD
VDD
VSS
ROW AND COLUMN ADDRESS TABLE
Rev. 0.7 / Nov. 2008
ITEMS
64Mx16
# of Bank
8
Bank Address
BA0, BA1, BA2
Auto Precharge Flag
A10/AP
Row Address
A0 - A12
Column Address
A0-A9
Page size
2 KB
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh
entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout
READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
ODT
Input
On Die Termination Control: ODT (registered HIGH) enables on die termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS,
RDQS, and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ,
UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended
Mode Register(EMR(1)) is programmed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(LDM, UDM)
Input
Input Data Mask: DM is an input mask signal for write data. Input Data is masked when DM is
sampled High coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMR command to EMR(1).
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE
command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if one of the mode register or extended mode register is to be accessed during a MR or
EMR command cycle.
A0 -A15
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge command to determine whether
the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to
be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code
during MRS or EMRS commands.
DQ
Input/Output
Data input / output: Bi-directional data bus
Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds
to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in
single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS
to provide differential pair signaling to the system during both reads and writes. An EMR(1) control bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/Output
Rev. 0.7 / Nov. 2008
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMR(1)
x4 DQS/DQS
x8 DQS/DQS
if EMR(1)[A11] = 0
x8 DQS/DQS, RDQS/RDQS,
if EMR(1)[A11] = 1
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of
EMR(1)
x4 DQS
x8 DQS
if EMR(1)[A11] = 0
x8 DQS, RDQS,
if EMR(1)[A11] = 1
x16 LDQS and UDQS
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
-ContinuedPIN
TYPE
DESCRIPTION
No Connect: No internal electrical connection is present.
NC
VDDQ
Supply
DQ Power Supply: 1.8V +/- 0.1V
VSSQ
Supply
DQ Ground
VDDL
Supply
DLL Power Supply: 1.8V +/- 0.1V
VSSDL
Supply
DLL Ground
VDD
Supply
Power Supply: 1.8V +/- 0.1V
VSS
Supply
Ground
VREF
Supply
Reference voltage.
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 1.0 V ~ 2.3 V
V
1
VDDQ
Voltage on VDDQ pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
VDDL
Voltage on VDDL pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
Voltage on any pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
-55 to +100
°C
1, 2
VDD
VIN, VOUT
TSTG
Parameter
Storage Temperature
II
Input leakage current; any input 0V VIN VDD;
all other balls not under test = 0V)
-2 uA ~ 2 uA
uA
IOZ
Output leakage current; 0V VOUT VDDQ; DQ
and ODT disabled
-5 uA ~ 5 uA
uA
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions. please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1,2
Note:
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
2. At 85~95° TOPER , Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this temperature range it must be required an EMRS command to change itself refresh rate.
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Symbol
Rating
Parameter
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
1.7
1.8
1.9
V
1
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
1,2
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1,2
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
3,4
VTT
Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
5
Note:
1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION
SYMBOL
MIN
NOM
MAX
UNITS NOTES
Rtt effective impedance value for EMR(A6,A2)=0,1; 75 ohm
Rtt1(eff)
60
75
90
ohm
1
Rtt effective impedance value for EMR(A6,A2)=1,0; 150 ohm
Rtt2(eff)
120
150
180
ohm
1
Rtt effective impedance value for EMR(A6,A2)=1,1; 50 ohm
Rtt3(eff)
40
50
60
ohm
1
Deviation of VM with respect to VDDQ/2
delta VM
-6
+6
%
1
Note:
1. Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac))
and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
Rtt(eff) =
VIH (ac) - VIL (ac)
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM: Measurement Voltage at test pin (mid point) with no load.
2 x Vm
delta VM =(
Rev. 0.7 / Nov. 2008
VDDQ
- 1) x 100%
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(dc)
dc input logic HIGH
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic LOW
- 0.3
VREF - 0.125
V
Notes
3.2.2 Input AC Logic Level
Symbol
DDR2 400,533
Parameter
Min.
VIH (ac)
ac input logic HIGH VREF + 0.250
VIL (ac)
ac input logic LOW
-
DDR2 667,800
Units
Max.
Min.
Max.
-
VREF + 0.200
-
V
VREF - 0.250
-
VREF - 0.200
V
Notes
3.2.3 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
V
1
VSWING(MAX)
Input signal maximum peak to peak swing
0.5 * VDDQ
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the figure below.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VSWING(MAX)
VIL(dc) max
delta TF
Falling Slew = VREF - VIL(ac) max
delta TF
delta TR
VIL(ac) max
VSS
Rising Slew = VIH(ac) min - VREF
delta TR
< Figure: AC Input Test Signal Waveform>
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3.2.4 Differential Input AC logic Level
Symbol
Parameter
VID (ac)
ac differential input voltage
VIX (ac)
ac differential cross point voltage
Min.
Max.
Units Notes
0.5
VDDQ + 0.6
V
1
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS)
level.
The minimum value is equal to VIH(DC) - V IL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is
expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
3.2.5 Differential AC output parameters
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
Max.
Units
Notes
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is
expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must
cross.
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3.3 Output Buffer Characteristics
3.3.1 Output AC Test Conditions
Symbol
VOTR
Parameter
Output Timing Measurement Reference Level
SSTL_18 Class II
Units
Notes
0.5 * VDDQ
V
1
SSTl_18
Units
Notes
- 13.4
mA
1, 3, 4
13.4
mA
2, 3, 4
Note:
1. The VDDQ of the device under test is referenced.
3.3.2 Output DC Current Drive
Symbol
Parameter
IOH(dc)
Output Minimum Source DC Current
IOL(dc)
Output Minimum Sink DC Current
Note:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ
and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test
device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are
delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating
point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3.3.3 OCD default characteristics
Description
Parameter
Min
Output impedance
-
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Sout
Nom
Unit
Notes
-
ohms
1
0
1.5
ohms
6
0
4
ohms
1,2,3
5
V/ns
1,4,5,6,7,8
1.5
-
Max
-
Note :
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUTVDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be
less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process
corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved
if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Output
(Vout)
Reference
point
7. DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
Rev. 0.7 / Nov. 2008
16
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
3.4 IDD Specifications & Test Conditions
IDD Specifications(max)
DDR2
400
Symbol
DDR2 533
DDR2 667
DDR2 800
Units
x4/x8
x4/x8
x16
x4/x8
x16
x4/x8
x16
IDD0
60
65
85
70
90
75
95
mA
IDD1
70
75
110
80
115
85
120
mA
IDD2P
10
10
10
10
10
10
10
mA
IDD2Q
22
27
27
30
30
32
32
mA
IDD2N
30
35
35
40
40
45
45
mA
F
20
20
20
25
25
25
25
mA
S
12
12
12
12
12
12
12
mA
IDD3N
35
45
45
50
50
55
55
mA
IDD4W
100
125
160
155
210
180
240
mA
IDD4R
100
125
160
150
195
170
225
mA
IDD5
165
165
165
175
175
180
175
mA
Normal
10
10
10
10
10
10
10
mA
Low
power
5
5
5
5
5
5
5
mA
165
175
260
200
265
235
295
mA
IDD3P
IDD6
IDD7
Rev. 0.7 / Nov. 2008
17
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS
min(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
= 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS
is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
mA
IDD2P
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MR(12) = 0
mA
Slow PDN Exit MR(12) = 1
mA
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
=tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),
tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
mA
Rev. 0.7 / Nov. 2008
18
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Note :
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed
grade)
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMR bits 10 and 11.
6. For DDR2-667/800 testing, tCK in the COnditions should be interpreted as tCK (avg).
7. Definitions for IDD
LOW is defined as Vin ≤ VILAC (max)
HIGH is defined as Vin ≥ VIHAC (min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Rev. 0.7 / Nov. 2008
19
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
IDD Testing Parameters
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2667
DDR2533
DDR2400
Parameter
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Units
CL(IDD)
5
6
5
4
3
tCK
tRCD(IDD)
12.5
15
15
15
15
ns
tRC(IDD)
57.5
60
60
60
55
ns
tRRD(IDD)-x4/x8
7.5
7.5
7.5
7.5
7.5
ns
tRRD(IDD)-x16
10
10
10
10
10
ns
tCK(IDD)
2.5
2.5
3
3.75
5
ns
tRASmin(IDD)
45
45
45
45
40
ns
tRASmax(IDD)
70000
70000
70000
70000
70000
ns
tRP(IDD)
12.5
15
15
15
15
ns
tRFC(IDD)-256Mb
75
75
75
75
75
ns
tRFC(IDD)-512Mb
105
105
105
105
105
ns
tRFC(IDD)-1Gb
127.5
127.5
127.5
127.5
127.5
ns
tRFC(IDD)-2Gb
197.5
197.5
197.5
197.5
197.5
ns
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW (IDD) using a burst length
of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D
-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3
-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3
-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3
-DDR2-800 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DDDDD
DDDD
DDD
Timing Patterns for 8 bank devices x4/8
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Rev. 0.7 / Nov. 2008
20
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
DDD
-DDR2-800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
DDDD
3.5. Input/Output Capacitance
Parameter
Symbol
DDR2 400
DDR2 533
DDR2 667
DDR2 800
Units
Min
Max
Min
Max
Min
Max
Input capacitance, CK and CK
CCK
1.0
2.0
1.0
2.0
1.0
2.0
pF
Input capacitance delta, CK and CK
CDCK
x
0.25
x
0.25
x
0.25
pF
Input capacitance, all other input-only pins
CI
1.0
2.0
1.0
2.0
1.0
1.75
pF
Input capacitance delta, all other input-only pins
CDI
x
0.25
x
0.25
x
0.25
pF
Input/output capacitance, DQ, DM, DQS, DQS
CIO
2.5
4.0
2.5
3.5
2.5
3.5
pF
Input/output capacitance delta, DQ, DM, DQS, DQS
CDIO
x
0.5
x
0.5
x
0.5
pF
Rev. 0.7 / Nov. 2008
21
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
4. Electrical Characteristics & AC Timing Specification
(TOPER; VDDQ = 1.8 +/- 0.1V; VDD = 1.8 +/- 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
Refresh to Active/Refresh
command time
tRFC
Average periodic
refresh interval
tREFI
256Mb 512Mb 1Gb
2Gb
4Gb
Units Notes
75
105
127.5
195
327.5
ns
1
0 ℃≤ TCASE ≤ 85℃
7.8
7.8
7.8
7.8
7.8
us
1
85℃＜ TCASE ≤ 95℃
3.9
3.9
3.9
3.9
3.9
us
1,2
Note:
1: If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be
executed.
2. This is an optional feature. For detailed information, please refer to “operating temperature condition” in this data sheet.
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units Notes
Parameter
min
min
min
min
min
min
Bin(CL-tRCD-tRP)
5-5-5
6-6-6
4-4-4
5-5-5
4-4-4
3-3-3
CAS Latency
5
6
4
5
4
3
tCK
tRCD
12.5
15
12
15
15
15
ns
2
12.5
15
12
15
15
15
ns
2
tRAS
45
45
45
45
45
40
ns
2,3
tRC
57.5
60
57
60
60
55
ns
2
tRP
*1
Note:
1. 8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+1*tCK, where tRP
are the values for a single bank Precharge, which are shown in the table above.
2. Refer to Specific Notes 32.
3. Refer to Specific Notes 3.
Rev. 0.7 / Nov. 2008
22
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
Parameter
DDR2-400
Symbol
DDR2-533
Unit
min
max
min
max
Note
DQ output access time from CK/CK
tAC
-600
+600
-500
+500
ps
DQS output access time from CK/CK
tDQSCK
-500
+500
-450
+450
ps
CK HIGH pulse width
tCH
0.45
0.55
0.45
0.55
tCK
CK LOW pulse width
tCL
0.45
0.55
0.45
0.55
tCK
tHP
min(tCL,
tCH)
-
min(tCL,
tCH)
-
ps
11,12
Clock cycle time, CL=x
tCK
5000
8000
3750
8000
ps
15
DQ and DM input setup time(differential strobe)
tDS(base)
150
-
100
-
ps
6,7,8,20
,28
DQ and DM input hold time(differential strobe)
tDH(base)
275
-
225
-
ps
6,7,8,21
,28
DQ and DM input setup time(single ended strobe)
tDS(base)
25
-
-25
-
ps
6,7,8,25
DQ and DM input hold time(single ended strobe)
tDH(base)
25
-
-25
-
ps
6,7,8,26
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
18
DQS low-impedance time from CK/CK
tLZ
(DQS)
tAC min
tAC max
tAC min
tAC max
ps
18
DQ low-impedance time from CK/CK
tLZ
(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
18
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
350
-
300
ps
13
DQ hold skew factor
tQHS
-
450
-
400
ps
12
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
Write command to first DQS latching transition
tDQSS
WL - 0.25
WL + 0.25
WL - 0.25
WL + 0.25
tCK
DQS input HIGH pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input LOW pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
10
Address and control input setup time
tIS
350
-
250
-
ps
5,7,9,23
Address and control input hold time
tIH
475
-
375
-
ps
5,7,9,23
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
19
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
19
Active to active command period for 1KB
page size products (x4, x8)
tRRD
7.5
-
7.5
-
ns
4
Active to active command period for 2KB
page size products (x16)
tRRD
10
-
10
-
ns
4
CK half period
Rev. 0.7 / Nov. 2008
23
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
-ContinuedParameter
DDR2-400
Symbol
DDR2-533
Units
min
max
min
max
Notes
Four Active Window for 1KB page size
products
tFAW
37.5
-
37.5
-
Four Active Window for 2KB page size
products
tFAW
50
-
50
-
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery +
precharge time
tDAL
WR+tRP*
-
WR+tRP*
-
tCK
14
Internal write to read command delay
tWTR
10
-
7.5
-
ns
24
Internal read to precharge command delay
tRTP
7.5
7.5
ns
3
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any nonread command
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
tCK
1, 2
tCKE
3
3
tCK
27
tAOND
2
2
2
2
tCK
16
tAON
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)
+1
ns
16
tAONPD
tAC(min)+
2
2tCK+tAC
(max)
+1
tAC(min)+
2
2tCK+tA
C(max)+1
ns
tAOFD
2.5
2.5
2.5
2.5
tCK
17,44
tAOF
tAC(min)
tAC(max)
+ 0.6
tAC(min)
tAC(max)
+ 0.6
ns
17,44
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+
2
2.5tCK+tA
C(max)+1
tAC(min)+
2
2.5tCK+t
AC(max)
+1
ns
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
OCD drive mode output delay
tOIT
0
tDelay
tIS+tCK+tI
H
CKE minimum pulse width
(HIGH and LOW pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Rev. 0.7 / Nov. 2008
2
12
0
tIS+tCK+tI
H
ns
ns
tCK
12
ns
ns
15
24
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
(DDR2-667 and DDR2-800)
Parameter
DDR2-667
Symbol
DDR2-800
min
max
min
max
Unit
Note
DQ output access time from CK/CK
tAC
-450
+450
-400
+400
ps
40
DQS output access time from CK/CK
tDQSCK
-400
+400
-350
+350
ps
40
CK HIGH pulse width
tCH(avg)
0.48
0.52
0.48
0.52
tCK(avg)
35,36
CK LOW pulse width
tCL(avg)
0.48
0.52
0.48
0.52
tCK(avg)
35,36
CK half period
tHP
min(tCL(abs),
tCH(abs))
-
min(tCL(abs),
tCH(abs))
-
ps
37
Clock cycle time, CL=x
tCK(avg)
3000
8000
2500
8000
ps
35,36
DQ and DM input setup time
tDS(base)
100
-
50
-
ps
6,7,8,20,28,31
DQ and DM input hold time
tDH(base)
175
-
125
-
ps
6,7,8,21,28,31
Control & Address input pulse width for each input
tIPW
0.6
-
0.6
-
tCK(avg)
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK(avg)
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
18,40
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
18,40
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
18,40
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
240
-
200
ps
13
DQ hold skew factor
tQHS
-
340
-
300
ps
38
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
39
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK(avg)
30
DQS input HIGH pulse width
tDQSH
0.35
-
0.35
-
tCK(avg)
DQS input LOW pulse width
tDQSL
0.35
-
0.35
-
tCK(avg)
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK(avg)
30
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK(avg)
30
Mode register set command cycle time
tMRD
2
-
2
-
tCK(avg)
Write preamble
tWPRE
0.35
-
0.35
-
tCK(avg)
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK(avg)
10
Address and control input setup time
tIS(base)
200
-
175
-
ps
5,7,9,22,29
Address and control input hold time
tIH(base)
275
-
250
-
ps
5,7,9,23,29
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK(avg)
19,41
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK(avg)
19,42
Activate to precharge command
tRAS
45
70000
45
70000
ns
3
Active to active command period for 1KB page size
products (x4, x8)
tRRD
7.5
-
7.5
-
ns
4,32
Active to active command period for 2KB page size
products (x16)
tRRD
10
-
10
-
ns
4,32
Four Active Window for 1KB page size products
tFAW
37.5
-
35
-
ns
32
Four Active Window for 2KB page size products
tFAW
50
-
45
-
ns
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
32
Auto precharge write recovery + precharge time
tDAL
WR+tnRP
-
WR+tnRP
-
nCK
33
Rev. 0.7 / Nov. 2008
2
32
nCK
25
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
-Continued-
Parameter
DDR2-667
Symbol
DDR2-800
min
max
min
max
-
7.5
-
Unit
Notes
ns
24,32
Internal write to read command delay
tWTR
7.5
Internal read to precharge command delay
tRTP
7.5
7.5
ns
3,32
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
32
Exit self refresh to a read command
tXSRD
200
-
200
-
nCK
Exit precharge power down to any non-read
command
tXP
2
-
2
-
nCK
Exit active power down to read command
tXARD
2
2
nCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
7 - AL
8 - AL
nCK
1, 2
CKE minimum pulse width
(HIGH and LOW pulse width)
tCKE
3
3
nCK
27
ODT turn-on delay
tAOND
2
2
2
2
nCK
16
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+0.7
ns
6,16,40
tAC(min)+2
2tCK(avg)+
tAC(max)+1
tAC(min)
+2
2tCK(avg)+
tAC(max)+1
ns
2.5
2.5
2.5
2.5
nCK
17,45
17,43,4
5
ODT turn-on
tAON
ODT turn-on(Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
ODT turn-off
tAOF
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(max)
+0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)
+2
2.5tCK(avg)+
tAC(max)+1
tAC(min)
+2
2.5tCK(avg)+
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
3
nCK
ODT power down exit latency
tAXPD
8
8
nCK
OCD drive mode output delay
tOIT
0
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Rev. 0.7 / Nov. 2008
tDelay
tIS + tCK (avg)
+ tIH
12
0
tIS + tCK
(avg)
+ tIH
12
ns
32
ns
15
26
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load
The following figure represents the timing reference load used in defining the relevant timing parameters
of the part. It is not intended to be either a precise representation of the typical system environment nor a
depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their
production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DUT
DQ
DQS
DQS
RDQS
RDQS
Output
Timing
reference
point
VTT = VDDQ/2
25Ω
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
2. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is
not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV
to CK - CK = +500 mV (+250mV to -500 mV for falling edges).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
between DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown below.
VDDQ
DUT
DQ
DQS, DQS
RDQS, RDQS
Output
Test point
VTT = VDDQ/2
25Ω
Slew Rate Test Load
Rev. 0.7 / Nov. 2008
27
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMR “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMR, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 KΩ resistor to insure proper operation.
tDQSH
DQS
DQS/
DQS
tDQSL
DQS
tWPRE
tWPST
VIH(dc)
VIH(ac)
DQ
D
D
VIL(ac)
VIL(dc)
tDS
VIH(ac)
tDS
DM
D
D
DMin
DMin
tDH
DMin
VIL(ac)
tDH
VIH(dc)
DMin
VIL(dc)
Figure -- Data input (write) timing
tCH
tCL
CK
CK/CK
CK
DQS
DQS/DQS
DQS
tRPRE
tRPST
DQ
Q
Q
tDQSQmax
Q
Q
tDQSQmax
tQH
tQH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. All voltages referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
Rev. 0.7 / Nov. 2008
28
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK or 2 * nCK) is required irrespective of operating frequency
5. Timings are specified with command/address input slew rate of 1.0 V/ns. See System Derating for other
slew rate values.
6. Timings are guaranteed with DQs, DM, and DQS’s (DQS/RDQS in singled ended mode) input slew rate of
1.0 V/ns. See System Derating for other slew rate values.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals
with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended
mode. See System Derating for other slew rate values.
8. tDS and tDH derating
tDS, tDH Derating Values for DDR2-400, DDR2-533(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Differential Slew Rate
4.0 V/ns
DQ
Slew
rate
V/ns
3.0 V/ns
2.0
△
tDS
125
△
tDH
45
△
tDS
125
1.5
83
21
83
1.0
0
0
0
0
0.9
-
-
-11
-14
0.8
-
-
-
-
0.7
-
-
-
0.6
-
-
-
0.5
-
-
-
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
△
△
△
tDH tDS tDH
45 +125 +45
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
21
+21
95
33
-
-
-
-
-
-
-
-
-
-
0
0
12
12
24
24
-
-
-
-
-
-
-
-
-11
-14
1
-2
13
10
25
22
-
-
-
-
-
-
-25
-31
-13
-19
-1
-7
11
5
23
17
-
-
-
-
-
-
-
-31
-42
-42
-19
-7
-8
5
-6
17
6
-
-
-
-
-
-
-
-43
-59
-31
-47
-19
-35
-7
-23
5
-11
-
-
-
-
-
-
-
-74
-89
-62
-77
-50
-65
-38
-53
+83
0.4 tDS,
- tDH Derating
- Values
- for- DDR2-667,
- units- in 'ps',
- Note- 1 applies
-127 -140
-115
-128 -103 -116
DDR2-800(ALL
to entire
Table)
DQS, DQS Differential Slew Rate
4.0 V/ns
DQ
Slew
rate
V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
2.0
△
tDS
100
△
tDH
45
△
tDS
100
△
tDH
45
△
tDS
100
△
tDH
45
△
tDS
-
△
tDH
-
1.5
67
21
67
21
67
21
79
33
1.0
0
0
0
0
0
0
12
12
0.9
-
-
-5
-14
-5
-14
7
-2
0.8
-
-
-
-
-13
-31
-1
-19
0.7
-
-
-
-
-
-
-10
0.6
-
-
-
-
-
-
0.5
-
-
-
-
-
0.4
-
-
-
-
-
1.6 V/ns
△
tDS
-
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
△
tDS
-
△
tDH
-
-
-
-
-
-
-
-
-
-
-
24
24
-
-
-
-
-
-
-
-
19
10
31
22
-
-
-
-
-
-
11
-7
23
5
35
17
-
-
-
-
-42
2
-30
14
-18
26
-6
38
6
-
-
-
-
-10
-59
2
-47
14
-35
26
-23
38
-11
-
-
-
-
-
-24
-89
-12
-77
0
-65
12
-53
-
-
-
-
-
-
-
-52
-140
-40
-128
-28
-116
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
Rev. 0.7 / Nov. 2008
29
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
tDS, tDH Derating Values for DDR2-400, DDR2-533(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Single-ended Slew Rate
4.0 V/ns
DQ
Slew
rate
V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
△
tDS
1.6 V/ns
1.4 V/ns
1.2 V/ns
△
tDS
△
tDH
△
tDS
△
tDH
△
tDS
△
tDH
2.0
188
188
167
146
125
63
1.5
146
167
125
125
83
42
1.0
63
125
42
83
0
0
0.9
-
-
31
69
-11
-14
0.8
-
-
-
-
-25
-31
-27
-30
-32
-44
-43
-62
-60
0.7
-
-
-
-
-
-
-45
-53
-50
-67
-61
-85
-78
0.6
-
-
-
-
-
-
-
-
-74
-96
0.5
-
-
-
-
-
-
-
-
-
-
0.4
-
-
-
-
-
-
-
-
-
-
1.0 V/ns
0.8 V/ns
△
tDH
△
tDS
△
tDH
△
tDS
△
tDH
△
tDS
△
tDH
△
tDS
△
tDH
△
tDS
△
tDH
-
-
-
-
-
-
-
-
-
-
-
-
81
43
-
-
-
-
-
-
-
-
-
-
-2
1
-7
-13
-
-
-
-
-
-
-
-
-13
-13
-18
-27
-29
-45
-
-
-
-
-
-
-86
-
-
-85
-109 -108 -152
-
-
-
-
-114 -102 -138 -132 -181 -183 -248
-128 -156 -145 -180 -175 -223 -226 -288
-
-
-210 -243 -240 -286 -291 -351
value listed in Table x.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’,
use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc) max and the first crossing
of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the
first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc)
region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig c.) If the
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.7 / Nov. 2008
30
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Fig. a. Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to ac
region
VIL(ac)max
Vss
Delta TF
Setup Slew Rate
=
Falling Signal
Rev. 0.7 / Nov. 2008
VREF(dc)-VIL(ac)max
Delta TF
Delta TR
Setup Slew Rate
=
Rising Signal
VIH(ac)min-VREF(dc)
Delta TR
31
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Fig. b. Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
tangent
line
VREF(dc)
Tangent
line
VIL(dc)max
VREF to ac
region
VIL(ac)max
Nomial
line
Vss
Delta TR
Delta TF
Setup Slew Rate Tangent line[VIH(ac)min-VREF(dc)]
=
Rising Signal
Delta TR
Setup Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Falling Signal
Delta TF
Rev. 0.7 / Nov. 2008
32
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Fig. c. Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
dc to VREF
region
VREF(dc)
nominal
slew rate
nominal
slew rate
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Hold Slew Rate
=
Rising Signal
Rev. 0.7 / Nov. 2008
VREF(dc)-VIL(dc)max
Delta TR
Delta TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
Delta TF
33
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Fig. d. Illustration of tangent line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
nominal
line
VIH(dc)min
tangent
line
VREF(dc)
dc to VREF
region
Tangent
line
nominal
line
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Rising Signal
Delta TR
Tangent line[VIH(ac)min-VREF(dc)]
Hold Slew Rate
=
Falling Signal
Delta TF
Rev. 0.7 / Nov. 2008
34
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values for DDR2-400, DDR2-533
CK, CK Differential Slew Rate
1.5 V/ns
2.0 V/ns
1.0 V/ns
△ tIS
△ tIH
△ tIS
△ tIH
△ tIS
△ tIH
Uni ts
Note s
4.0
+187
+94
+217
+124
+247
+154
ps
1
3.5
+179
+89
+209
+119
+239
+149
ps
1
3.0
+167
+83
+197
+113
+227
+143
ps
1
2.5
+150
+75
+180
+105
+210
+135
ps
1
2.0
+125
+45
+155
+75
+185
+105
ps
1
1.5
+83
+21
+113
+51
+143
+81
ps
1
1.0
+0
0
+30
+30
+60
+60
ps
1
0.9
-11
-14
+19
+16
+49
+46
ps
1
-25
-31
+5
-1
+35
+29
ps
1
-43
-54
-13
-24
+17
+6
ps
1
Command /
0.8
Address
Slew
0.7
rate(V/ns) 0.6
-67
-83
-37
-53
-7
-23
ps
1
0.5
-110
-125
-80
-95
-80
-65
ps
1
0.4
-175
-188
-145
-158
-115
-128
ps
1
0.3
-285
-292
-255
-262
-225
-232
ps
1
0.25
-350
-375
-320
-345
-290
-315
ps
1
0.2
-525
-500
-495
-470
-465
-440
ps
1
0.15
-800
-708
-770
-678
-740
-648
ps
1
0.1
-1450
-1125
-1420
-1095
-1390
-1065
ps
1
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tIS, tIH Derating Values for DDR2-667, DDR2-800
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
△ tIS
△ tIH
△ tIS
△ tIH
△ tIS
△ tIH
Uni ts
Note s
4.0
+15
+94
+180
+124
+210
+154
ps
1
3.5
+143
+89
+173
+119
+203
+149
ps
1
3.0
+133
+83
+163
+113
+193
+143
ps
1
2.5
+120
+75
+150
+105
+180
+135
ps
1
2.0
+100
+45
+130
+75
+150
+105
ps
1
1.5
+67
+21
+97
+51
+127
+81
ps
1
1.0
0
0
+30
+30
+60
+60
ps
1
0.9
Command /
0.8
Address
Slew
0.7
rate(V/ns) 0.6
-5
-14
+25
+16
+55
+46
ps
1
-13
-31
+17
-1
+47
+29
ps
1
-22
-54
+8
-24
+38
+6
ps
1
-34
-83
-4
-53
+26
-23
ps
1
0.5
-60
-125
-30
-95
0
-65
ps
1
0.4
-100
-188
-70
-158
-40
-128
ps
1
0.3
-168
-292
-138
-262
-108
-232
ps
1
0.25
-200
-375
-170
-345
-140
-315
ps
1
0.2
-325
-500
-395
-470
-265
-440
ps
1
0.15
-517
-708
-487
-678
-457
-648
ps
1
0.1
-1000
-1125
-970
-1095
-940
-1065
ps
1
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is
always earlier than the nominal slew rate for line between shaded ‘VREF(dc) to ac region’, use nominal slew
rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level
to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VREF(dc). If the actual signal is always later than the nominal slew rate
line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual
signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew
rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig
d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
11. MIN (t CL, t CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as
provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).
For example, t CL and t CH are = 50% of the period, less the half period jitter (t JIT(HP)) of the clock source,
and less the half period jitter due to crosstalk (t JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are, separately, due to data pin skew and output pattern effects, and
p-channel to n-channel variation of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the
output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle.
14. t DAL = (nWR) + (tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the t WR parameter stored in the MR.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)
clocks =4 +(4)clocks=8clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode.
In case of clock frequency change during precharge power-down, a specific procedure is required as described
in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are
referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or
begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving
(tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
Rev. 0.7 / Nov. 2008
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19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when
the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to
calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
VTT + 2xmV
VOH + xmV
VTT + xmV
VOH + 2xmV
tLZ
tRPRE begin point
tHZ
tRPST end point
T1
T2
T1
VOL + 1xmV
VTT -xmV
VOL + 2xmV
VTT - 2xmV
T2
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from
the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal
applied to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc)
to the differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
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22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test.
24. tWTR is at least two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the
input signal crossing at the VIH (ac) level to the single-ended data strobe crossing VIH/L (dc) at the start
of its transition for a rising signal, and from the input signal crossing at the VIL (ac) level to the singleended data strobe crossing VIH/L (dc) at the start of its transition for a falling signal applied to the device
under test. The DQS signal must be monotonic between Vil(dc)max and Vih (dc) min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the
input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of
its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended
data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under
test. The DQS signal must be monotonic between Vil(dc)max and Vih (dc) min.
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE
must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus,
after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK
+ tIH.
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data
before a valid READ can be executed.
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0,
A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not
affected by the amount of clock jitter applied (i.e. tJIT (per), tJIT (cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be
met whether clock jitter is present or not.
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective
clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT (per), tJIT (cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
31. These parameters are measured from a data signal ((L/U) DM, (L/U) DQ0, (L/U) DQ1, etc.) transition
edge to its respective data strobe signal ((L/U/R)DQS/DQS) crossing.
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support
tnPARAM = RU {tPARAM / tCK (avg)}, which is in clock cycles, assuming all input clock jitter specifications
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
are satisfied.
For example, the device will support tnRP = RU {tRP / tCK (avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support
tnRP =RU {tRP / tCK (avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge
command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input
clock jitter.
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK (avg) [ps]}, where WR is the value
programmed in the mode register set.
34. New units, ‘tCK (avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.
Unit ‘tCK (avg)’ represents the actual tCK (avg) of the input clock under operation.
Unit ‘nCK’, represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ‘tCK’, is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered
at Tm+2, even if (Tm+2 - Tm) is 2 x tCK (avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as
'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter
specified is a random jitter meeting a Gaussian distribution.
DDR2-667
Parameter
DDR2-800
Symbol
Units
Notes
100
ps
35
-80
80
ps
35
250
-200
200
ps
35
-200
200
-160
160
ps
35
tERR(2per)
-175
175
-150
150
ps
35
Cumulative error across 3 cycles
tERR(3per)
-225
225
-175
175
ps
35
Cumulative error across 4 cycles
tERR(4per)
-250
250
-200
200
ps
35
Cumulative error across 5 cycles
tERR(5per)
-250
250
-200
200
ps
35
Cumulative error across n cycles,
n=6...10, inclusive
tERR(6~10per)
-350
350
-300
300
ps
35
Cumulative error across n cycles,
n=11...50, inclusive
tERR(11~50per)
-450
450
-450
450
ps
35
tJIT (duty)
-125
125
-100
100
ps
35
min
max
min
max
tJIT (per)
-125
125
-100
tJIT (per, lck)
-100
100
tJIT (cc)
-250
Cycle to cycle clock period jitter during DLL
locking period
tJIT (cc, lck)
Cumulative error across 2 cycles
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
Duty cycle jitter
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36. These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and
max of SPEC values are to be used for calculations in the table below.)
Parameter
Symbol
min
max
Units
Absolute clock period
tCK (abs)
tCK (avg), min + tJIT (per), min
tCK (avg), max + tJIT (per), max
ps
Absolute clock HIGH pulse width
tCH (abs)
tCH (avg), min* CK (avg), min +
tJIT (per), min
tCH (avg), max* tCK (avg), max
+ tJIT(per), max
ps
Absolute clock LOW pulse width
tCL (abs)
tCL (avg), min* tCK (avg), min + tCL (avg), max* tCK (avg), max +
tJIT (per), min
tJIT (per), max
ps
Example: For DDR2-667, tCH (abs), min = (0.48 x 3000 ps) - 125 ps = 1315 ps
37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but
not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing
tQH.
The value to be used for tQH calculation is determined by the following equation;
tHP = Min (tCH (abs), tCL (abs)),
where,
tCH (abs) is the minimum of the actual instantaneous clock HIGH time;
tCL (abs) is the minimum of the actual instantaneous clock LOW time;
38. tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the
input is transferred to the output; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and
p-channel to n-channel variation of the output drivers
39. tQH = tHP? tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and
tQHS is the specification value under the max column.
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye
will be.}
Examples:
1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum.
2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps
minimum.
40. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and
tERR(6-10per), max = + 293 ps, then tDQSCK, min (derated) = tDQSCK, min - tERR(6-10per),max = 400 ps - 293 ps = - 693 ps and tDQSCK, max (derated) = tDQSCK, max - tERR(6-10per),min = 400 ps +
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31CFR
272 ps = + 672 ps. Similarly, tLZ (DQ) for DDR2-667 derates to tLZ (DQ), min (derated) = - 900 ps - 293
ps = - 1193 ps and tLZ (DQ), max (derated) = 450 ps + 272 ps = + 722 ps. (Caution on the min/max
usage!)
41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT (per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT (per), min = - 72 ps and tJIT (per),
max = + 93 ps, then tRPRE, min (derated) = tRPRE, min + tJIT (per), min = 0.9 x tCK (avg) - 72 ps = +
2178 ps and tRPRE, max (derated) = tRPRE, max + tJIT (per), max = 1.1 x tCK (avg) + 93 ps = + 2843
ps. (Caution on the min/max usage!)
42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT (duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT (duty), min = - 72 ps and tJIT (duty),
max = + 93 ps, then tRPST, min (derated) = tRPST, min + tJIT (duty), min = 0.4 x tCK (avg) - 72 ps = +
928 ps and tRPST, max (derated) = tRPST, max + tJIT (duty), max = 0.6 x tCK (avg) + 93 ps = + 1592 ps.
(Caution on the min/max usage!)
43. When the device is operated with input clock jitter, this parameter needs to be derated by {tJIT (duty), max - tERR(6-10per),max} and {- tJIT (duty), min - tERR(6-10per),min} of the actual input
clock.(output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(610per), max = + 293 ps, tJIT (duty), min = - 106 ps and tJIT (duty), max = + 94 ps, then tAOF, min (derated) = tAOF, min + {- tJIT (duty), max - tERR(6-10per),max} = - 450 ps + {- 94 ps - 293 ps} = - 837 ps
and tAOF, max (derated) = tAOF, max + {- tJIT (duty), min - tERR(6-10per),min} = 1050 ps + {106 ps +
272 ps} = + 1428 ps. (Caution on the min/max usage!)
44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH
pulse width of 0.5 relative to tCK. tAOF, min and tAOF, max should each be derated by the same amount
as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input
clock has a worst case tCH of 0.45, the tAOF, min should be derated by subtracting 0.05 x tCK from it,
whereas if an input clock has a worst case tCH of 0.55, the tAOF, max should be derated by adding 0.05 x
tCK to it. Therefore, we have;
tAOF, min (derated) = tAC, min - [0.5 - Min(0.5, tCH, min)] x tCK
tAOF, max (derated) = tAC, max + 0.6 + [Max(0.5, tCH, max) - 0.5] x tCK
or
tAOF, min (derated) = Min (tAC, min, tAC, min - [0.5 - tCH, min] x tCK)
tAOF, max (derated) = 0.6 + Max (tAC, max, tAC, max + [tCH, max - 0.5] x tCK)
where tCH, min and tCH, max are the minimum and maximum of tCH actually measured at the DRAM
input balls.
45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH (avg), average input
clock HIGH pulse width of 0.5 relative to tCK (avg). tAOF, min and tAOF, max should each be derated by
the same amount as the actual amount of tCH (avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case tCH (avg) of 0.48, the tAOF, min should be derated by subRev. 0.7 / Nov. 2008
42
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
tracting 0.02 x tCK (avg) from it, whereas if an input clock has a worst case tCH (avg) of 0.52, the tAOF,
max should be derated by adding 0.02 x tCK (avg) to it. Therefore, we have;
tAOF, min (derated) = tAC, min - [0.5 - Min(0.5, tCH (avg), min)] x tCK (avg)
tAOF, max (derated) = tAC, max + 0.6 + [Max(0.5, tCH (avg), max) - 0.5] x tCK (avg)
or
tAOF, min (derated) = Min (tAC, min, tAC, min - [0.5 - tCH (avg), min] x tCK (avg))
tAOF, max (derated) = 0.6 + Max (tAC, max, tAC, max + [tCH (avg), max - 0.5] x tCK (avg))
where tCH (avg), min and tCH (avg), max are the minimum and maximum of tCH (avg) actually measured
at the DRAM input balls.
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT (duty) and
tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter
table and are not derated. Thus the final derated values for tAOF are;
tAOF, min (derated_final) = tAOF, min (derated) + {- tJIT (duty), max - tERR(6-10per),max}
tAOF, max (derated_final) = tAOF, max (derated) + {- tJIT (duty), min - tERR(6-10per),min}
Rev. 0.7 / Nov. 2008
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5. Package Dimensions
Package Dimension(x4,x8)
60Ball Fine Pitch Ball Grid Array Outline
8.00 ± 0.10
0.15 ± 0.05
11.40 ± 0.10
A1 BALL MARK
< Top View>
< SIDE View>
1.10 ± 0.10
0.80 X 8 = 6.40
0.34 ± 0.05
2.10 ± 0.10
9 8 7
2-R0.13MAX
A1 BALL MARK
3 2 1
0.80
A
B
C
D
E
F
G
H
J
K
L
60X Φ0.45 ± 0.05
1.60
1.60
0.80
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.7 / Nov. 2008
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HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Package Dimension(x16)
84Ball Fine Pitch Ball Grid Array Outline
8.00 ± 0.10
0.15 ± 0.05
13.00 ± 0.10
A1 BALL MARK
< Top View>
< SIDE View>
1.10 ± 0.10
0.80 X 8 = 6.40
2.10 ± 0.10
A1 BALL MARK
3 2 1
9 8 7
0.34 ± 0.05
0.80
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
84X Φ0.45 ± 0.05
2-R0.13MAX
1.60 1.60
0.80
< Bottom View>
Note: All dimensions are in millimeters.
Rev. 0.7 / Nov. 2008
45