HANBit HMN4M8DV(N) Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 3.3V Part No. HMN4M8DV(N) GENERAL DESCRIPTION The HMN4M8DV Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits. The HMN4M8DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after V CC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain t he memory until after V CC returns valid. The HMN4M8DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non volatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES PIN ASSIGNMENT w Access time : 55, 70ns w High-density design : 32Mbit Design w Battery internally isolated until power is applied w Industry-standard 40-pin 4,096K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 5-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 36-pin Encapsulated Package VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 21 40-pin Encapsulated Package w Package Option - HMN4M8DV - 36 Pin DIP Package - HMN4M8DVN - 40 Pin DIP Package URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 1 HANBit Electronics Co.,Ltd NC VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC HANBit HMN4M8DV(N) FUNCTIONAL DESCRIPTION The HMN4M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A 0-A19) defines which of the 4,194,304 bytes of data is accessed. Valid data will be a vailable to the eight data output drivers within t ACC (access time) after the last address input signal is stable. When power is valid, the HMN4M8DV operates as a standard CMOS SRAM. During power -down and power-up cycles, the HMN4M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN4M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will d etermine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in t ODW from its falling edge. The HMN4M8DV provides full functional capability for V cc greater than 4.5 V and write protects by 4.37 V nominal. Power-down/power-up control circuitry constantly monitors the V cc supply for a power-fail-detect threshold V PFD. When VCC falls below the V PFD threshold, the SRAM automatically write -protects the data. All inputs to the RAM become “don’t care” and all outputs are high impedance. As V cc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain d ata. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external V cc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION A0-A19 /OE (1M x 8) x 4 SRAM Block CE2 /WE /CE1 Power A0-A21 : Address Input DQ0-DQ7 /CE : Chip Enable VSS : Ground DQ0-DQ7 : Data In / Data Out /WE : Write Enable /CE CON /OE : Output Enable /CE A20-A21 Power – Fail Control VCC VCC: Power (+5V) NC : No Connection Lithium Cell URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 2 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) TRUTH TABLE MODE /OE /CE CE2 /WE I/O OPERATION POWER Not selected X H X X High Z Standby Output disable H L H H High Z Active Read L L H H DOUT Active Write X L H L DIN Active ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VCC -0.5V to VCC +0.2V VT -0.2V to 4.6V DC voltage applied on V CC relative to VSS DC Voltage applied on any pin excluding V CC relative to VSS 0 to 70°C Commercial -40 to 85°C Industrial Operating temperature TOPR Storage temperature TSTG -65°C to 150°C Temperature under bias TBIAS -40°C to 85°C TSOLDER 260°C Soldering temperature NOTE: CONDITIONS For 10 second Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER SYMBOL MIN TYPICAL MAX Supply Voltage VCC 3.0V 3.3V 3.6V Ground VSS 0 0 0 Input high voltage VIH 2.2 - Input low voltage VIL NOTE: -0.2 2) - VCC+0.3V 1) 0.6V 1. Overshoot: VCC+2.0V in case of pulse width ≤20ns. 2. Undershoot: -2.0V in case of pulse width ≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 3 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) CAPACITANCE (TA=25℃ , f=1MHz) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS SYMBOL MAX MIN UNIT Input voltage = 0V CIN 8 - pF Output voltage = 0V CI/O 10 - pF NOTE: 1. Capacitance is sampled, not 100% tested. DC AND OPERATION CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax ) UNI PARAMETER CONDITIONS SYMBOL MIN TYP. MAX Input Leakage Current VIN=VSS to VCC ILI -4 - +4 mA Output Leakage Current /CE=VIH or /OE=VIH or /WE=VIL ILO -4 - +4 mA Output high voltage IOH=-1.0 mA VOH 2.4 - - V Output low voltage IOL= 2.1 mA VOL - - 0.4 V Standby supply current /CE≥ VCC-0.2V ISB1 - - 80 mA ICC1 - - 12 ㎃ ICC2 - - 50 ㎃ Power-fail-detect voltage VPFD 2.5 2.6 2.7 V Supply switch-over voltage VSO - 3 - V T Cycle time=Min, 100% duty, II/O=0㎃ , /CE<Vcc-0.2V, Average operating current VIN<0.2V or VIN>VCC-0.2V Cycle time=1us, 100% duty, II/O=0㎃ , /CE=VIL, VIN=VIL or VIH CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels 0 to 3V Input rise and fall times < 5 ns Input and output timing 1.5V reference levels +5V VALUE URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 1.9KΩ DOUT 100㎊ 1KΩ 5㎊ 1KΩ ( unless otherwise specified) Output load (including scope and jig) 1.9KΩ DOUT +5V See Figure 1 and 2 4 Figure 1. Figure 2. Output Load A Output Load B HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER SYMBOL Read Cycle Time tRC Address Access Time tACC Chip enable access time -70 CONDITIONS -85 -120 -150 UNIT MIN MAX MIN MAX MIN MAX MIN MAX 70 - 85 - 120 - 150 - ns Output load A - 70 - 85 - 120 - 150 ns tACE Output load A - 70 - 85 - 120 - 150 ns Output enable to Output valid tOE Output load A - 35 - 45 - 60 - 70 ns Chip enable to output in low Z tCLZ Output load B 5 - 5 - 5 - 10 - ns Output enable to output in low Z tOLZ Output load B 5 - 0 - 0 - 5 - ns Chip disable to output in high Z tCHZ Output load B 0 25 0 35 0 45 0 60 ns Output disable to output high Z tOHZ Output load B 0 25 0 25 0 35 0 50 ns Output hold from address change tOH Output load A 10 - 10 - 10 - 10 - ns WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax ) PARAMETER SYMBOL Write Cycle Time tWC Chip enable to end of write tCW Address setup time -70 CONDITIONS -85 -120 -150 UNI MIN MAX MIN MAX MIN MAX Min Max T 70 - 85 - 120 - 150 - ns Note 1 65 - 75 - 100 - 100 - ns tAS Note 2 0 - 0 - 0 - 0 - ns Address valid to end of write tAW Note 1 65 - 75 - 100 - 90 - ns Write pulse width tWP Note 1 55 - 65 - 85 - 90 - ns Write recovery time (write cycle 1) tWR1 Note 3 5 - 5 - 5 - 5 - ns Write recovery time (write cycle 2) tWR2 Note 3 15 - 15 - 15 - 15 - ns Data valid to end of write tDW 30 - 35 - 45 - 50 - ns Data hold time (write cycle 1) tDH1 Note 4 0 - 0 - 0 - 0 - ns Data hold time (write cycle 2) tDH2 Note 4 10 - 10 - 10 - 0 - ns Write enabled to output in high Z tWZ Note 5 0 25 0 30 0 40 0 50 ns Output active from end of write tOW Note 5 5 - 0 - 0 - 5 - ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at t he later transition of /CE going low and /WE going low. 3. Either t WR1 or tWR2 must be met. 4. Either t DH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outpu ts remain in highimpedance state. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 5 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) DATA RETENTION CHARACTERISTICS (TA= TOPR, VCC=5V) PARAMETER SYMBOL CONDITIONS MIN TYP. MAX UNIT Vcc for data retention VDR CE≥Vcc-0.2V 1.5 - 3.6 V Data retention current IDR Vcc=3.0V, CE≥Vcc 2 24 uA Data retention set-up time tSDR See 0 - - Recovery time tRDR waveform tRC - - MIN TYP. MAX UNIT tF 300 - - ms tFB 150 - - ms tR 10 - - ms 250 ms data retention ms POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=3.3V) PARAMETER VPFD(max) to VPFD(min) VCC Fail Time VPFD(max) to VSS VCC Fail Time VPFD(max) to VPFD(min) VCC Rise Time SYMBOL CONDITIONS Delay after Vcc slews down Write Protect Time tWPT past VPFD before SRAM is 40 Write-protected. Chip Enable Recovery VSS to VPFD (min) VCC Rise Time tCER 40 - 120 ms tRB 1 - - ms TIMING WAVEFORM - READ CYCLE NO.1 (Address Access)* 1,2 tRC Address tACC tOH DOUT URL : www.hbe.co.kr Rev. 1.0 (May, 2002) Previous Data Valid Data Valid 6 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) - READ CYCLE NO.2 (/CE Access) *1,3,4 tRC /CE tACE tCHZ tCLZ DOUT High-Z High-Z - READ CYCLE NO.3 (/OE Access) *1,5 tRC Address tACC /OE tOE DOUT tOHZ tOLZ Data Valid High-Z High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =V IL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = V IL. 5. Device is continuously selected: /CE = V IL *1,2,3 - WRITE CYCLE NO.1 (/WE-Controlled) tWC Address tAW tWR1 tCW /CE tAS tWP /WE tDW DIN Data-in Valid tWZ DOUT Rev. 1.0 (May, 2002) tOW High-Z Data Undefined (1) URL : www.hbe.co.kr tDH1 7 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) *1,2,3,4,5 - WRITE CYCLE NO.2 (/CE-Controlled) Address tAW tAS tWR2 tCW /CE tWP /WE tDH2 tDW Data-in DIN tWZ DOUT NOTE: High-Z Data Undefined (2) 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opp osite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either t WR1 or tWR2 must be met. 5. Either t DH1 or tDH2 must be met. POWER-DOWN/POWER-UP TIMING VCC tPF 4.75 VPFD VPFD 4.25 VSO VSO tFS tWPT tPU tCER tDR /CE URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 8 HANBit Electronics Co.,Ltd HANBit HMN4M8DV(N) PACKAGE DIMENSION Dimension Min Max A 2.070 2.100 B 0.710 0.740 C 0.365 0.375 D 0.015 - E 0.008 0.013 F 0.590 0.630 G 0.017 0.023 H 0.090 0.110 I 0.080 0.110 J 0.120 0.150 J A H I G C D E B F All dimensions are in inches. ORDERING INFORMATION H M N 4 M 8 D V N – 70 I Temperature Option : Blank : Commercial(0 to 70°C) I : Industrial : -40 to 85°C Speed Option : 70 = 70ns 85 = 85ns 120 = 120ns 150 = 150ns Package Option : Blank : 36 Pin Dip Package N : 40 Pin Dip Package Operation Voltage : 3.3V Dip type package Device : 4,096K x 8 bit Nonvolatile SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 9 HANBit Electronics Co.,Ltd