Rohm BR24C21FJ Id rom for crt display Datasheet

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
ID ROM for CRT display
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
The BR24C21 series are 1kbits serial EEPROMs and support DDC1TM and DDC2TM interfaces for PLUG&PLAY
displays.
!Features
1) 128 x 8 bits serial EEPROM
2) Operating voltage range (2.5V∼5.5V)
3) Completely implements DDC1TM / DDC2TM interface
for monitor identification
Transmit-Only Mode
Recovery Mode
Bi-directional Mode
4) Page write function : 8 bytes
5) Low current consumption
Active (at 5V) : 1.5mA (Typ.)
Standby (at 5V) : 10µA (Typ.)
6) DATA security
Write enable feature
Inhibit to WRITE at low Vcc
7) Compact packages
8) High reliability fine pattern CMOS technology
9) Rewriting possible up to 100,000 times
10) Data can be stored for ten years without corruption
11) Noise filters at SCL, SDA and VCLK pins
!Absolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Unit
VCC
−0.3~+6.5
V
Supply voltage
Pd
Power disssipation
800(DIP8)
∗1
450(SOP8)
∗2
450(SOP-J8)
∗2
350(SSOP-B8)
∗3
mW
−65~+125
°C
Topr
−40~+85
°C
−
−0.3~VCC+0.3
V
Storage temperature range
Tstg
Operating temperature range
Terminal voltage
∗1 Degradation is done at 8.0mW/°C for operation above 25°C.
∗2 Degradation is done at 4.5mW/°C for operation above 25°C.
∗3 Degradation is done at 3.5mW/°C for operation above 25°C.
!Recommended operating conditions (Ta=25°C)
Symbol
Limits
Unit
Supply voltage
Parameter
VCC
2.5~5.5
V
Input voltage
VIN
0~VCC
V
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!Block diagram
N.C.
1
1kbits EEPROM array
2
N.C.
3
VCC
7
VCLK
6
SCL
5
SDA
8bits
7bits
N.C.
8
Address
decoder
7bits
Data
register
Slave word
address register
START
STOP
Control logic
ACK
GND
High voltage generator
4
Vcc level detecter
!Pin assignment
VCC
VCLK
SCL
SDA
8
7
6
5
BR24C21
BR24C21F
BR24C21FJ
BR24C21FV
1
2
3
4
N.C.
N.C.
N.C.
GND
!Pin descriptions
Pin No.
Pin name
I/O
1
N.C.
−
No connection
Function
2
N.C.
−
No connection
3
N.C.
−
No connection
4
GND
−
Ground (0V)
5
SDA
I/O
6
SCL
I
Serial clock input for Bi-directional Mode
Slave and word address,
serial data input, serial data output
7
VCLK
I
Clock input (Transmit-Only Mode)
Write enable (Bi-directional Mode)
8
VCC
−
Power supply
∗ An open drain output requires a pull-up resistor.
∗
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!Electrical characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.5∼5.5V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VIH1
0.7VCC
−
−
V
SCL, SDA
"HIGH" input volatge1
Conditions
"LOW" input volatge1
VIL1
−
−
0.3VCC
V
SCL, SDA
"HIGH" input volatge2
VIH2
2.0
−
−
V
VCLK
"LOW" input volatge2
VIL2
−
−
0.8
V
VCLK, VCC≥4.0V
"LOW" input volatge3
VIL3
−
−
0.2VCC
V
VCLK, VCC<4.0V
"LOW" output volatge
VOL
−
−
0.4
V
SDA, IOL=3.0mA
Input leakage current
ILI
−1
−
1
µA
SCL, VCLK, VIN=0V~VCC
Output leakage current
ILO
−1
−
1
µA
SDA, VOUT=0V~VCC
Operating current
ICC
−
−
3.0
mA
VCC=5.5V, fSCL=400kHz
Standby current
ISB
−
10
100
µA
VCC=5.5V, SDA=SCL=VCC, VCLK=GND ∗1
∗1 Transmit-Only Mode…After the power is on, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are in Standby state without providing the clock on the VCLK pin.
After the VCLK pin is provided the clock, the device is switched from Standby to Transmit-Only Mode, and the operating current runs.
Bi-directional Mode…The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are in Standby state after each command is porformed.
!Operating timing characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.5∼5.5V)
Parameter
Symbol
Fast-mode
Vcc=2.5~5.5V
Standard-mode
Vcc=2.5~5.5V
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
SCL frequency
fSCL
−
−
400
−
−
100
kHz
Data clock "HIGH" time
tHIGH
0.6
−
−
4.0
−
−
µs
Data clock "LOW" time
tLOW
1.3
−
−
4.7
−
−
µs
tR
−
−
0.3
−
−
1.0
µs
SDA/SCL rise time
tF
−
−
0.3
−
−
0.3
µs
tHD : STA
0.6
−
−
4.0
−
−
µs
Start condition setup time
tSU : STA
0.6
−
−
4.7
−
−
µs
Input data hold time
tHD : DAT
0
−
−
0
−
−
ns
Input data setup time
tSU : DAT
100
−
−
250
−
−
ns
SDA/SCL fall time
Start condition hold time
tPD
−
−
0.9
−
−
3.5
µs
tSU : STO
0.6
−
−
4.0
−
−
µs
Bus open time before start or transfer
tBUF
1.3
−
−
4.7
−
−
µs
Internal write cycle time
tWR
−
−
10
−
−
10
ms
tI
−
−
0.1
−
−
0.1
µs
Output data delay time (SCL)
Stop condition setup time
Noise erase valid time (SCL and SDA)
<Transmit-Only Mode>
tVPD
−
−
1.0
−
−
2.0
µs
VCLK "HIGH" time
tVHIGH
0.6
−
−
4.0
−
−
µs
VCLK "LOW" time
tVLOW
1.3
−
−
4.7
−
−
µs
VCLK setup time
tVSU
0
−
−
0
−
−
µs
Output data delay time (VCLK)
VCLK hold time
tVHD
0.6
−
−
4.0
−
−
µs
Mode transition time
tVHZ
−
−
0.5
−
−
1.0
µs
Transmit-Only powerup time
tVPU
0
−
−
0
−
−
µs
tVI
−
−
0.1
−
−
0.1
µs
Noise erase valid time (VCLK)
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!Timing charts
SYNCHRONOUS DATA TIMING
tR
tF
tHIGH
SCL
tHD : STA
tSU : DAT
tLOW
tHD : DAT
SDA
(IN)
tBUF
tPD
SDA
(OUT)
SCL
tSU : STA
tHD : STA
tSU : STO
SDA
START BIT
STOP BIT
Fig.7
•SDA data is latched into the chip at the rising edge of the SCL clock.
•Output data toggles at the falling edge of the SCL clock.
WRITE CYCLE TIMING
SCL
SDA
D0
ACK
tWR
WRITE DATA
(n)
STOP CONDITION
START CONDITION
Fig.8
WRITE ENABLE TIMING
START BIT
STOP BIT
SCL
SDA
VCLK
WRITE COMMAND
tVHD
tVSU
Fig.9
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!Circuit operation
The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV operate in two modes, Transmit-Only Mode and Bi-directional
Mode. The devices operate in Transmit-Only Mode when they will power up. In this mode, the devices transmit data on
the SDA pin with the VCLK clock. This mode is continued by providing a valid high to low transition on the SCL pin.
The devices can be switched into Bi-directional Mode by providing a valid high to low transition on the SCL pin. They
begin to count the VCLK clock at once. If the VCLK counter reaches 128 clock without the command for Bi-directional
Mode, the device revert to Transmit-Only Mode. (Recovery function) If the devices are received the command for Bidirectional Mode and respond with an Acknowledge before the VCLK counter reaches 128 clock, it is impossible to revert
to Transmit-Only Mode. (The way to switch Bi-directional Mode to Transmit-Only Mode is that the power down again.)
* When the power is on, the SCL pin set to VCC (High level).
(1) Transmit-Only Mode
•After the power is on, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are in Transmit-Only Mode. In this
mode, the data can be output by providing the clock on the VCLK pin.
•When the power is on, the SCL pin set to VCC (High level).
•The state of SDA is high-impedance during input of the first 9 clocks, and a data is output starting with the 10th rising
clock edge on VCLK. After the power is on, the output data is as follow
00h address data → 01h address data → 02h address data → …
The address is incremented by one with every 9 clock of VCLK. All address is output in this mode. When the counter
reaches the last address, the next output data is 00h address data.
•In the mode, the NULL bit (High data) is output between the address data and the next address data.
•The read operation in Transmit-Only Mode can be started after the power stabilized.
VCC
SCL
1
9
10
VCLK
tVPU
D7
SDA
D6
D5
D4
00h ADDRESS DATA
Fig.10 TRANSMIT-ONLY MODE
tVHIGH tVLOW
VCLK
tVPD
SDA
D1
ADDRESS n
DATA
D0
D7
NULL BIT
DATA=1
Fig.11 NULL BIT
D6
ADDRESS n+1
DATA
D3
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
(2) Bi-directional Mode
1) Bi-directional Mode and Recovery function
•The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV can be switched from Transmit-Only Mode to
Bi-directional Mode by providing a valid high to low transition on the SCL pin, and the state of SDA is high-impedance.
•After a valid high to low transition on the SCL pin, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV begin to
count the VCLK clock. If the VCLK counter reaches 128 clock without the command for Bi-directional Mode, the
device revert to Transmit-Only Mode. (Recovery function) The VCLK counter is reset by providing a valid high to low
transition on the SCL pin. After reversion to Transmit-Only Mode, the devices begin to output a data with the 129th
rising clock edge on VCLK. The output data is 00h address data at the time.
•If the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are switched from Transmit-Only Mode and received
the command for Bi-directional Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only
Mode. (The only way to revert to Transmit-Only Mode is that the power down again.) Unless the input device code is
“1010”, the device responds no Acknowledge. If the VCLK counter reaches 128 clock afterward, it is possible to revert
to Transmit-Only Mode for Recovery function. If the master generates a stop condition during the slave address input,
it is possible to revert to Transmit-Only Mode.
•When the devices are switched from Transmit-Only Mode to Bi-directional Mode, the period of tVHZ need to be held.
Bi-directional
Transition Mode with possibility to return to Transmit-Only Mode
Transmit-Only
Transmit-Only
MODE
1
2
3
4
127
128
129
VCLK
ADDRESS 00h
SCL
tVHZ
D7
D6
D5
D4
SDA
Fig.12 RECOVERY MODE
MODE
Transmit-only
Bi-directional
Transition Mode with possibility to return to Transmit-Only Mode
1
2
Bi-directional
parmanently
n<128
n
VCLK
SCL
tVHZ
S
1
0
1
SDA
Fig.13 MODE CHANGE
0
∗
∗
∗
R/W
ACK
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
2) Bi-directional Mode
START CONDITION
•All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
•The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this condition has been met.
STOP CONDITION
•All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH.
•The stop condition initiates internal write cycle to write the data into memory array after write sequence.
•The stop condition is also used to place the device into the standby power mode after read sequence.
•A stop condition can only be issued after the transmitting device has released the bus.
DEVICE ADDRESSING
•Following a START condition, the master output the device address of the slave to be accessed. The most significant
four bits of the slave address are the “device type indentifier”, For the BR24C21, BR24C21F, BR24C21FJ and
BR24C21FV this is fixed as “1010”.
•The next three bits of the slave address are don’t care.
•The last bit of the stream determines the operation to be performed. When set to “1”, a read operation is selected ;
when set to “0”, a write operation is selected.
R / W set to “0” ··· WRITE
(This bit also sets to “0” for random read operation)
R / W set to “1” ··· READ
1010
∗
∗
∗
R/W
∗ Don't care
WRITE PROTECT FUNCTION
•WRITE ENABLE (VCLK)
When using the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV in the Bi-directional Mode, the VCLK pin can
be used as a write enable pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents
writing to any location in the array. Changing VCLK from high to low during the self-timed program operation will not
halt programming of the device. Setting VCLK low allow the word address setting in random read.
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
ACKNOWLEDGE
•Acknowledge is a software convention used to indicate successful data transfers. The master or the slave will release
the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to
acknowledge that the eight bits of data has been received.
•The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV will respond with an Acknowledge after recognition of a
START condition and its slave address. If both the device and a write operation have been selected, the BR24C21,
BR24C21F, BR24C21FJ and BR24C21FV will respond with an Acknowledge, after the receipt of each subsequent
8-bit word.
•In the READ mode, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV will transmit eight bits of data, release
the SDA line, and monitor the line for an Acknowledge.
•If an Acknowledge is detected, and no STOP condition is generated by the master, the BR24C21, BR24C21F,
BR24C21FJ, BR24C21FV will continue to transmit the data.
•If an Acknowledge is not detected, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV will terminate further
data transmissions and await a STOP condition before returning to the standby mode.
START CONDITION
(START BIT)
1
SCL
(From µ−COM)
8
9
SDA
(µ−COM
OUTPUT DATA)
SDA
(IC OUTPUT DATA)
Acknowledge Signal
(ACK Signal)
Fig.14 ACKNOWLEDGE RESPONSE FROM RECEIVER
3) Bi-directional Mode Command
BYTE WRITE
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
1 0 1 0 ∗ ∗ ∗
WORD
ADDRESS
∗
R A
/ C
W K
WA
6
S
T
O
P
DATA
WA
0
D7
A
C
K
D0
A
C
K
VCLK
∗Don't care
Fig.15 BYTE WRITE CYCLE TIMING
•When the master generates a STOP condition, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV begin the
internal write cycle to the nonvolatile array.
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
PAGE WRITE
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS(n)
1 0 1 0 ∗ ∗ ∗
∗
WA
6
DATA(n+7)
DATA(n)
WA
0
R A
/ C
W K
D7
S
T
O
P
D0
D0
A
C
K
A
C
K
A
C
K
VCLK
∗Don't care
Fig.16 PAGE WRITE CYCLE TIMING
•If the master transmits the next data instead of generating a stop condition in byte write cycle, the BR24C21,
BR24C21F, BR24C21FJ and BR24C21FV transfer from byte write cycle to page write cycle. After the receipt of each
word, the three lower order address pointer bits are internally incremented by one. The high order five bits of the word
address remains constant.
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll
over”, and the previous transmitted data will be overwritten.
CURRENT READ
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1
0
1
0
∗
∗
∗
S
T
O
P
DATA
D7
R A
/ C
W K
D0
A
C
K
Fig.17 CURRENT READ CYCLE TIMING
•The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV contain an internal address counter which maintains the
address of the last word accessed, incremented by one. If the last accessed address is address n in a read operation,
the next read operation will access data from address n+1 and increment the current address counter. If the last
accessed address is address n in a write operation, the next read operation will access data from address n. If the
master does not transfer the acknowledge but does generate a stop condition, the current address read operation
only provides a single byte of data. At this point, the device discontinues transmission.
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
RANDOM READ
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS(n)
∗
1 0 1 0 ∗ ∗ ∗
S
T
A
R
T
WA
6
WA
0
R A
/ C
W K
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 ∗ ∗ ∗
A
C
K
S
T
O
P
DATA(n)
D7
D0
A
C
K
R A
/ C
W K
Fig.18 RANDOM READ CYCLE TIMING
•Random read operation allows the master to access any memory location. This operation involves a two-step
process. First, the master issues a write command which includes the start condition and the slave address field (with
R / W set to “0”) followed by the address of the word to be read. This procedure sets the internal address counter of
the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV to the desired address. After the word address
acknowledge is received by the master, the master immediately reissues a start condition followed by the slave
address field with R / W the set to “1”. The device will respond with an acknowledge and then transmit the 8-data bits
stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop
condition, at this point BR24C21, BR24C21F, BR24C21FJ and BR24C21FV discontinue transmission.
SEQUENTIAL READ
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
1 0 1 0 ∗
R
E
A
D
∗ ∗
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
A
C
K
D0
A
C
K
Fig.19 SEQUENTIAL READ CYCLE TIMING
(Current Read)
•During the sequential read operation, the internal address counter of the BR24C21, BR24C21F, BR24C21FJ and
BR24C21FV automatically increments with each acknowledge received ensuring the data from address n will be
followed with the data from n+1. For read operations, all bits of the address counter are incremented allowing the
entire array to be read during a single operation. When the counter reaches the top of the array, it will “roll over” to the
bottom of the array and continue to transmit the data.
•The sequential read operation can be performed with both current read and random read.
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!External dimension (Units : mm)
9.3 ± 0.3
5
5.0 ± 0.2
0.11
5
1
4
1.27 0.4 ± 0.1
0.5 ± 0.1
0°~15°
SOP8
4.9 ± 0.2
3.0 ± 0.2
1.27
0.42 ± 0.1
1
4
0.22 ± 0.1
(0.52)
0.15 ± 0.1
6.4 ± 0.3
0.2 ± 0.1
0.45Min.
5
4.4 ± 0.2
3.9 ± 0.2
0.175
1 2 3 4
8
0.1
1.15 ± 0.1
2.54
0.15
8 7 6 5
6.0 ± 0.3
0.3Min.
0.3 ± 0.1
DIP8
1.375 ± 0.1
0.15 ± 0.1
7.62
1.5 ± 0.1
8
4.4 ± 0.2
4
0.51Min.
3.2 ± 0.2 3.4 ± 0.3
1
6.2 ± 0.3
6.5 ± 0.3
8
0.3Min.
0.65
0.1
0.1
SOP-J8
SSOP-B8
Appendix
Notes
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means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
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otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document use silicon as a basic material.
Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level of
reliability and the malfunction of with would directly endanger human life (such as medical instruments,
transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other
safety devices), please be sure to consult with our sales representative in advance.
About Export Control Order in Japan
Products described herein are the objects of controlled goods in Annex 1 (Item 16) of Export Trade Control
Order in Japan.
In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)
on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.
Appendix1-Rev1.0