EEPROM AS8E512K8 Austin Semiconductor, Inc. 512K x 8 EEPROM PIN ASSIGNMENT EEPROM Module (Top View) AVAILABLE AS MILITARY SPECIFICATIONS • • 32-Pin DIP & 32-Pin SOJ (CW) FEATURES • • • • • • • • Access times of 150, 200, 250, and 300 ns JEDEC Compatible Pinout 10,000 Write Endurance Cycles 10 year Data Retention Organized as 512Kx8 Operation with single 5 volt supply Low power CMOS TTL Compatible Inputs and Outputs OPTIONS • • • 1 32 Vcc A16 2 31 WE\ A15 3 30 A17 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 Vss 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 20 19 18 17 A14 A13 A8 A9 A11 OE\ A10 CE\ I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 A18 SMD 5962-93091 MIL-STD-883 MARKING Packaging 32 pin 600 MIL DIP CW Timing 150ns 200ns 250ns 300ns -150 -200 -250 -300 Operating Temperature Range -Military (-55oC to +125oC) -Industrial (-40oC to +85oC) No. 112 PIN DESCRIPTION A0 - A18 Address Inputs I/O 0 - I/O 7 Data Inputs/Outputs CE\ Chip Select OE\ Output Enable WE\ Write Enable Vcc +5.0V Power XT IT GENERAL DESCRIPTION A0 - A16 The Austin Semiconductor, Inc. AS8E512K8 is a 4 Megabit CMOS EEPROM Module organized as 512K x 8-bits. It is built with four 128K x 8 components and a single decoder. The AS8E512K8 achieves high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. Software data protection is implemented using the JEDEC Optional Standard algorithm. This military temperature grade product is ideally suited for military and space applications requiring high reliability. AS8E512K8 Rev. 3.1 6/05 I/O 0 - I/O 7 WE\ OE\ U1 A0 - A16 I/O 0 - I/O 7 U4 U3 A0 - A16 I/O 0 - I/O 7 A0 - A16 I/O 0 - I/O 7 WE\ WE\ WE\ WE\ OE\ OE\ OE\ OE\ CE\ A17 A18 CE\ U2 A0 - A16 I/O 0 - I/O 7 CE\ CE\ CE\ 1 of 4 Decoder For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 EEPROM Austin Semiconductor, Inc. AS8E512K8 DEVICE OPERATION: TOGGLE BIT: The AS8E512K8 is an electrically erasable and programmable memory module that is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA\ polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. In addition to DATA\ Polling the AS8E512K8 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O 6 toggling between one and zero. Once the write has completed, I/O 6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host power supply. The E2 module has incorporated both hardware and software features that will protect the memory against inadvertent writes. READ: HARDWARE PROTECTION: The AS8E512K8 is accessed like a Static RAM. When CE\ and OE\ are low and WE\ is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE\ or OE\ is high. This dual-line control gives designers flexibility in preventing bus contention in their system. Hardware features protect against inadvertent writes to the AS8E512K8 in the following ways: (a) Vcc sense - if Vcc is below 3.8V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8V the device will automatically time out 5ms (typical) before allowing a write; (c) write inhibit - holding any one of OE\ low, CE\ high or WE\ high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE\ or CE\ inputs will not initiate a write cycle. BYTE WRITE: A low pulse on the WE\ or CE\ input with CE\ or WE\ low (respectively) and OE\ high initiates a write cycle. The address is latched on the falling edge of CE\ or WE\, whichever occurs last. The data is latched by the first rising edge of CE\ or WE\. Once a byte, word or double word write has been started it will automatically time itself to completion. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on theAS8E512K8. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user and is shipped with SDP disabled, SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after tWC for each of the die the entire AS8E512K8 will be protected from inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AS8E512K8. This is done by preceding the data to be written by the same three byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AS8E512K8 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. PAGE WRITE: The page write operation of the AS8E512K8 allows 1 to 128 BWDWs of data to be written into the device during a single internal programming period. Each new BWDW must be written within 150us (tBLC) of the previous BWDW. If the tBLC limit is exceeded the AS8E512K8 will cease accepting data and commence the internal programming operation. For each WE\ high to low transition during the page write operation, A7-A18 must be the same. The A0-A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA\ POLLING: The AS8E512K8 features DATA\ Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O 7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA\ Polling may begin at anytime during the write cycle. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 EEPROM AS8E512K8 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Supply/Input Voltage Range1.........................-0.6V to +6.25V DC Voltage on OE\ and A9....................................-0.6V to +13.5V DC Voltage on all other pins..................................-0.6V to +6.25V DC Storage Temperature.............................................-65°C to +150°C Operating Temperature, TA (Ambient)................-55oC to +125oC Lead Temperature (soldering 10 seconds)........................+300oC Maximum Junction Temperature**....................................+165°C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. NOTE: 1. Including NC pins, with respect to ground. PIN CAPACITANCE (f= 1MHz, T = 25° C)(1) SYMBOL CONDITIONS MAX UNIT VIN = 0V, f = 1MHz 45 pF CI/O VOUT = 0V, f = 1MHz 50 pF CCE\ VIN = 0V, f = 1MHz 10 pF CADD, OE\, WE\ OPERATING MODES MODE CE\ OE\ WE\ I/O VIL VIL VIH DOUT VIL VIH VIL DIN VIH 1 X X High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X Read Write 2 Standby/Write Inhibit High Z NOTE: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC<TA<+125oC; Vcc = 5V +10%) PARAMETER Input Load Current Output Leakage Current Vcc Standby Current CMOS CONDITION SYMBOL MIN MAX UNITS VIN = OV to Vcc + 1V ILI -20 20 µΑ VI/O = OV to Vcc ILO -20 20 µΑ CE\ = Vcc -0.2V to Vcc + 1 ISB1 CE\ = 2.2V to Vcc + 1 ISB2 20 mA F = 5 MHz; IOUT = 0 mA ICC 120 mA Input Low Voltage VIL 0.8 V Input High Voltage VIH Vcc Standby Current TTL Vcc Active Current mA 2.0 V Output Low Voltage IOL = 2.1 mA VOL Output High Voltage IOH = -400 µA VOH1 2.4 V IOH = -100 µA; Vcc = 4.5V VOH2 4.2 V Output High Voltage CMOS AS8E512K8 Rev. 3.1 6/05 0.45 V Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 EEPROM AS8E512K8 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC READ OPERATING CONDITIONS (-55oC<TA<+125oC; Vcc = 5V +10%) !" # "" ! A.C. READ WAVEFORMS(1,2,3,4) ADDRESS ADDRESS VALID CE\ tCE tOE OE\ OUTPUT HIGH Z tOH tACC OUTPUT VALID NOTES: 1. CE\ may be delayed up to tACC-tCE after the address transition without inpact on tACC. 2. OE\ may be delayed up to tCE-tOE after the falling edge of CE\ without inpact on tCE or by tACC-tOE after an address change without inpact on tACC. 3. tDF is specified from OE\ or CE\ whichever occurs first (CL = 5pF). 4. This parameter is characterized and is not 100% tested. 5. A17 and A18 must remain valid through the WE\ and CE\ low pulse. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL FOR AC TEST CONDITIONS In p u t P u ls e L e v e ls In p u t R is e a n d F a ll T im e s In p u t a n d O u tp u t T im in g R e fe re n c e L e v e ls AS8E512K8 Rev. 3.1 6/05 tDF 0 V to 3 .0 V 5nS 1 .5 V OUTPUT TEST LOAD 5.0V 1.8K 1.3K 100pF Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 EEPROM AS8E512K8 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE OPERATING CONDITIONS (-55oC<TA<+125oC; Vcc = 5V +10%) SYMBOL PARAMETER tWC Write Cycle Time MIN tAS Address Set-up time tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns ns 5 tDH Data Hold Time 0 Write Pulse Width 100 tBLC Byte Load Cycle Time Write Pulse Width High OE\ UNITS 10 ms 10 tWP tWPH MAX ns ns 150 50 µs ns AC WRITE WAVEFORMS - WE\ CONTROLLED5 tOEH tOES ADDRESS CE\ WE\ tAS5 tCH tAH5 tCS tWPH tWP tDS tDH DATA IN AC WRITE WAVEFORMS - CE\ CONTROLLED5 OE\ tOEH tOES ADDRESS ?WE\ CE\ tAS5 tCH tAH5 tCS tWPH tWP tDS tDH DATA IN AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 EEPROM AS8E512K8 Austin Semiconductor, Inc. PAGE MODE CHARACTERISTICS PARAMETER SYMBOL MIN tAS, tOES 10 ns Address Hold Time tAH 50 ns Chip Select Setup Time tCS 0 ns Chip Select Hold Time tCH 0 ns Write Pulse Width (WE\ or CE\) tWP 100 ns Data Setup Time tDS 50 ns tDH, tOEH 10 ns Address, OE\ Setup Time Data, OE\ Hold Time MAX UNITS PAGE MODE WRITE WAVEFORMS(1,2,3) OE\ ?CE\ tBLC tWPH tWP WE\ tAS A0-A18 t AH VALID ADDR tDS DATA tDH VALID DATA BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 126 NOTES: 1. A7 through A16 must specify the page address during each high to low transition of ?W/E (or ?C/E). 2. ?O/E must be high only when ?W/E and ?C/E are both low. 3. A17 and A18 must remain valid throughout the WE\ and CE\ low. BYTE 127 tWC CHIP ERASE WAVEFORMS VIH CE\ VIL VH ?OE\ VIH NOTES: tS = 5µsec (min) tW= tH= 10 msec (min) VH=12.0 V +/- 0.5 V AS8E512K8 Rev. 3.1 6/05 ?WE\ tS VIH VIL tH tw Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 EEPROM AS8E512K8 Austin Semiconductor, Inc. SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1)(5) SOFTWARE DATA PROTECTION DISABLE ALGORITHM(1)(5) Load Data AA to Address 5555 Load Data AA to Address 5555 Load Data 55 to Address 2AAA Load Data 55 to Address 2AAA Load Data A0 to Address 5555 Load Data 80 to Address 5555 Writes Enabled(2) Load Data AA to Address 5555 Load Data XX to Any Address(4) Load Last Byte to Last Address Load Data 55 to Address 2AAA Enter Data Protect State Load Data 20 to Address 5555 Exit Data Protect State(3) Load Data XX to Any Address(4) Load Last Byte to Last Address NOTES: 1. Data Format: I/O 7 - I/O0 (Hex) 2. Write Protect state will be active at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded. 5. Applies to each of the 4 die in the module. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 EEPROM AS8E512K8 Austin Semiconductor, Inc. SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1,2,3,4) OE\ CE\ WE\ tWP tAS tAH A0-A6 BYTE ADDRESS 5555 2AAA 5555 A7-A18 PAGE ADDRESS tDH tDS DATA tBLC tWPH AA 55 A0 BYTE 0 BYTE 126 BYTE 127 t WC NOTES: 1. A0-A14 must conform to the addressing sequence for the first three bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7-A18) must be the same for each high to low transition of WE\ (or CE\). 3. OE\ Must be high only when WE\ and CE\ are both low. 4. A17 and A18 must remain valid throughout the WE\ and CE\ low cycle. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 EEPROM AS8E512K8 Austin Semiconductor, Inc. DATA POLLING CHARACTERISTICS(1) SYMBOL MIN Data Hold Time PARAMETER tDH 10 ns OE\ Hold Time tOEH 10 ns 2 tOE Write Recovery Time tWR OE\ to Output Delay MAX UNITS ns 0 ns NOTES: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. DATA POLLING WAVEFORMS WE\ CE\ tOEH OE\ t OE I/O7 A0-A18 AS8E512K8 Rev. 3.1 6/05 An tWR HIGH Z An An An An Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 EEPROM Austin Semiconductor, Inc. AS8E512K8 TOGGLE BIT CHARACTERISTICS(1) PARAMETER SYMBOL MIN Data Hold Time tDH 10 ns OE\ Hold Time tOEH 10 ns OE\ to Output Delay 2 MAX UNITS ns tOE OE\ High Pulse Write Recovery Time tOEHP 150 tWR 0 ns NOTES: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. TOGGLE BIT WAVEFORMS(1,2,3) WE\ CE\ t OEH ?OE\ t DH I/O6 t OE HIGH Z t WR NOTES: 1. Toggling either OE\ or CE\ or Both OE\ and CE\ will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 EEPROM AS8E512K8 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #112 (Package Designator CW) SMD 5962-93091, Case Outline Y D 32 17 A A1 D1 1 A2 16 e e1 D2 B B1 SMD Specifications SYMBOL A A1 A2 B B1 D D1 D2 e e1 MIN 0.161 0.027 MAX 0.181 0.047 0.125 MIN 0.009 0.590 1.654 0.580 1.492 0.012 0.610 1.686 0.600 1.508 0.100 TYP 0.016 0.02 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. *All measurements are in inches. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 EEPROM AS8E512K8 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS8E512K8CW-250/XT Device Number Package Type Speed ns Process AS8E512K8 CW -150 /* AS8E512K8 AS8E512K8 AS8E512K8 CW CW CW -200 -250 -300 /* /* /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range HQ = MIL-PRF-38534 AS8E512K8 Rev. 3.1 6/05 -40oC to +85oC -55oC to +125oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 EEPROM Austin Semiconductor, Inc. AS8E512K8 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator CW ASI Part # AS8E512K8CW-150/HQ AS8E512K8CW-150/HQ AS8E512K8CW-200/HQ AS8E512K8CW-200/HQ AS8E512K8CW-250/HQ AS8E512K8CW-250/HQ AS8E512K8CW-300/HQ AS8E512K8CW-300/HQ SMD Part # 5962-9309101HYC 5962-9309101HYA 5962-9309104HYC 5962-9309104HYA 5962-9309103HYC 5962-9309103HYA 5962-9309102HYC 5962-9309102HYA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13