ON MC74LCX244DTR2G Low−voltage cmos octal buffer with 5 v−tolerant inputs and outputs (3−state, non−inverting) Datasheet

MC74LCX244
Low−Voltage CMOS Octal
Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The MC74LCX244 is a high performance, non−inverting octal
buffer operating from a 2.3 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5 V allows MC74LCX244 inputs
to be safely driven from 5 V devices. The MC74LCX244 is suitable
for memory address driving and all TTL level bus oriented transceiver
applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE) input, when HIGH, disables the output by placing them in a
HIGH Z condition.
MARKING
DIAGRAMS
20
20
1
•
•
•
LCX244
AWLYYWWG
1
20
Features
•
•
•
•
•
•
•
•
SOIC−20
DW SUFFIX
CASE 751D
Designed for 2.3 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available
20
1
LCX
244
ALYW G
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
20
1
SOEIAJ−20
M SUFFIX
CASE 967
1
74LCX244
AWLYWWG
A
= Assembly Location
L, WL = Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 7
1
Publication Order Number:
MC74LCX244/D
MC74LCX244
VCC
2OE
1O0
2D0
1O1
2D1
1O2
2D2
1O3
2D3
20
19
18
17
16
15
14
13
12
11
1OE
1D0
1D1
1
2
3
4
5
6
7
8
9
10
1OE
1D0
2O0
1D1
2O1
1D2
2O2
1D3
2O3
GND
1D2
1D3
1
2
18
4
16
6
14
8
12
1O0
1O1
1O2
1O3
Figure 1. Pinout: 20−Lead (Top View)
PIN NAMES
2OE
PINS
FUNCTION
nOE
1Dn, 2Dn
1On, 2On
Output Enable Inputs
Data Inputs
3−State Outputs
2D0
2D1
2D2
19
17
3
15
5
13
7
11
9
2O0
2O1
2O2
TRUTH TABLE
INPUTS
OUTPUTS
1OE
2OE
1Dn
2Dn
1On, 2On
L
L
L
L
H
H
H
X
Z
2D3
2O3
Figure 2. Logic Diagram
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For ICC reasons, DO NOT FLOAT Inputs
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2
MC74LCX244
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
VO
Value
Condition
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
V
DC Output Voltage
−0.5 ≤ VO ≤ +7.0
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State (Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Operating
Data Retention Only
(HIGH or LOW State)
(3−State)
Min
Typ
Max
Unit
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
−24
−12
mA
IOL
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
24
12
mA
−40
+85
°C
0
10
ns/V
TA
Operating Free−Air Temperature
Dt/DV
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V,
VCC = 3.0 V
ORDERING INFORMATION
Device
Package
MC74LCX244DW
SOIC−20
MC74LCX244DWG
SOIC−20
(Pb−Free)
MC74LCX244DWR2
SOIC−20
MC74LCX244DWR2G
SOIC−20
(Pb−Free)
MC74LCX244DT
TSSOP−20*
MC74LCX244DTG
TSSOP−20*
MC74LCX244DTR2
TSSOP−20*
MC74LCX244DTR2G
TSSOP−20*
MC74LCX244MELG
SOEIAJ−20
(Pb−Free)
Shipping †
38 Units / Rail
1000 / Tape & Reel
75 Units / Rail
2500 / Tape & Reel
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74LCX244
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
Characteristic
VIH
HIGH Level Input Voltage (Note 2)
VIL
LOW Level Input Voltage (Note 2)
VOH
HIGH Level Output Voltage
Condition
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
Max
V
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V ≤ VCC ≤ 3.6 V
VOL
LOW Level Output Voltage
Unit
V
0.8
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
VCC − 0.2
VCC = 2.3 V; IOH = −8 mA
1.8
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
VCC = 2.3 V; IOL= 8 mA
0.6
VCC = 2.7 V; IOL= 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
V
VCC = 3.0 V; IOL = 24 mA
0.55
II
Input Leakage Current
2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5
mA
IOZ
3−State Output Current
2.3 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V;
VI = VIH or V IL
±5
mA
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
mA
ICC
Quiescent Supply Current
mA
DICC
2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
500
Increase in ICC per Input
mA
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS (tR = tF = 2.5 ns; RL = 500 W)
Limits
TA = −40°C to +85°C
Symbol
Parameter
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
VCC = 2.5 V +0.2
CL = 50 pF
CL = 50 pF
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Input to Output
1
1.5
1.5
6.5
6.5
1.5
1.5
7.5
7.5
1.5
1.5
7.8
7.8
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
8.0
8.0
1.5
1.5
9.0
9.0
1.5
1.5
10
10
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
7.0
7.0
1.5
1.5
8.0
8.0
1.5
1.5
8.4
8.4
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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4
MC74LCX244
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage (Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
8
pF
CPD
Power Dissipation Capacitance
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
25
pF
VCC
Vmi
1Dn, 2Dn
Vmi
0V
tPLH
tPHL
Vmo
1On, 2On
VOH
Vmo
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
Vmi
1OE, 2OE
Vmi
0V
tPZH
tPHZ
VCC
VOH − 0.3 V
Vmo
1On, 2On
≈0V
tPZL
tPLZ
≈ 3.0 V
Vmo
1On, 2On
VOL + 0.3 V
GND
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
VCC
3.3 V ± 0.3 V
2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
Symbol
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5
2.5 V ± 0.2 V
MC74LCX244
VCC
PULSE
GENERATOR
R1
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 0.3 V
6 V at VCC = 2.5 0.2 V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
CL =
CL =
RL =
RT =
GND
50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)
30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)
R1 = 500 W or equivalent
ZOUT of pulse generator (typically 50 W)
Figure 4. Test Circuit
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6
6V
OPEN
GND
MC74LCX244
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74LCX244
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74LCX244
PACKAGE DIMENSIONS
SOEIAJ−20
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your local
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MC74LCX244/D
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