Freescale Semiconductor Technical Data MC34710 Rev. 3.0, 3/2006 Document order number: Dual Output DC-DC & Linear Regulator IC The 34710 is a dual-output power regulator IC integrating switching regulator, linear regulator, supervisory and power supply sequencing circuitry. With a wide operating input voltage range of 13 V to 32 V, the 34710 is applicable to many commercial and industrial applications using embedded MCUs. 33710 34710 DUAL OUTPUT DC-DC & LINEAR REGULATOR A mode-selected 5.0 V or 3.3 V DC-DC switching regulator is provided for board-level I/O and user circuitry up to 700 mA. A linear regulator provides mode-selected core supply voltages of either 3.3V, 2.5V, 1.8V, or 1.5V at currents up to 500 mA. The supervisor circuitry ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Features • Efficient 5.0 V / 3.3 V Buck Regulator • Low Noise LDO Regulator (mode-selected 3.3V, 2.5V,1.8V, or 1.5V) • On-Chip Thermal Shutdown Circuitry • Supervisory Functions (Power-ON Reset and Error Reset Circuitry) • Sequenced I/O and Core Voltages • Pb-Free Packaging Designated by Suffix Code EW DW SUFFIX EW SUFFIX (PB-FREE) 98ASA10627D 32-TERMINAL SOICW ORDERING INFORMATION Device Temperature Range (TA) Package *PC33710EW / R2 -40°C to 105° 32 SOICW-EP MC34710EW/R2 0°C to 85°C 32 SOICW-EP *Device in development. Electrical parameters being defined. VI/O 13 V to 32 V 34710 B+ VB CT VSWITCH CP2 VI/O VFB CP1 MCU MODE0 MODE1 MODE2 RST LINB+ VCORE GND VCORE Figure 1. 34710 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM B+ 200 kHz Oscillator CP1 CP2 Charge Pump VB Supervisory and Temperature Shutdown RST CT Bandgap MODE0 MODE1 MODE2 LINB+ VI/O Switching Regulator VFB VSWITCH VCORE Linear Regulator VCORE GND Figure 2. 34710 Simplified Internal Block Diagram 34710 2 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS RST MODE0 MODE1 MODE2 N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 CT CP1 CP2 VB B+ VSWITCH VFB LINB+ N/C VCORE N/C N/C N/C N/C N/C N/C Figure 3. 34710 Terminal Connections Table 1. 34710 Terminal Definitions Terminal Number Terminal Name Terminal Function Formal Name 1 RST Reset Reset 2 3 4 Mode0 Mode1 Mode2 Input Mode Control These input terminals control VFB and VCORE output voltages. 5 – 12, 14 –22, 24 NC NC No Connects No internal connection to this terminal. 13 GND Ground Ground 23 VCORE Output Core Voltage Regulator Output 25 LINB+ Input Core Voltage Regulator Input Core regulator input voltage. 26 VFB Input VI/O Switching Regulator Feedback Feedback terminal for VI/O switching regulator and internal logic supply. 27 VSWITCH Output VI/O Switching Regulator Switch Output 28 B+ Input Power Supply Input Regulator input voltage. 29 VB Output Boost Voltage Boost voltage storage node. 30 CP2 Passive Component CP Capacitor Positive Charge pump capacitor connection 2. 31 CP1 Passive Component CP Capacitor Negative Charge pump capacitor connection 1. 32 CT Passive Component Reset Delay Capacitor Reset delay adjustment capacitor. Definition Reset is an open drain output only. Ground. Core regulator output voltage. VI/O switching regulator switching output. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 3 MAXIMUM RATINGS MAXIMUM RATINGS MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Max Unit ELECTRICAL RATINGS VB+ Input Power Supply Voltage V -0.3 to 36 IB+ = 0.0 A Terminal Soldering Temperature (1) Power Dissipation (2) TSOLDER 260 °C PD 3.0 W VESD1 ±2000 RθJA 45 V ESD Standoff Voltage Non-Operating, Unbiased, Human Body Model (3) °C/W Thermal Resistance Junction-to-Ambient (4) RθJA 25 RθJC 2.0 Operating Ambient Temperature TA 0 to 85 °C Operating Junction Temperature TJ 0 to 105 °C Junction-to-Ambient (2) Junction-to-Exposed-Pad THERMAL RATINGS VB+ Input Power Supply Voltage V 13 to 32 IB+ = 0.0 A to 3.0 A IB+(Q) Quiescent Bias Current from B+ (5) mA 7.5 VB+ = 13 V to 32 V VI /O SWITCHING REGULATOR (6) Maximum Output Voltage Startup Overshoot (COUT = 330 µF) VI / O(STARTUP) Mode0 = 0 3.6 Mode0 = Open Maximum Output Current TA = 0°C to 105°C V 5.4 IVI/O mA 700 Notes 1. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. 3. With 2.0 in2 of copper heatsink. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 4. 5. 6. With no additional heatsinking. Maximum quiescent power dissipation is 0.25 W. 13 V ≤ VB+ ≤ 32 V and - 20°C ≤ TJ ≤ 145°C unless otherwise noted. 34710 4 Analog Integrated Circuit Device Data Freescale Semiconductor MAXIMUM RATINGS MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Max Unit VCORE LINEAR REGULATOR (7) Maximum Output Voltage Startup Overshoot (COUT = 10 µF) (8) VCORE (STARTUP) Mode2=Low, Mode1=Low, Mode0=Low 2.7 Mode2=Open, Mode1=Low, Mode0=Don’t Care 2.0 Mode2=Low, Mode1=Open, Mode0=Don’t Care 1.65 Mode2=Open, Mode1=Open, Mode0=Don’t Care Maximum Output Current TJ = 0°C to 105°C, VLINB+ ≤ VCORE (NOM) + 0.8 V (9) V 3.6 IVCORE mA 500 Notes 7. 13 V ≤ VB+ ≤ 32 V and - 20°C ≤ TJ ≤ 145°C unless otherwise noted. 8. 9. Refer to Table 2, page 9. Pulse testing with low duty cycle used. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 4.8 5.0 5.2 3.15 3.25 3.45 Unit SWITCHING REGULATOR (VI/O, MODE0) Logic Supply Voltage (IVI/O = 25 to 700 mA) VI / O Mode0 = 0 Mode0 = Open (floating) Output On Resistance RDS(ON) Ω 0.5 VB+ = 13 V to 32 V Soft Start Threshold Voltage V 1.0 2.0 VI / O(SOFT) V – 2.5 3.1 ILIMIT (OP) 1.9 2.4 2.9 ILIMIT (SOFT) 1.0 – 1.9 -0.5 – – 3.15 3.3 3.45 2.45 2.5 2.75 1.7 1.8 2.05 1.425 1.5 1.575 3.0 – 3.4 2.2 – 2.6 Mode2=Open, Mode1=Don’t Care, Mode0=Low 1.55 – 1.9 Mode2=Open, Mode1=Don’t Care, Mode0=Open 1.33 – 1.53 – 0.5 0.8 Mode0 = any Current Limit Threshold (TJ = 25°C to 100°C) Normal Operation Soft Start, VI / O ≤ 2.5 V Minimum Voltage Allowable on VSWITCH Terminal A VVSWITCH (MIN) TJ = 25°C to 100°C V LINEAR REGULATOR (VCORE, MODE 1, 2, 3, 4) Supply Voltage (IVCORE = 5.0 mA) (10) VCORE (NOM) Mode2=Low, Mode1=Don’t Care, Mode0=Low Mode2=Low, Mode1=Don’t Care, Mode0=Open Mode2=Open, Mode1=Don’t Care, Mode0=Low Mode2=Open, Mode1=Don’t Care, Mode0=Open Supply Voltage (IVCORE = 500 mA) (10) Mode2=Low, Mode1=Don’t Care, Mode0=Open IVCORE(DROPOUT) VCORE = VCORE (NOM), IVCORE = 0.5 A Normal Current Limit Threshold TJ = 25°C to 100°C, VLINB+ = VCORE (NOM) + 1.0 V V VCORE (NOM) Mode2=Low, Mode1=Don’t Care, Mode0=Low VCORE Dropout Voltage V V ILIMIT mA 600 800 1000 Notes 10. Refer to Table 2, page 9. 34710 6 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit – – 0.825 2.6 – – 7.0 8.0 13 VB+ (MIN) – – 9.0 V VB+(ASSERT) – 1.9 2.2 V – 0.25 0.4 – – VI/O(NOM) MODE TERMINALS OPERATING VOLTAGES Mode Control Terminals Low Voltage Mode Control Terminals High Voltage Mode Control Terminals Voltage with Input Floating VIL(Moden) V VIH (Moden) V VMode(FLOAT) VB+ = 13 V to 14 V V SUPERVISOR CIRCUITRY (RST, VCORE) Minimum Function VB+ for Charge Pump and Oscillator Running Minimum VB+ for RST Assertion, VB+ Rising RST Low Voltage VOL VB+ = 2.0 V, IRST ≤ 5.0 mA V RST VI / O Threshold VI / O Rising VI / OT+ VI / O Falling VI / OT- VI/O (NOM) - 300 mV – – VHYSVI/O 10 – 100 VCORE Rising VCORET+ – – VCORE (NOM) VCORE Falling VCORET- – – RST Hysteresis for VI / O RST VCORE Threshold RST Hysteresis for VCORE TJ (TSD) Overtemperature Hysteresis V mV 10 50 100 0.5 – 0.9 V °C – – 170 TJ (HYSTERESIS) – 20 – VB VB+ 8 VB+ 9 VB+ 10 VB VB+ 10 VB+ 12 VB+ 14 TJ Rising mV - 30 mV VCORE (SHUTDOWN) VB+ = 13 V to 32 V Thermal Shutdown Temperature - 300 mV - 50 mV VHYS CORE VB+ = 13 V to 32 V VCORE - VI / O for VCORE Shutdown VCORE (NOM) V °C VB CHARGE PUMP Boost Voltage (11) VB+ = 12 V, Ivb = 0.5 mA VB+ = 32 V, Ivb = 0.5 mA V Notes 11. Bulk capacitor ESR ≤ 10 milliohms 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 7 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted Characteristic Symbol Min Typ Max Unit D 45 49 55 % 20 35 50 VI /O SWITCHING REGULATOR Duty Cycle Switching Rise and Fall Time t R , tF Load Resistance = 100 Ω, VB+ = 30 V ns SUPERVISOR CIRCUITRY (RST) RST Delay t DELAY 40 60 80 2.0 4.0 8.0 – 25 75 ICDLY 2.0 3.5 5.0 µA VTHCD 1.7 2.0 2.2 V 140 170 260 Cdelay = 0.1 µF RST Filter Time t FILTER VB+ = 9.0 V RST Fall Time ms tF CL = 100 pF, RPULLUP = 4.7 kΩ, 90% to 10% µs ns C Delay Charge Current Threshold Voltage INTERNAL OSCILLATOR Charge Pump and VI / O Switching Regulator Operating Frequency VB+ = 12 V to 32 V f OP kHz 34710 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION VI /O Switching Regulator The VI /O switching regulator output voltage is determined by the Mode digital input terminals. The 34710’s Mode terminals select the output voltage. For example, if Mode2, Mode1, and Mode0 are set to 0, 0, 0 (respectively) then VI /O will be set to 5.0 V; if Mode2, Mode1, and Mode0 are all left floating (i.e., Open, Open, and Open), then the voltage for VI /O will be set to 3.3 V. Table 2 provides the truth table for setting the various combination of regulator outputs via the Mode pins. The topology of the regulator is a hysteretic buck regulator operating from the internal ~200 kHz oscillator. VCORE Linear Regulator The VCORE linear LDO (low drop-out) regulator can produce either a +3.3 V, 2.5 V, 1.8 V, or 1.5 V output voltage at currents up to 500 mA. The input to the VCORE regulator is a terminal that may be connected to the VI /O regulator output or to an external power supply. Note, the minimum input voltage level must be equal to or greater than the selected VCORE voltage + 0.8 V. (I.e., 0.8V is the LDO regulator drop out voltage.) The Mode terminals select the output voltage as depicted in Table 2. Table 2. VI /O and VCORE Regulator Output Voltage Selection Mode2 Mode1 Mode0 VI /O (V) VCORE (V) 0 0 0 5.0 3.3 0 0 Open 3.3 2.5 0 Open 0 5.0 1.8 0 Open Open 3.3 1.8 Open 0 0 5.0 2.5 Open 0 Open 3.3 2.5 Open Open 0 5.0 1.5 Open Open Open 3.3 1.5 Open indicates terminal is not connected externally (i.e. floating). FUNCTIONAL TERMINAL DESCRIPTION Power Supply Input (B+) Main supply voltage for the VI/O Switching Regulator and general chip bias circuitry. Core Voltage Regulator Input (Lin B+) Supply voltage for the VCORE Regulator. May be provided by the VI/O regulator output or from an independent supply. Mode Control (MODE 0,1,2) Mode select terminals to select the VI/O and VCORE output voltages per table 2. Pull to ground for low state, float for high state. Switching Capacitors 1 and 2 (CP1/CP2) Terminals for the Charge Pump capacitor. Boost Voltage (VB) The Boost Voltage is an output terminal used for the charge pump boost voltage and is a connection point for the Charge Pump bulk capacitor.It provides a gate drive for the VI/O Switch FET. Reset (RST) during fault conditions. This terminal has no input function and requires an external pull-up resistor. The RST terminal is an open drain output driver to prevent oscillations during the transition. It is recommended to connect a 0.1 uF capacitor between the CT pin and RST pin. Note: error conditions must be present for a minimum time, tFILTER, before the 34710 responds to them. Once all error conditions have been cleared, RST is held low for an additional time of tDELAY. Reset Delay Capacitor (CT) This terminal is the external delay. It is used with a capacitor to ground to delay RST turn-on time and to RST to prevent RST oscillations during chip power-on. VI/O Switching Regulator Feedback (VFB) This terminal is the feedback input for the VI/O Switching Regulator and the output of the regulator application. VI/O Switching Regulator output (VSWITCH) This terminal is the Switching output for the VI/O Buck Regulator. It has internal high side FET. Reset is an output terminal for supervisory functions. This terminal is in high state during normal operation and low state 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION SUPERVISORY FUNCTIONS Supervisory Circuitry The supervisory circuitry provides control of the RST line, an open drain signal, based on system operating conditions monitored by the 34710. VI /O, VCORE, VB+, and thermal shutdown (TSD) detectors in various parts of the chip are monitored for error conditions. VI /O, VCORE, VB+, and thermal shutdown have both positive- and negative-going thresholds for triggering the reset function. The supervisor circuitry also ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Specifically, the sequencing ensures that VI /O is never less than 0.9 V below VCORE. This means that VCORE VI /O will be clamped at 0.5 V, and that the VCORE regulator operation will be suppressed during startup and shutdown to ensure that VCORE - VI /O = 0.9 V. VB Charge Pump The high-side MOSFET in the switching regulator (buck converter) requires a gate drive supply voltage that is biased higher than the B+ voltage, and this boosted voltage is provided by the internal charge pump and stored in a capacitor between the VB pin and the B+ pin. The charge pump operates directly from the B+ supply, and uses an internal oscillator operating at 200 kHz. Internal Oscillator The internal oscillator provides a 200 kHz square wave signal for charge pump operation and for the buck converter. 34710 10 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS B+ 13 V - 32 V C1 330 µF R1 1K SW1 C1 0.1 mF 1 RST 2 MODE0 3 MODE1 4 MODE2 SUPERVISORY & SHUTDOWN 13 GND CT 32 31 CHARGE CP1 30 PUMP CP2 VB 29 28 B+ BUCK 27 REG VSW 26 VFB 25 LINB 24 LDO 23 VCORE C5 0.1 µF C6 10 µF RSERIES 1.8 MC34710 L1 100 µH D1 MBRS130LT3 C8 330 µF 1 2 V I/O VCORE Figure 4. Typical Application Diagram The MC34710 provides both a buck converter and an LDO regulator in one IC. Figure 4 above shows a typical application schematic for the MC34710. L1 is the buck converter's inductor. The buck inductor is a key component and must not only present the required reactance, but do so at a dc resistance of less than 20 milliohms in order to preserve the converter's efficiency. Also important to the converter's efficiency is the utilization of a low Vf Schottky diode for D1. Note that a 0.1uF capacitor is connected between CT and the reset pins; this prevents any possibility of oscillations occurring on the reset line during transitions by allowing the CT terminal to discharge to ground potential via the RST pin, and then charge when RST returns to a logic high. The capacitor between the CP1 and CP2 pins is the charge pump's “bucket capacitor”, and sequentially charges and discharges to pump up the reservoir capacitor connected to the VB pin. Note that the reservoir capacitor's cathode is connected to B+ rather than ground. Also note that the charge pump is intended only to provide gate-drive potential for the buck regulator's internal power MOSFET, and therefore connecting external loads to the VB pin is not recommended. The IC's internal VCORE LDO regulator can provide up to 500 mA of current as long as the operating junction temperature is maintained below 105 degrees C. The heatgenerating power dissipation of the LDO is primarily a function of the Volt x Amp product across the LINB+ and VCORE terminals. Therefore, if the LINB+ voltage is >> than the selected VCORE voltage + 0.8 V, it is recommended to use a power resistor in series with the LINB+ input to drop the voltage and dissipate the heat externally from the IC. For example, if the output of the buck regulator (V I/O on the schematic) is used as the input to LINB+, and the mode switches are set such that V I/O = 5 V and VCORE = 3.3 V, then a series resistance of 1.8 ohms at the LINB+ pin would provide an external voltage drop at 500 mA while still leaving the minimum required headroom of 0.8 V. Conversely, if the mode switches are set such that V I/O = 3.3 V and VCORE = 2.5 V, then no series resistance would be required, even at the maximum output current of 500 mA. Designing a power supply circuit with the MC34710, like all dc-dc converter ICs, requires special attention not only to component selection, but also to component placement (i.e., printed circuit board layout). The MC34710 has a nominal switching frequency of 200 kHz, and therefore pcb traces between the buck converter discrete component terminals and the IC should be kept as short and wide as possible to keep the parasitic inductance low. Likewise, keeping these 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 11 TYPICAL APPLICATIONS pcb traces short and wide helps prevent the converter's high di/dt switching transients from causing EMI/RFI. possible. The square vias in the plane are located to provide an immediate path to ground from the top copper circuitry. Figure 5. Typical PCB Layout Figure 5 shows a typical layout for the pcb traces connecting the IC's switching terminal (VSWITCH) and the power inductor, rectifier, and filter components. Also, it is recommended to design the component layout so that the switching currents can be immediately sunk into a broad full-plane ground that provides terminations physically right at the corresponding component leads. This helps prevent switching noise from propagating into other sections of the circuitry. Figure 6. Bottom Copper Layout Figure 6 illustrates a pcb typical bottom copper layout for the area underneath a buck converter populated on the top of the same section of pcb. The ground plane is highlighted so the reader may note how the ground plane has been kept as broad and wide as Figure 7. Top Copper Layout Figure 7 shows the corresponding top copper circuit area with the component placement. Again, the ground plane and the vias have been highlighted so the reader may note the proximity of these current sink pathways to the key converter components. It is also important to keep the power planes of the switching converter's output spread as broad as possible beneath the passive components, as this helps reduce EMI/RFI and the potential for coupling noise transients into adjacent circuitry. Figure 8. Output Plane of Buck Converter Figure 8 shows the output plane of the buck converter highlighted. 34710 12 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS This layout provides the lowest possible impedance as well as lowest possible dc resistance for the power routing. Note that the power path and its return should be placed, if possible, on top of each other on different layers or opposite sides of the pcb. Small ceramic capacitors are placed in parallel with the Aluminum electrolytics so that the overall bulk filtering presents a low ESL to the high di/dt switching currents. Alternatively, special low ESL/ESR switching-grade electrolytics may be used. An additional feature of the MC34710 is the 32 SOICW-EP exposed pad package. The package allows heat to be conducted from the die down through the exposed metal pad underneath the package and into the copper of the pcb. In order to best take advantage of this feature, a grid array of thru-hole vias should be placed in the area corresponding to the exposed pad, and these vias then should then connect to a large ground plane of copper to dissipate the heat into the ambient environment. An example of these vias can be seen in the previous figures of a typical pcb layout. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 13 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD PLASTIC PACKAGE 98ASA10627D ISSUE O 34710 14 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD PLASTIC PACKAGE 98ASA10627D ISSUE O 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 15 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 2.0 3/2006 • • • • • Converted to Freescale format Updated Maximum Ratings, Static and Dynamic Characteristics tables. Updated packaging drawing Changed terminal VI/O_OUT to VFB Implemented Revision History page 3.0 3/2006 • • Updated format from Preliminary to Advance Information. Format and style corrections to match standard template. 34710 16 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 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