Cypress CY7C1062DV33 16-mbit (512k x 32) static ram Datasheet

CY7C1062DV33
PRELIMINARY
16-Mbit (512K X 32) Static RAM
Features
Functional Description
• High speed
The CY7C1062DV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
— tAA = 10 ns
Writing to the device is accomplished by enabling the chip
(CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (BA) is LOW, then data from I/O
pins (I/O0 through I/O7), is written into the location specified on
the address pins (A0 through A18). If Byte Enable B (BB) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23
and I/O24 to I/O31, respectively.
• Low active power
— ICC = 150 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
Reading from the device is accomplished by enabling the chip
(CE1, CE2, and CE3 LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (BA) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
Enable B (BB) is LOW, then data from memory will appear on
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3
features
• Available in Pb-free 119-ball plastic ball grid array
(PBGA) package
The input/output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1,
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (BA-D HIGH), or during a write
operation (CE1, CE2, and CE3 LOW, and WE LOW).
The CY7C1062DV33 is available in 119-ball plastic ball grid
array (PBGA) package.
WE
CE1
CE2
CE3
OE
BA
BB
BC
BD
OUTPUT BUFFERS
512K x 32
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFERS
CONTROL LOGIC
Logic Block Diagram
I/O0–I/O31
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
COLUMN
DECODER
Cypress Semiconductor Corporation
Document #: 38-05477 Rev.*C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 4, 2006
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CY7C1062DV33
PRELIMINARY
Selection Guide
–10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
150
mA
Maximum CMOS Standby Current
25
mA
Pin Configuration[1]
119-ball PBGA
(Top View)
1
2
3
4
5
6
7
A
I/O16
A
A
A
A
A
I/O0
B
C
D
E
F
G
H
J
K
L
M
N
P
I/O17
I/O18
I/O19
A
Bc
VDD
A
CE2
VSS
CE1
NC
VSS
A
CE3
VSS
A
Ba
VDD
I/O1
I/O2
I/O3
I/O20
VSS
VDD
VSS
VDD
VSS
I/O4
I/O21
VDD
VSS
VSS
VSS
VDD
I/O5
I/O22
VSS
VDD
VSS
VDD
VSS
I/O6
I/O23
NC
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O7
NC
I/O24
I/O25
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O8
I/O9
VDD
VSS
VSS
VSS
VDD
I/O10
I/O27
VSS
VDD
VSS
VDD
VSS
I/O11
I/O28
VDD
VSS
VSS
VSS
VDD
I/O12
I/O29
A
Bd
NC
Bb
A
I/O13
I/O30
A
A
WE
A
A
I/O14
I/O31
A
A
OE
A
A
I/O15
R
T
U
I/O26
Note:
1. NC pins are not connected on the die
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
DC Input Voltage[2] ................................–0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage ............................................>2001V
Storage Temperature ..................................–65°C to +150°C
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .............................................–55°C to +125°C
Latch-up Current......................................................>200 mA
Supply Voltage on VCC Relative to GND[2] ..... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[2] ................................... –0.5V to VCC + 0.5V
Operating Range
Ambient
Temperature
VCC
–40°C to +85°C
3.3V ± 0.3V
Range
Industrial
DC Electrical Characteristics Over the Operating Range
–10
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
[7]
Min.
Max.
Unit
2.4
V
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[2]
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply Current
VCC = Max., f = fMAX = 1/tRC
IOUT = 0 mA CMOS levels
150
mA
ISB1
Automatic CE Power-down
Current —TTL Inputs
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30
mA
ISB2
Automatic CE Power-down
Current —CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
25
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
pF
10
pF
Thermal Resistance[3]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance (Junction to Ambient)
ΘJC
Thermal Resistance (Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
All - Packages
Unit
TBD
°C/W
TBD
°C/W
AC Test Loads and Waveforms[4]
50Ω
3.3V
VTH = 1.5V
OUTPUT
Z0 = 50Ω
OUTPUT
30 pF*
All input pulses
(a)
*Capacitive Load consists of all
components of the test environment
R1 317 Ω
3.0V
GND
90%
10%
90%
10%
Rise time > 1V/ns
(c)
Fall time:
> 1V/ns
R2
351Ω
5 pF*
*Including
jig and
scope
(b)
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum
operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
AC Switching Characteristics Over the Operating Range[5]
–10
Parameter
Description
Min.
Max.
Unit
Read Cycle
tpower
VCC (typical) to the first access[6]
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE active LOW to Data Valid[7]
10
ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low-Z
[8]
OE HIGH to High-Z
CE active LOW to Low-Z[7, 8]
tHZCE
CE deselect HIGH to
tPU
CE active LOW to
CE deselect HIGH to
Byte Enable to Data Valid
tHZBE
Byte Enable to
Low-Z[8]
Byte Disable to
High-Z[8]
ns
ns
5
0
Power-down[7, 9]
tDBE
tLZBE
5
Power-up[7, 9]
tPD
ns
3
High-Z[7, 8]
ns
ns
1
tLZCE
tWC
3
[8]
tHZOE
Write
10
ns
ns
10
ns
5
ns
1
ns
5
ns
Cycle[10, 11]
Write Cycle Time
End[7]
10
ns
7
ns
7
ns
tSCE
CE active LOW LOW to Write
tAW
Address Set-up to Write End
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5.5
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low-Z[8]
3
ns
tHZWE
WE LOW to High-Z
[8]
tBW
Byte Enable to End of Write
5
7
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in (a) of AC Test Loads, unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 and CE2 and CE3 LOW. When deselect HIGH, CE indicates the
CE1 or CE2 or CE3 HIGH
8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±
200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. The chip enables must be active and WE must
be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data Retention Time
tR[12]
Operation Recovery Time
Min.
Typ.
Max.
Unit
2
V
VCC = 2V , CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
25
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3V
VCC
3V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[13,14]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 15, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BA, BB, BC, BD
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tHZBE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
IICC
CC
50%
ISB
Notes:
12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs
13. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16, 17]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BA, BB, BC , BD
tSD
tHD
DATAI/O
Write Cycle No. 2 (BA, BB, BC, BD Controlled)[15, 16, 17]
tWC
ADDRESS
tSA
tBW
BA, BB, BC , BD
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Notes:
16. Data I/O is high-impedance if OE or BA, BB, BC, BD = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BA, BB, BC, BD
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05477 Rev.*C
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CY7C1062DV33
PRELIMINARY
Truth Table
CE1 CE2 CE3
OE
WE
BA
BB
Bc
BD
I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 I/O24–I/O31
Mode
Power
H
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down (ISB)
X
H
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down (ISB)
X
X
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Power Down (ISB)
L
L
L
L
H
L
L
L
L
Data Out
Data Out
Data Out
Data Out
Read All Bits (ICC)
L
L
L
L
H
L
H
H
H
Data Out
High-Z
High-Z
High-Z
Read Byte A (ICC)
Bits Only
L
L
L
L
H
H
L
H
H
High-Z
Data Out
High-Z
High-Z
Read Byte B (ICC)
Bits Only
L
L
L
L
H
H
H
L
H
High-Z
High-Z
Data Out
High-Z
Read Byte C (ICC)
Bits Only
L
L
L
L
H
H
H
H
L
High-Z
High-Z
High-Z
Data Out
Read Byte D (ICC)
Bits Only
L
L
L
X
L
L
L
L
L
Data In
Data In
Data In
Data In
Write All Bits (ICC)
L
L
L
X
L
L
H
H
H
Data In
High-Z
High-Z
High-Z
Write Byte A (ICC)
Bits Only
L
L
L
X
L
H
L
H
H
High-Z
Data In
High-Z
High-Z
Write Byte B (ICC)
Bits Only
L
L
L
X
L
H
H
L
H
High-Z
High-Z
Data In
High-Z
Write Byte C (ICC)
Bits Only
L
L
L
X
L
H
H
H
L
High-Z
High-Z
High-Z
Data In
Write Byte D (ICC)
Bits Only
L
L
L
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Selected,
Outputs
Disabled
(ICC)
L
L
L
X
X
H
H
H
H
High-Z
High-Z
High-Z
High-Z
Selected,
Outputs
Disabled
(ICC)
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
10
CY7C1062DV33-10BGXI
51-85115
119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free)
Industrial
Document #: 38-05477 Rev.*C
Page 8 of 10
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PRELIMINARY
CY7C1062DV33
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders
Document #: 38-05477 Rev.*C
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1062DV33
Document History
Document Title: CY7C1062DV33 16-Mbit (512K X 32) Static RAM
Document Number: 38-05477
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
201560
See ECN
SWI
Advance Data sheet for C9 IPP
*A
233748
See ECN
RKF
1.AC, DC parameters are modified as per EROS (Spec # 01-2165)
2.Pb-free offering in the ‘ordering information’
*B
469420
See ECN
NXR
Converted from Advance Information to Preliminary
Removed –8 and –12 speed bins from product offering
Removed Commercial operating Range
Changed J7 ball of PBGA from DNU to NC in the pinout diagram
Included the Maximum ratings for Static Discharge Voltage and Latch Up Current
on page #3
Changed ICC(Max) from 220 mA to 150 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot spec in footnote # 1
Changed tSD from 5.5 ns to 5 ns
Added Data Retention Characteristics table and waveform on page # 5.
Updated the 48-pin FBGA package
Updated the Ordering Information Table
*C
499604
See ECN
NXR
Added note# 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics
Table on page# 4
Document #: 38-05477 Rev.*C
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