Fairchild FSEZ1216 Primary-side-regulation pwm integrated power mosfet Datasheet

FSEZ1216 — Primary-Side-Regulation PWM Integrated
Power MOSFET
Features
Description
ƒ
Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
ƒ
ƒ
Green Mode: Frequency Reduction at Light-Load
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Cable Voltage Drop Compensation in CV Mode
The primary-side PWM integrated Power MOSFET,
FSEZ1216, significantly simplifies power supply design
that requires CV and CC regulation capabilities.
FSEZ1216 controls the output voltage and current
precisely only with the information in the primary side of
the power supply, not only removing the output current
sensing loss, but also eliminating all secondary
feedback circuitry.
ƒ
Fixed Over-Temperature Protection with Latch
ƒ
DIP-8 Package Available
Fixed PWM Frequency at 42kHz with Frequency
Hopping to Reduce EMI
Low Startup Current: 10μA
The green-mode function with a low startup current
(10µA) maximizes the light load efficiency so the power
supply can meet stringent standby power regulations.
Low Operating Current: 3.5mA
Peak-Current-Mode Control in CV Mode
Cycle-by-Cycle Current Limiting
VDD Over-Voltage Protection with Auto-Restart
VDD Under-Voltage Lockout (UVLO)
Gate Output Maximum Voltage Clamped at 18V
Compared with conventional secondary side regulation
approach, the FSEZ1216 can reduce total cost,
component
count,
size,
and
weight,
while
simultaneously increasing efficiency, productivity, and
system reliability.
A typical output CV/CC characteristic envelope is shown
in Figure 1.
Applications
ƒ
Battery Chargers for Cellular Phones, Cordless
Phones, PDA, Digital Cameras, Power Tools
ƒ
ƒ
Replaces Linear Transformer and RCC SMPS
Offline High Brightness (HB) LED Drivers
Figure 1.
Typical Output V-I Characteristic
Ordering Information
Part Number
Operating
Temperature
Range
FSEZ1216NY -40°C to +105°C
MOSFET
BVDSS
MOSFET
RDS.ON
Eco
Status
Package
Packing
Method
600V
9.3Ω
(Typical)
Green
8-Lead, Dual Inline Package (DIP-8)
Tube
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
April 2009
CSN 2
RSN 2
VO
Bridge
Rectifier
Diode
RSN1
VDL
+
CDL
CSN1
NP
NS
DR
CO
RSTAR T
-
IO
DSN
DDD
AC Line
CDD
NA
FSEZ1216
RCS
CS
DRAIN
1
CCOMR
RCOMR
8
2 COMR
GND 7
3 COMI
VDD 6
4 COMV
VS 5
RS1
RS2
CC OM I
RC OM I
CS
CCOMV
RCOMV
Figure 2.
Typical Application
Internal Block Diagram
+
VDD
6
OVP
Auto
Restart
Protection
28V
+
Internal Bias
Brownout
8 DRAIN
Latch
Protection
OTP
-
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Application Diagram
16V/5V
OSC with
Frequency
Hopping
S Q
Soft-Driver
R Q
PWM
Comparator
PWM
Comparator
+
+
1.3V
Leading-Edge
Blanking
Slope Compensation
IO
Estimator
+
Green Mode
Controller
+
EA_I
2.5V
Cable Drop
Compensation
-
GND
Brownout
Protection
t DIS
Detector
5 VS
Temperature
Compensation
EA_V
7
VO
Estimator
3
4
COMI
2
COMV
Figure 3.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
1 CS
+
PWM
Comparator
COMR
Functional Block Diagram
www.fairchildsemi.com
2
F- Fairchild Logo
Z- Plant Code
X- 1-Digit Year Code
Y- 1-Digit Week Code
TT- 2-Digits Die Run Code
T- Package Type (N=DIP)
P- Z: Pb Free, Y: Green Package
M- Manufacture Flow Code
Figure 4.
Top Mark
Pin Configuration
DRAIN
CS
COMR
GND
COMI
VDD
COMV
VS
Figure 5.
Pin Configuration
Pin Definitions
Pin #
Name
1
CS
2
COMR
Cable Compensation. This pin connects a capacitor between COMR and GND for
compensation voltage drop due to output cable loss in CV mode.
3
COMI
Constant Current Loop Compensation. This pin connects a capacitor and a resistor between
COMI and GND for compensation current loop gain.
4
COMV
Constant Voltage Loop Compensation. This pin connects a capacitor and a resistor between
COMV and GND for compensation voltage loop gain.
5
VS
6
VDD
Power Supply. The power supply pin for the IC operating current and MOSFET driving current.
This pin is connects to an external VDD capacitor (typically 10μF). The threshold voltages for
startup and turn-off are 16V and 5V, respectively.
7
GND
Ground.
8
DRAIN
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Marking Information
Description
Current Sense. This pin connects a current-sense resistor to sense the MOSFET current for
peak-current-mode control in CV mode and provides for output-current regulation in CC mode.
Voltage Sense. This pin detects the output voltage information and discharge time based on
voltage of auxiliary winding. This pin connects two divider resistors and one capacitor.
Drain. This pin is the high-voltage power MOSFET drain.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
(1)
VVDD
DC Supply Voltage
Max.
Unit
30
V
VVS
VS Pin Input Voltage
-0.3
7.0
V
VCS
CS Pin Input Voltage
-0.3
7.0
V
VCOMV
Voltage Error Amplifier Output Voltage
-0.3
7.0
V
VCOMI
Voltage Error Amplifier Output Voltage
-0.3
7.0
V
600
V
VDS
Drain-Source Voltage
ID
Continuous Drain Current
TC=25°C
1.0
TC=100°C
0.6
A
IDM
Pulsed Drain Current
4
A
EAS
Single Pulse Avalanche Energy
33
mJ
IAR
Avalanche Current
1
A
PD
Power Dissipation (TA＜50°C)
800
mW
ΘJA
Thermal Resistance Junction-to-Air
113
°C/W
ΘJC
Thermal Resistance Junction-to-Case
67
°C/W
+150
°C
TJ
TSTG
TL
ESD
Operating Junction Temperature
Storage Temperature Range
+150
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
-55
+260
°C
Electrostatic Discharge Capability, Human Body Model,
JEDEC: JESD22-A114
2.5
KV
1250
V
Electrostatic Discharge Capability, Charged Device
Model, JEDEC: JESD22-C101
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Absolute Maximum Ratings
Note:
1. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Conditions
Operating Ambient Temperature
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
Min.
-40
Typ.
Max.
Unit
+105
°C
www.fairchildsemi.com
4
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
25
V
VDD-ON
VOP
Turn-On Threshold Voltage
15
16
17
V
VDD-OFF
Turn-Off Threshold Voltage
4.5
5.0
5.5
V
0
1.6
10.0
μA
3.5
5.0
mA
1
2
mA
IDD-ST
IDD-OP
Continuously Operating Voltage
Startup Current
Operating Current
0< VDD < VDD-ON-0.16V
VDD=20V, fS=fOSC, VVS=2V,
VCS=3V, CL=1nF
VDD=20V, VVS=2.7V,
fS=fOSC-N-MIN, VCS=0V, CL=1nF,
VCOMV=0V
IDD-GREEN
Green Mode Operating Supply
Current
VDD-OVP
VDD Over-Voltage Protection
Level
VCS=3V, VVS=2.3V,
27
28
29
V
tD-VDDOVP
VDD Over-Voltage Protection
Debounce Time
fs= fOSC, VVS=2.3V
100
250
400
μs
Center Frequency
TA=25°C
39
42
45
Frequency
Hopping Range
TA=25°C
±1.8
±2.6
±3.6
Oscillator Section
fOSC
Frequency
tFHR
Frequency Hopping Period
TA=25°C
3
KHz
ms
fOSC-N-MIN
Minimum Frequency at No Load
VVS=2.7V, VCOMV=0V
550
Hz
fOSC-CM-MIN
Minimum Frequency at CCM
VVS=2.3V, VCS=0.5V
20
KHz
fDV
Frequency Variation vs. VDD
Deviation
VDD=10V to 25V
5
%
fDT
Frequency Variation vs.
Temperature Deviation
TA=-40°C to +85°C
15
%
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Electrical Characteristics
Voltage-Sense Section
IVS-UVP
Itc
VBIAS-COMV
Sink Current for Brownout
Protection
RVS=20KΩ
IC Compensation Bias Current
Adaptive Bias Voltage
Dominated by VCOMV
VCOMV=0V, TA=25°C, RVS=20KΩ
180
μA
9.5
μA
1.4
V
Current-Sense Section
tPD
Propagation Delay to GATE
Output
100
200
ns
tMIN-N
Minimum On Time at No Load
VVS=-0.8V, RS=2KΩ, VCOMV=1V
1100
ns
tMINCC
Minimum On Time in CC Mode
VVS=0V, VCOMV=2V
400
ns
Duty Cycle of SAW Limiter
40
%
Threshold Voltage for Current
Limit
1.3
V
DSAW
VTH
Continued on following page…
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
5
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
2.475
2.500
2.525
V
Voltage-Error-Amplifier Section
VVR
Reference Voltage
VN
Green Mode Starting Voltage on
fS=fOSC-2KHz, VVS=2.3V
COMV Pin
2.8
V
VG
Green Mode Ending Voltage on
COMV Pin
fS=1KHz
0.8
V
Output Sink Current
VVS=3V, VCOMV=2.5V
90
μA
Output Source Current
VVS=2V, VCOMV=2.5V
90
μA
Output High Voltage
VVS=2.3V
IV-SINK
IV-SOURCE
VV-HGH
4.5
V
Current-Error-Amplifier Section
VIR
Reference Voltage
II-SINK
Output Sink Current
VCS=3V, VCOMI=2.5V
55
μA
Output Source Current
VCS=0V, VCOMI=2.5V
55
μA
Output High Voltage
VCS=0V
II-SOURCE
VI-HGH
2.475
2.500
2.525
V
4.5
V
Cable Compensation Section
VCOMR
Variation Test Voltage on COMR
RCOMR=100k
Pin for Cable Compensation
0.735
V
75
%
Internal MOSFET Section
DCYMAX
Maximum Duty Cycle
BVDSS
Drain-Source Breakdown
Voltage
ID=250μA, VGS=0V
∆BVDSS /∆TJ
Breakdown Voltage
Temperature Coefficient
ID=250μA, Referenced to 25°C
600
V
0.6
V/°C
IS
Maximum Continuous DrainSource Diode Forward Current
1
A
ISM
Maximum Pulsed Drain-Source
Diode Forward Current
4
A
11.5
Ω
RDS(ON)
Static Drain-Source OnResistance
IDSS
Drain-Source Leakage Current
tD-ON
Turn-On Delay Time
tr
tD-OFF
tf
(2,3)
ID=0.5A, VGS=10V
9.3
VDS=600V, VGS=0V, TC=25°C
1
VDS=480V, VGS=0V, TC=100°C
10
VDS=300V, ID=1.1A, RG=25Ω
μA
7
24
ns
Rise Time
21
52
ns
Turn-Off Delay Time
13
36
ns
Fall Time
CISS
Input Capacitance
COSS
Output Capacitance
VGS=0V, VDS=25V, fS=1MHz
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Electrical Characteristics
27
64
ns
130
170
pF
19
25
pF
Over-Temperature-Protection Section
TOTP
Threshold Temperature for
(4)
OTP
+140
°C
Notes:
2. Pulse test: pulse width ≦ 300µs, duty cycle ≦ 2%.
3. Essentially independent of operating temperature.
4. When over-temperature protection is activated, the power system enters latch mode and output is disabled.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
6
5.5
16.6
5.3
VDD-OFF (V)
VDD-ON (V)
17
16.2
15.8
15.4
5.1
4.9
4.7
15
4.5
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature (ºC)
Figure 6.
Turn-On Threshold Voltage (VDD-ON)
vs. Temperature
Figure 7.
4.5
75
85
100
125
Turn-Off Threshold Voltage (VDD-OFF)
vs. Temperature
44
fOSC (KHz)
IDD-OP (mA)
50
45
4.1
3.7
3.3
2.9
43
42
41
40
2.5
39
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature (ºC)
Figure 8.
0
25
50
75
85
100
125
Temperature (ºC)
Operating Current (IDD-OP)
vs. Temperature
Figure 9.
2.525
2.525
2.515
2.515
2.505
2.505
VIR (V)
VVR (V)
25
Temperature (ºC)
2.495
2.485
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics
Center Frequency (fOSC) vs. Temperature
2.495
2.485
2.475
2.475
-40
-30
-15
0
25
50
75
85
100
125
-40
Temperature (ºC)
-15
0
25
50
75
85
100
125
Temperature (ºC)
Figure 10. Reference Voltage (VVR) vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
-30
Figure 11. Reference Voltage (VIR) vs. Temperature
www.fairchildsemi.com
7
25
560
23
fOSC-CM-MIN (KHz)
fOSC-N-MIN (Hz)
600
520
480
440
21
19
17
400
15
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature (ºC)
25
75
85
100
125
Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN)
vs. Temperature
1000
25
950
20
900
tMIN-N (ns)
30
15
10
5
850
800
750
0
700
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature (ºC)
25
50
75
85
100
125
Temperature (ºC)
Figure 14. Green Mode Frequency Decreasing Rate
(SG) vs. Temperature
Figure 15. Minimum On Time at No Load (tMIN-N)
vs. Temperature
5
1
4
0.8
3
0.6
VG (V)
VN (V)
50
Temperature (ºC)
Figure 12. Minimum Frequency at No Load
(fOSC-N-MIN) vs. Temperature
SG (KHz/V)
0
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics (Continued)
2
0.4
0.2
1
0
0
-40
-30
-15
0
25
50
75
85
100
-40
125
Figure 16. Green Mode Starting Voltage on
COMV Pin (VN) vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 17. Green Mode Ending Voltage on
COMV Pin (VG) vs. Temperature
www.fairchildsemi.com
8
95
92
91
IV-SOURCE (µA)
IV-SINK (µA)
95
89
86
83
87
83
79
80
75
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
Temperature (ºC)
75
85
100
125
Figure 19. Output Source Current (IV-SOURCE)
vs. Temperature
65
65
62
62
II-SOURCE (µA)
II-SINK (µA)
Figure 18. Output Sink Current (IV-SINK)
vs. Temperature
59
56
53
59
56
53
50
50
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
Temperature (ºC)
0
25
50
75
85
100
125
Temperature (ºC)
Figure 20. Output Sink Current (II-SINK)
vs. Temperature
Figure 21. Output Source Current (II-SOURCE)
vs. Temperature
2
80
1.6
76
DCYMAX (%)
VCOMR (V)
50
Temperature (ºC)
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics (Continued)
1.2
0.8
0.4
72
68
64
0
60
-40
-30
-15
0
25
50
75
85
100
125
-40
Temperature (ºC)
-15
0
25
50
75
85
100
125
Temperature (ºC)
Figure 22. Variation Test Voltage on COMR Pin for
Cable Compensation (VCOMR)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
-30
Figure 23. Maximum Duty Cycle (DCYMAX)
vs. Temperature
www.fairchildsemi.com
9
Figure 24 shows the basic circuit diagram of primaryside regulated flyback converter, with typical waveforms
shown in Figure 25. Generally, discontinuous
conduction mode (DCM) operation is preferred for
primary-side regulation since it allows better output
regulation. The operation principles of DCM flyback
converter are as follows:
IO
D
+
V DL
VAC
Lm
+
+ VF -
VO
-
During the MOSFET ON time (tON), input voltage (VDL) is
applied across the primary-side inductor (Lm). Then
MOSFET current (Ids) increases linearly from zero to the
peak value (Ipk). During this time, the energy is drawn
from the input and stored in the inductor.
L
O
A
D
-
Ids
EA_I
V COMI
IO
Estimator
CS
RCS
Ref
t DIS
Detector
PWM
Control
When the MOSFET is turned off, the energy stored in
the inductor forces the rectifier diode (D) to turn on.
While the diode is conducting, the output voltage (VO),
together with diode forward voltage drop (VF), are
2
applied across the secondary-side inductor (Lm×Ns /
2
Np ) and the diode current (ID) decreases linearly from
the peak value (Ipk× Np/Ns) to zero. At the end of
inductor current discharge time (tDIS), all the energy
stored in the inductor has been delivered to the output.
V COMV
VS
NA
VDD
VO
Estimator
EA_V
RS1
Ref
RS2
Primary-Side Regulation
Controller
+
Vw
-
Figure 24. Simplified PSR Flyback Converter Circuit
When the diode current reaches zero, the transformer
auxiliary winding voltage (VW) begins to oscillate by the
resonance between the primary-side inductor (Lm) and
the effective capacitor loaded across MOSFET.
Id s (MOSFET Drain-to-Source Current)
I pk
During the inductor current discharge time, the sum of
output voltage and diode forward voltage drop is
reflected to the auxiliary winding side as (VO+VF)×
NA/NS. Since the diode forward voltage drop decreases
as current decreases, the auxiliary winding voltage
reflects the output voltage best at the end of diode
conduction time where the diode current diminishes to
zero. By sampling the winding voltage at the end of the
diode conduction time, the output voltage information
can be obtained. The internal error amplifier for output
voltage regulation (EA_V) compares the sampled
voltage with internal precise reference to generate error
voltage (VCOMV), which determines the duty cycle of the
MOSFET in CV mode.
ID (Diode Current)
I pk •
NP
NS
I D .avg = I
o
VW (Auxiliary Winding Voltage)
VF •
Meanwhile, the output current can be estimated using
the peak drain current and inductor current discharge
time since output current is same as the average of the
diode current in steady state.
The output current estimator picks up the peak value of
the drain current with a peak detection circuit and
calculates the output current using the inductor
discharge time (tDIS) and switching period (tS). These
output information is compared with internal precise
reference to generate error voltage (VCOMI), which
determines the duty cycle of the MOSFET in CC mode.
NA
NS
VO •
t ON
t
t
NA
NS
DI S
S
Figure 25. Key Waveforms of DCM Flyback
Converter
Among the two error voltages, VCOMV and VCOMI, the
smaller actually determines the duty cycle. During
constant voltage regulation mode, VCOMV determines the
duty cycle while VCOMI is saturated to HIGH. During
constant current regulation mode, VCOMI determines the
duty cycle while VCOMV is saturated to HIGH.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
ID
Np:Ns
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Functional Description
www.fairchildsemi.com
10
Switching Frequen cy
When it comes to cellular phone charger applications,
the actual battery is located at the end of cable, which
causes, typically, several percent of voltage drop on the
actual battery voltage. FSEZ1216 has a programmable
cable voltage drop compensation, which provides a
constant output voltage at the end of the cable over the
entire load range in CV mode. As load increases, the
voltage drop across the cable is compensated by
increasing the reference voltage of voltage regulation
error amplifier. The amount of compensation is
programmed by the resistor on the COMR pin. The
relationship between the amount of compensation and
the COMR resistor is shown in Figure 26.
42kHz
Dee p
Green
Mode
15
Green Mode
Normal Mode
550H z
14
0.8V
13
V COMV
2.8V
Figure 27. Switching Frequency in Green Mode
12
Compensation Percentage (%)
11
10
9
Frequency Hopping
8
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FSEZ1216 has an internal frequency
hopping circuit that changes the switching frequency
between 39.4kHz and 44.6kHz with a period of 3ms, as
shown in Figure 28.
7
6
5
4
3
2
Gate Drive Signal
1
10
20
30
40
50
60
RCOMR (k )
70
80
90
100
t
s
t
s
t
s
Figure 26. Cable Voltage Drop Compensation
Temperature Compensation
Built-in temperature compensation provides constant
voltage regulation over wide a range of temperature
variation.
This
internal
compensation
current
compensates the forward-voltage drop variation of the
secondary-side rectifier diode.
fs
Green-Mode Operation
44.6kHz
42.0kHz
39.4kHz
The FSEZ1216 uses voltage regulation error amplifier
output (VCOMV) as an indicator of the output load and
modulates the PWM frequency, as shown in Figure 27,
such that the switching frequency decreases as load
decreases. In heavy load conditions, the switching
frequency is fixed at 42KHz. Once VCOMV decreases
below 2.8V, the PWM frequency starts to linearly
decrease from 42KHz to 550Hz to reduce the switching
losses. As VCOMV decreases below 0.8V, the switching
frequency is fixed at 550Hz and FSEZ1216 enters deep
green mode, where the operating current reduces to
1mA, further reducing the standby power consumption.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Cable Voltage Drop Compensation
3ms
Figure 28. Frequency Hopping
t
www.fairchildsemi.com
11
enables and disables the switching of the MOSFET until
the fault condition is eliminated (see Figure 30).
Meanwhile, OTP is latch mode protection, which is reset
when VDD is fully discharged by un-plugging the AC
power line.
At the instant the MOSFET is turned on, there is a highcurrent spike through the MOSFET, caused by primaryside capacitance and secondary-side rectifier reverse
recovery. Excessive voltage across the RCS resistor can
lead to premature turn-off of MOSFET. FSEZ1216
employs an internal leading-edge blanking (LEB) circuit.
To inhibit the PWM comparator for a short time after the
MOSFET is turned on. External RC filtering is not required.
VDS
Fault
Occurs
Power
On
Fault Removed
Startup
Figure 29 shows the typical startup circuit and
transformer auxiliary winding for a FSEZ1216
application. Before FSEZ1216 begins switching, it
consumes only startup current (typically 10μA) and the
current supplied through the startup resistor charges the
VDD capacitor (CDD). When VDD reaches turn-on voltage
of 16V (VDD-ON), FSEZ1216 begins switching, and the
current consumed by FSEZ1216 increases to 3.5mA.
Then, the power required for FSEZ1216 is supplied from
the transformer auxiliary winding. The large hysteresis
of VDD provides more holdup time, which allows using a
small capacitor for VDD.
VDD
16V
5V
Operating Current
VD L
+
CD L
-
3.5mA
Np
10µA
RSTAR T
Normal
Operation
DD D
Fault
Situation
Normal
Operation
Figure 30. Auto-Restart Operation
CD D
AC Line
NA
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 28V by
open feedback condition, OVP is triggered. The OVP
has a de-bounce time (typcal 250µs) to prevent false
trigger by switching noise. It also protects other
switching devices from over voltage.
FSEZ1216
1
2
3
4
CS
DRAIN 8
COMR
SGND
COMI
VDD
COMV
VS
7
RS1
6
5
RS2
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Leading-Edge Blanking (LEB)
Over-Temperature Protection (OTP)
A built-in temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 140°C.
Figure 29. Startup Circuit
Brownout Protection
FSEZ1216 detects the line voltage using auxiliary
winding voltage since the auxiliary winding voltage
reflects the input voltage when the MOSFET is turned
on. The VS pin is clamped at 1.15V while the MOSFET
is turned on and brownout protection is triggered if the
current out of the VS pin is less than IVS-UVP (typical
180μA) during the MOSFET conduction.
Protections
The FSEZ1216 has several self-protective functions,
such as Over-Voltage Protection (OVP), OverTemperature
Protection
(OTP),
and
brownout
protection. All the protections except OTP are
implemented as auto-restart mode. Once the fault
condition occurs, switching is terminated and the
MOSFET remains off. This causes VDD to fall. When VDD
reaches the VDD turn-off voltage of 5V, the current
consumed by FSEZ1216 reduces to the startup current
(typically 10µA) and the current supplied startup resistor
charges the VDD capacitor. When VDD reaches the turnon voltage of 16V, FSEZ1216 resumes its normal
operation. In this manner, the auto-restart alternately
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
Pulse-by-Pulse Current Limit
When the sensing voltage across the current sense
resistor exceeds the internal threshold of 1.4V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
www.fairchildsemi.com
12
Application
Fairchild Devices
Input Voltage Range
Output
Cell Phone Charger
FSEZ1216
90~265VAC
5V/0.78A (3.9W)
Features
ƒ
High efficiency (>66% at full load) meeting Energy StarSM V2.0 and CEC regulation
ƒ
Low standby power consumption (Pin=0.095W for 115VAC and Pin=0.138W for 230VAC)
ƒ
Tight output regulation (CV:±5%, CC:±7%)
74
6
72
5
Efficiency (%)
Output Voltage (V)
115V60Hz (68.7% avg)
70
230V50Hz (66.9% avg)
68
66
66.3% : Energy Star V2.0 (Nov. 2008)
4
3
AC90V
AC120V
AC230V
AC264V
2
64
1
62
62.2% : CEC (2008)
25
50
75
0
100
0
100
200
300
Load (%)
400
500
600
700
800
Output Current (mA)
Figure 31. Measured Efficiency and Output Regulation
1nF
30Ω
CSN2
RSN2
1mH
+
1N4007
1N4007
1N4007
1N4007
1kΩ
CDL2
CDL1
4.7µF
4.7µF
LP 15µH
SB260
VDL
RSTART
2MΩ
4.7µH
RSN1
CSN1
100kΩ
1nF
RDAMP
IO
VO
DR
N1
N3
CO
470µF
270Ω
DSN
1N4007
1N4007
DDD
CDD
AC Line
900
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Application Circuit (Primary-Side Regulated Flyback Charger)
CP
220µF
RPL
1kΩ
N2
10µF
FSEZ1216
1
2
100kΩ
RCS
1.4Ω
RCOMR
3
4
CS
DRAIN
COMR
SGND
COMI
COMV
VDD
VS
8
RS1
7
115kΩ
6
5
RS2
1µF
24.9kΩ
CCOMR
10nF
68nF CCOMI
200kΩRCOMI
CCOMV
CS
RCOMV
43kΩ
47pF
Figure 32. Schematic of Typical Application Circuit
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
13
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Application Circuit (Continued)
Transformer specification
ƒ
ƒ
Core: EE16
Bobbin: EE16
Pin
Specifications
Primary-Side Inductance
1－3
2.3mH ± 5%
100kHz, 1V
Primary-Side Effective Leakage
1－8
65μH ± 5%.
Short one of the secondary windings
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
Remark
www.fairchildsemi.com
14
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
5.08 MAX
7.62
0.33 MIN
3.60
3.00
(0.56)
2.54
0.56
0.355
0.356
0.20
1.65
1.27
9.957
7.87
7.62
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
Physical Dimensions
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 33. 8-Lead, Dual Inline Package (DIP-8)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
15
FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET
© 2009 Fairchild Semiconductor Corporation
FSEZ1216 • Rev. 1.0.1
www.fairchildsemi.com
16