ON NCP4586DMU18TCG 150 ma, low noise, low dropout regulator Datasheet

NCP4586
150 mA, Low Noise, Low
Dropout Regulator
The NCP4586 is a CMOS 150 mA low dropout linear with low
noise, high ripple rejection, low dropout, high output voltage accuracy
and low supply current. The device is available in three
configurations: enable high, enable low and enable high plus
auto−discharge. Small packages allow mounting on high density
PCBs. This is an excellent general purpose regulator, well suited to
many applications.
Features
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 1.7 V to 6.5 V
Output Voltage Range: 1.2 to 5.0 V (available in 0.1 V steps)
Very Low Dropout: 320 mV Typ. at 150 mA
±1% Output Voltage Accuracy (VOUT > 2 V, TJ = 25°C)
High PSRR: 80 dB at 1 kHz
Current Fold Back Protection
Stable with a 0.47 mF Ceramic Capacitors
Available in 1.0 x 1.0 UDFN, SC−82AB and SOT23−5 Package
These are Pb−Free Devices
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MARKING
DIAGRAMS
1
UDFN4
CASE 517BR
XX
MM
SC−82AB
CASE 419C
Typical Applications
•
•
•
•
Battery Powered Equipment
Portable Communication Equipment
Cameras, MP3 Players and Camcorder
High Stability Voltage Reference
SOT−23−5
CASE 1212
VIN
C1
470 n
GND
XXX
MM
VOUT
VOUT
CE
1
XX, XXX= Specific Product Code
MM
= Lot Number
NCP4586x
VIN
1
XX
MM
ORDERING INFORMATION
C2
470 n
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 4
1
Publication Order Number:
NCP4586/D
NCP4586
NCP4586Lxxxxxxxx
NCP4586Hxxxxxxxx
VIN
VOUT
VIN
Vref
VOUT
Vref
Current Limit
CE
CE
Current Limit
GND
GND
NCP4586Dxxxxxxxx
VIN
VOUT
Vref
Current Limit
CE
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
UDFN4
Pin No.
SC82−AB
Pin No.
SOT23−5
Pin Name
4
4
1
VIN
Input pin
2
2
2
GND
Ground
3
1
3
CE/CE
Chip enable pin (“L” active / “H” active)
1
3
5
VOUT
Output pin
−
−
4
NC
Description
No connection
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2
NCP4586
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
7
V
Output Voltage
VOUT
−0.3 to VIN + 0.3
V
Chip Enable Input
VCE
−0.3 to 7
V
Output Current
IOUT
200
mA
PD
400
Input Voltage (Note 1)
Power Dissipation UDFN4
Power Dissipation SC−82AB
380
Power Dissipation SOT23−5
420
mW
Maximum Junction Temperature
TJ(MAX)
+150
°C
Operating Ambient Temperature
TA
−40 to +85
°C
TSTG
−55 to +125
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Storage Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, UDFN4
Thermal Resistance, Junction−to−Air
RqJA
250
°C/W
Thermal Characteristics, SOT23−5
Thermal Resistance, Junction−to−Air
RqJA
238
°C/W
Thermal Characteristics, SC 82AB
Thermal Resistance, Junction−to−Air
RqJA
263
°C/W
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NCP4586
ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 85°C; VIN = VOUT(NOM) + 1 V or 2.5 V, whichever is greater; IOUT = 1 mA, CIN =
COUT = 0.47 mF, unless otherwise noted. Typical values are at TA = +25 °C.
Parameter
Test Conditions
Max
Unit
1.7
6.5
V
x0.99
x1.01
V
VOUT ≤ 2 V
−20
20
mV
VOUT > 2 V
x0.985
x1.015
V
VOUT ≤ 2 V
−30
30
mV
Operating Input Voltage
Output Voltage
TA = +25 °C
VOUT > 2 V
−40°C ≤ TA ≤ 85°C
Output Voltage Temp. Coefficient
Symbol
Min
VIN
VOUT
TA = −40 to 85°C
Typ
ppm/°C
±20
Line Regulation
VIN = VOUT + 0.5 V to 5 V
LineReg
0.02
0.10
%/V
Load Regulation
IOUT = 1 mA to 150 mA
LoadReg
10
30
mV
VDO
0.67
1.00
V
1.5 V ≤ VOUT < 1.7 V
0.54
0.81
1.7 V ≤ VOUT < 2.0 V
0.46
0.68
2.0 V ≤ VOUT < 2.5 V
0.41
0.60
2.5 V ≤ VOUT < 4.0 V
0.32
0.51
4.0 V ≤ VOUT
0.24
0.37
Dropout Voltage
IOUT = 150 mA
1.2 V ≤ VOUT < 1.5 V
Output Current
IOUT
150
mA
Short Current Limit
VOUT = 0 V
ISC
40
Quiescent Current
IOUT = 0 mA
IQ
38
58
mA
VCE = VIN (L version), VCE = 0 V(H and
D version), TA = 25°C
ISTB
0.1
1
mA
CE / CE Input Voltage “H”
VCEH
CE / CE Input Voltage “L”
VCEL
H and D version
IPD
0.4
mA
VIN = VOUT + 1 V or 3.0 V whichever is higher,
IOUT = 30 mA, f = 1 kHz
PSRR
80
dB
VOUT = 1.2 V, IOUT = 30 mA, f = 10 Hz to
100 kHz
VN
30
mVrms
D Version only, VIN = 4 V, VCE = 0 V
RLOW
30
W
Standby Current
CE/CE Pin Threshold Voltage
CE Pull Down Current
Power Supply Rejection Ratio
Output Noise Voltage
Low Output N−ch Tr. On
Resistance
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4
mA
V
1.0
0.4
NCP4586
TYPICAL CHARACTERISTICS
1.4
3.0
1.2
4.2 V
2.0
6.0 V
0.8
VOUT (V)
VOUT (V)
1.0
2.5
3.6 V
VIN = 2.2 V
6.5 V
0.6
VIN = 6.5 V
3.8 V
1.5
1.0
0.4
0.5
0.2
0.0
4.2 V
6.0 V
0
100
200
300
IOUT (mA)
400
0.0
500
0
Figure 3. Output Voltage vs. Output Current
1.2 V Version (TA = 25 5C)
200
300
IOUT (mA)
400
500
Figure 4. Output Voltage vs. Output Current
2.8 V Version (TA = 25 5C)
6
0.8
0.7
5
0.6
6.0 V
4
VIN = 6.5 V
3
25°C
0.5
VDO (V)
VOUT (V)
100
2
85°C
0.4
0.3
−40°C
0.2
1
0
0
0.1
100
200
300
400
0
0
500
100
200
IOUT (mA)
300
400
500
IOUT (mA)
Figure 5. Output Voltage vs. Output Current
5.0 V version (TA = 255C)
Figure 6. Dropout Voltage vs. Output Current
1.2 V version
0.40
0.30
0.35
0.25
0.20
0.25
25°C
0.20
VDO (V)
VDO (V)
0.30
85°C
0.15
0.10
85°C
0.10
−40°C
−40°C
0.05
0.05
0.00
0
25°C
0.15
100
200
300
400
500
0.00
0
IOUT (mA)
25
50
75
100
125
150
IOUT (mA)
Figure 7. Dropout Voltage vs. Output Current
2.8 V Version
Figure 8. Dropout Voltage vs. Output Current
5.0 V Version
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NCP4586
TYPICAL CHARACTERISTICS
2.85
1.25
VIN = 3.8 V
1.23
2.83
1.21
2.81
VOUT (V)
VOUT (V)
VIN = 2.2 V
1.19
2.79
2.77
1.17
1.15
−40
−20
0
20
40
60
TJ, JUNCTION TEMPERATURE (°C)
2.75
−40
80
Figure 9. Output Voltage vs. Temperature, 1.2 V
Version
5.05
45.0
40.0
5.02
35.0
5.01
30.0
IIN (mA)
VOUT (V)
50.0
5.03
5.00
4.99
25.0
20.0
4.98
15.0
4.97
10.0
4.96
5.0
4.95
−40
−20
0
20
40
60
TJ, JUNCTION TEMPERATURE (°C)
0.0
80
0
50.0
50.0
45.0
45.0
40.0
40.0
35.0
35.0
30.0
30.0
25.0
20.0
10.0
10.0
5.0
5.0
2
3
VIN (V)
4
5
3
VIN (V)
4
5
6
20.0
15.0
1
2
25.0
15.0
0
1
Figure 12. Supply Current vs. Input Voltage,
1.2 V Version
IIN (mA)
IIN (mA)
Figure 11. Output Voltage vs. Temperature,
5.0 V Version
0.0
80
Figure 10. Output Voltage vs. Temperature,
2.8 V version
VIN = 6.0 V
5.04
−20
0
20
40
60
TJ, JUNCTION TEMPERATURE (°C)
0.0
6
0
Figure 14. Supply Current vs. Input Voltage,
2.8 V Version
1
2
3
VIN (V)
4
5
6
Figure 13. Supply Current vs. Input Voltage,
5.0 V version
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NCP4586
TYPICAL CHARACTERISTICS
40.0
40.0
VIN = 2.2 V
38.0
38.0
37.0
37.0
36.0
36.0
35.0
34.0
33.0
32.0
31.0
31.0
−20
0
20
40
60
30.0
−40
80
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Supply Current vs. Temperature,
1.2 V Version
Figure 16. Supply Current vs. Temperature,
2.8 V Version
1.4
VIN = 6.0 V
1.2
43
1.0 1 mA
42
VOUT (V)
41
40
39
38
0.8
0.6
30 mA
0.4
37
IOUT = 50 mA
0.2
36
35
−40
−20
0
20
40
60
0.0
80
1
2
3
4
5
6
VIN (V)
Figure 17. Supply Current vs. Temperature,
5.0 V Version
Figure 18. Output Voltage vs. Input Voltage,
1.2 V Version
6.0
2.5
5.0
2.0
VOUT (V)
1.5
1.0
2
1 mA
1.0
IOUT = 50 mA
1
3.0
2.0
30 mA
0.5
7
4.0
1 mA
0
0
TJ, JUNCTION TEMPERATURE (°C)
3.0
0.0
−20
TJ, JUNCTION TEMPERATURE (°C)
45
IIN (mA)
34.0
32.0
44
VOUT (V)
35.0
33.0
30.0
−40
VIN = 3.8 V
39.0
IIN (mA)
IIN (mA)
39.0
3
4
VIN (V)
5
6
0.0
7
30 mA
IOUT = 50 mA
0
Figure 19. Output Voltage vs. Input Voltage,
2.8 V Version
1
2
3
4
VIN (V)
5
6
Figure 20. Output Voltage vs. Input Voltage,
5.0 V Version
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7
NCP4586
TYPICAL CHARACTERISTICS
100
100
1 mA
90
80
PSRR (dB)
50
40
50
40
30
20
20
10
10
0.1
1
10
FREQUENCY (kHz)
100
IOUT = 150 mA
60
30
0
0.01
30 mA
70
IOUT = 150 mA
60
1 mA
80
30 mA
70
PSRR (dB)
90
0
0.01
1000
Figure 21. PSRR, 1.2 V Version
100
1000
1.6
90
1.4
80
1.2
1 mA
70
30 mA
IOUT = 150 mA
60
50
VN (mVrms/√Hz)
PSRR (dB)
1
10
FREQUENCY (kHz)
Figure 22. PSRR, 2.8 V Version
100
40
30
1.0
0.8
0.6
0.4
20
0.2
10
0
0.01
0.1
1
10
FREQUENCY (kHz)
100
0
0.01
1000
Figure 23. PSRR, 5.0 V Version
0.1
1
10
FREQUENCY (kHz)
100
1000
Figure 24. Output Voltage Noise, 1.2 V Version
7.0
7.0
6.0
6.0
5.0
5.0
VN (mVrms/√Hz)
VN (mVrms/√Hz)
0.1
4.0
3.0
2.0
1.0
4.0
3.0
2.0
1.0
0
0.01
0.1
1
10
FREQUENCY (kHz)
100
0
0.01
1000
Figure 25. Output Voltage Noise, 2.8 V Version
0.1
1
10
FREQUENCY (kHz)
100
1000
Figure 26. Output Voltage Noise, 5.0 V Version
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NCP4586
TYPICAL CHARACTERISTICS
4
3
1
VIN (V)
VOUT (V)
2
1.205
1.200
1.195
1.190
0
10
20
30
40
50
t (ms)
60
70
80
90
100
Figure 27. Line Transients, 1.2 V Version,
tR = tF = 5 ms, IOUT = 30 mA
6
5
3
VIN (V)
VOUT (V)
4
2.805
2.800
2.795
2.790
0
10
20
30
40
50
t (ms)
60
70
80
90
100
Figure 28. Line Transients, 2.8 V Version,
tR = tF = 5 ms, IOUT = 30 mA
7
6
4
VIN (V)
VOUT (V)
5
5.005
5.000
4.995
4.990
0
10
20
30
40
50
t (ms)
60
70
80
90
Figure 29. Line Transients, 5.0 V Version, tR =
tF = 5 ms, IOUT = 30 mA
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100
NCP4586
TYPICAL CHARACTERISTICS
200
150
100
0
1.23
1.22
1.21
1.20
1.19
1.18
0
10
20
30
40
50
t (ms)
60
70
80
90
IOUT (mA)
VOUT (V)
50
100
Figure 30. Load Transients, 1.2 V Version,
IOUT = 50 − 100 mA, tR = tF = 0.5 ms, VIN = 2.2 V
200
150
100
0
2.83
2.82
2.81
2.80
2.79
2.78
0
10
20
30
40
50
60
70
80
90
IOUT (mA)
VOUT (V)
50
100
t (ms)
Figure 31. Load Transients, 2.8 V Version,
IOUT = 50 − 100 mA, tR = tF = 0.5 ms, VIN = 3.8 V
200
150
100
0
5.03
5.02
5.01
4.99
4.98
0
10
20
30
40
50
t (ms)
60
70
80
90
Figure 32. Load Transients, 5.0 V Version,
IOUT = 50 − 100 mA, tR = tF = 0.5 ms, VIN = 6.0 V
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10
100
IOUT (mA)
VOUT (V)
50
NCP4586
TYPICAL CHARACTERISTICS
200
150
50
0
1.30
1.25
1.20
1.15
1.10
1.05
0
10
20
30
40
50 60
t (ms)
70
80
90
IOUT (mA)
VOUT (V)
100
100
Figure 33. Load Transients, 1.2 V Version,
IOUT = 1 − 150 mA, tR = tF = 0.5 ms, VIN = 2.2 V
200
150
50
0
2.90
2.85
2.80
2.75
2.70
2.65
0
10
20
30
40
50 60
t (ms)
70
80
90
IOUT (mA)
VOUT (V)
100
100
Figure 34. Load Transients, 2.8 V Version,
IOUT = 1 − 150 mA, tR = tF = 0.5 ms, VIN = 3.8 V
200
150
50
0
5.10
5.05
5.00
4.95
4.90
4.85
0
10
20
30
40
50
60
70
80
90
t (ms)
Figure 35. Load Transients, 5.0 V Version,
IOUT = 1 − 150 mA, tR = tF = 0.5 ms, VIN = 6.0 V
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11
100
IOUT (mA)
VOUT (V)
100
NCP4586
TYPICAL CHARACTERISTICS
4
3
Chip Enable
2
0
2.0
1.5
IOUT = 150 mA
1.0
IOUT = 1 mA
VCE (V)
VOUT (V)
1
0.5
0.0
−0.5
0
2
4
6
8
10 12
t (ms)
14
16
18
20
Figure 36. Start−up, 1.2 V Version, VIN = 2.2 V
5
Chip Enable
4
3
1
4
3
2
IOUT = 1 mA
1
VCE (V)
VOUT (V)
2
IOUT = 150 mA
0
−1
0
2
4
6
8
10
t (ms)
12
14
16
18
20
Figure 37. Start−up, 2.8 V Version, VIN = 3.8 V
10
8
Chip Enable
6
2
8
0
6
4
IOUT = 1 mA
2
IOUT = 150 mA
0
−2
0
5
10
15
20
25
t (ms)
30
35
40
45
Figure 38. Start−up, 5.0 V Version, VIN = 6.0 V
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12
50
VCE (V)
VOUT (V)
4
NCP4586
TYPICAL CHARACTERISTICS
4
3
2
VOUT (V)
0
2.0
1.5
IOUT = 1 mA
IOUT = 30 mA
1.0
0.5
0.0
−0.5
VCE (V)
1
Chip Enable
IOUT = 150 mA
0
10
20
30
40
50 60
t (ms)
70
80
90
100
Figure 39. Shutdown, 1.2 V Version D,
VIN = 2.2 V
5
4
2
Chip Enable
2.0
1
1.5
IOUT = 1 mA
IOUT = 30 mA
1.0
0.5
0.0
−0.5
VCE (V)
VOUT (V)
3
IOUT = 150 mA
0
10
20
30
40
50
t (ms)
60
70
80
90
100
Figure 40. Shutdown, 2.8 V Version D,
VIN = 3.8 V
10
8
6
2
Chip Enable
8
0
6
4
IOUT = 1 mA
2
0
−2
IOUT = 30 mA
IOUT = 150 mA
0
10
20
30
40
50
t (ms)
60
70
80
90
Figure 41. Shutdown, 5.0 V version D,
VIN = 6.0 V
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100
VCE (V)
VOUT (V)
4
NCP4586
APPLICATION INFORMATION
A typical application circuit for NCP4586 series is shown
in Figure 42.
NCP4586x
VIN
VIN
C1
470n
VOUT
CE
GND
version of IC. Active high or low versions are available;
please see the ordering information table. The Enable pin
has an internal pull down current source for versions H and
D. If the enable function is not needed connect the CE pin to
ground for version L or connect the CE pin to VIN for
versions H and D.
VOUT
C2
470n
Output Discharger
The D version includes a transistor between VOUT and
GND that is used for faster discharging of the output
capacitor. This function is activated when the IC goes into
disable mode.
Thermal
Figure 42. Typical Application Schematic
As power across the IC increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature rise for the part.
That is to say, when the device has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
Input Decoupling Capacitor (C1)
A 470 nF ceramic input decoupling capacitor should be
connected as close as possible to the input and ground pin of
the NCP4586. Higher values and lower ESR improves line
transient response.
Output Decoupling Capacitor (C2)
A 470 nF or larger ceramic output decoupling capacitor is
sufficient to achieve stable operation of the IC. If a tantalum
capacitor is used, and its ESR is high, loop oscillation may
result. The capacitors should be connected as close as
possible to the output and ground pins. Larger values and
lower ESR improves dynamic parameters.
PCB Layout
Make VIN and GND line sufficient. If their impedance is
high, noise pickup or unstable operation may result. Connect
capacitors C1 and C2 as close as possible to the IC, and make
wiring as short as possible.
Enable Operation
The Enable pin CE or CE may be used for turning the
regulator on and off. Control polarity is dependent on
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NCP4586
ORDERING INFORMATION
Device
Nominal Output
Voltage
Description
Marking
NCP4586DSQ12T1G
1.2 V
LA
NCP4586DSQ18T1G
1.8 V
LG
NCP4586DSQ28T1G
2.8 V
MH
NCP4586DSQ30T1G
3.0 V
NA
NCP4586DSQ33T1G
3.3 V
ND
NCP4586DSQ50T1G
5.0 V
QA
NCP4586DMU12TCG
1.2 V
VA
NCP4586DMU14TCG
1.4 V
VC
NCP4586DMU15TCG
1.5 V
VD
NCP4586DMU18TCG
1.8 V
NCP4586DMU25TCG
2.5 V
NCP4586DMU28TCG
2.8 V
VT
NCP4586DMU30TCG
3.0 V
VW
NCP4586DMU33TCG
3.3 V
VZ
NCP4586DMU50TCG
5.0 V
WS
NCP4586DSN12T1G
1.2 V
H2A
NCP4586DSN18T1G
1.8 V
H2G
NCP4586DSN28T1G
2.8 V
H2T
NCP4586DSN30T1G
3.0 V
H2W
NCP4586DSN33T1G
3.3 V
H2Z
NCP4586DSN50T1G
5.0 V
J2S
Package
Shipping†
SC82AB
(Pb−Free)
3000 / Tape & Reel
UDFN4
(Pb−Free)
10000 / Tape & Reel
SOT−23−5
(Pb−Free)
3000 / Tape & Reel
VG
Enable High,
Auto discharge
VQ
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: To order other package and voltage variants, please contact your ON Semiconductor sales representative.
http://onsemi.com
15
NCP4586
PACKAGE DIMENSIONS
UDFN4 1.0x1.0, 0.65P
CASE 517BR−01
ISSUE O
PIN ONE
REFERENCE
2X
0.05 C
4X
A
B
D
ÉÉ
ÉÉ
typ
DETAIL A
0.05 C
2X
c 0.18
L2
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L3
3X
TOP VIEW
0.43
4X
0.23
(A3)
0.05 C
A
3X
0.05 C
NOTE 4
A1
SIDE VIEW
e
DETAIL A
3X
2
0.10
DETAIL B
MILLIMETERS
MIN
MAX
−−−
0.60
0.00
0.05
0.10 REF
0.20
0.30
1.00 BSC
0.43
0.53
1.00 BSC
0.65 BSC
0.20
0.30
0.27
0.37
0.02
0.12
RECOMMENDED
MOUNTING FOOTPRINT*
e/2
1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
e
L
L2
L3
L
0.65
PITCH
DETAIL B
D2
45 5
D2
4
3
0.52
1.30
4X
BOTTOM VIEW
2X
PACKAGE
OUTLINE
b
0.05
M
C A B
NOTE 3
0.53
4X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
NCP4586
PACKAGE DIMENSIONS
SC−82AB
CASE 419C−02
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. 419C−01 OBSOLETE. NEW STANDARD IS
419C−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
A
G
C
D 3 PL
N
4
DIM
A
B
C
D
F
G
H
J
K
L
N
S
3
K
B
S
1
2
F
L
H
J
0.05 (0.002)
MILLIMETERS
MIN
MAX
1.8
2.2
1.15
1.35
0.8
1.1
0.2
0.4
0.3
0.5
1.1
1.5
0.0
0.1
0.10
0.26
0.1
−−−
0.05 BSC
0.2 REF
1.8
2.4
SOLDERING FOOTPRINT*
1.30
0.0512
0.65
0.026
1.90
0.95 0.075
0.037
0.90
0.035
0.70
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.008
0.016
0.012
0.020
0.043
0.059
0.000
0.004
0.004
0.010
0.004
−−−
0.002 BSC
0.008 REF
0.07
0.09
NCP4586
PACKAGE DIMENSIONS
SOT−23 5−LEAD
CASE 1212−01
ISSUE A
A
5
E
1
L1
A1
4
2
DIM
A
A1
A2
b
c
D
E
E1
e
L
L1
L
3
5X
e
A2
0.05 S
B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
A
E1
b
0.10
C
M
C B
S
A
S
C
MILLIMETERS
MIN
MAX
--1.45
0.00
0.10
1.00
1.30
0.30
0.50
0.10
0.25
2.70
3.10
2.50
3.10
1.50
1.80
0.95 BSC
0.20
--0.45
0.75
RECOMMENDED
SOLDERING FOOTPRINT*
3.30
5X
0.85
5X
0.95
PITCH
0.56
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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http://onsemi.com
18
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP4586/D