TI1 LM36923HYFFR Highly efficient triple-string white led driver Datasheet

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LM36923H
SNVSAF3A – FEBRUARY 2016 – REVISED FEBRUARY 2016
LM36923H Highly Efficient Triple-String White LED Driver
1 Features
3 Description
•
The LM36923H is an ultra-compact, highly efficient,
three-string white-LED driver designed for LCD
display backlighting. The device can power up to 12
series LEDs at up to 25 mA per string. An adaptive
current regulation method allows for different LED
voltages in each string while maintaining current
regulation.
1
•
•
•
•
•
•
•
•
•
•
•
•
1% Matched Current Sinks Across Process,
Voltage, Temperature
3% Current-Sink Accuracy Across Process,
Voltage, Temperature
11-Bit Dimming Resolution
Up to 90% Solution Efficiency
Drives from One to Three Parallel LED Strings at
up to 38 V at 25 mA per String
PWM Dimming Input
I2C Programmable
Selectable 500-kHz and 1-MHz Switching
Frequency With Optional –12% shift
Auto Switch Frequency Mode (250 kHz, 500 kHz,
1 MHz)
Four Configurable Overvoltage Protection
Thresholds (17 V, 24 V, 31 V, 38 V)
Four Configurable Overcurrent Protection
Thresholds (750 mA, 1000 mA, 1250 mA,
1500 mA)
Thermal Shutdown Protection
Externally Selectable I2C Address Options via
ASEL Input
The LED current is adjusted via an I2C interface or
through a logic level PWM input. The PWM duty cycle
is internally sensed and mapped to an 11-bit current
thus allowing for a wide range of PWM frequencies
with noise-free operation from 50 µA to 25 mA.
Other features include an auto-frequency mode,
which can automatically change the frequency based
on load current in order to optimize efficiency.
The device operates over the 2.5-V to 5.5-V input
voltage range and a –40°C to +85°C temperature
range.
Device Information(1)
PART NUMBER
LM36923H
PACKAGE
DSBGA (12)
BODY SIZE (MAX)
1.756 mm × 1.355 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
2 Applications
•
space
Power Source for Smart Phone and Tablet
Backlighting
LCD Panels With up to 24 LEDs
•
space
space
space
space
Simplified Schematic
VOUT (Up to 38V)
Typical String-to-String Matching vs LED Current
VBATT
VIO
SW
OVP
IN
LM36923H
HWEN
SDA
SCL
LED1
ASEL
LED2
PWM
GND
LED3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM36923H
SNVSAF3A – FEBRUARY 2016 – REVISED FEBRUARY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
I2C Timing Requirements..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
16
7.5 Programming........................................................... 24
7.6 Register Maps ........................................................ 25
8
Applications and Implementation ...................... 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
9
Power Supply Recommendations...................... 35
9.1 Input Supply Bypassing .......................................... 35
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 38
11 Device and Documentation Support ................. 39
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Trademarks ...........................................................
Community Resources..........................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2016) to Revision A
•
2
Page
Changed device from product preview to production ............................................................................................................ 1
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5 Pin Configuration and Functions
YFF Package
12-Pin DSBGA
Top View
A
LED1
ASEL
GND
B
LED2
SDA
SW
C
LED3
SCL
VOUT
D
PWM
HWEN
IN
1
2
3
Pin Functions
PIN
I/O
DESCRIPTION
NUMBER
NAME
A1
LED1
Input
Input to current sink 1. The boost converter regulates the minimum voltage between LED1,
LED2, LED3 to VHR.
A2
ASEL
Input
ASEL is a logic input which selects between two I2C address options. This pin is read on
power up (VIN going above 1.8 V, and HWEN going above a logic high voltage). GND =
address 0x36, logic high = address 0x37.
A3
GND
Input
Ground
B1
LED2
Input
Input pin to current sink 2. The boost converter regulates the minimum voltage between LED1,
LED2 ,LED3 to VHR.
B2
SDA
I/O
B3
SW
Output
C1
LED3
Input
Input pin to current sink 3. The boost converter regulates the minimum voltage between LED1,
LED2, LED3 to VHR.
C2
SCL
Input
Clock input for I2C-compatible interface.
C3
OUT
Input
OUT serves as the sense point for overvoltage protection. Connect OUT to the positive pin of
the output capacitor.
D1
PWM
Input
Logic level input for PWM current control.
D2
HWEN
Input
Hardware enable input. Drive HWEN high to bring the device out of shutdown and allow I2C
writes or PWM control.
D3
IN
Input
Input voltage connection. Bypass IN to GND with a minimum 2.2-µF ceramic capacitor.
Data I/O for I2C-Compatible Interface.
Drain connection for internal low side NFET, and anode connection for external Schottky
diode.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
IN
Input voltage
–0.3
6
V
OUT
Output overvoltage sense input
–0.3
40
V
SW
Inductor connection
–0.3
40
V
LED1, LED2, LED3
LED string cathode connection
–0.3
30
V
HWEN, PWM, SDA,
SCL, ASEL
Logic I/Os
–0.3
6
V
150
°C
150
°C
Maximum junction temperature, TJ_MAX
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
IN
Input voltage
2.5
5.5
V
OUT
Overvoltage sense input
0
38
V
SW
Inductor connection
0
38
V
LED1, LED2, LED3
LED string cathode connection
0
29.5
V
HWEN, PWM, SDA,
SCL, ASEL
Logic I/Os
0
5.5
V
6.4 Thermal Information
LM36923H
THERMAL METRIC (1)
YFQ (DSBGA)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
88.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.7
°C/W
RθJB
Junction-to-board thermal resistance
43.9
°C/W
ΨθJT
Junction-to-top characterization parameter
2.9
°C/W
ΨθJB
Junction-to-board characterization parameter
43.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), typical values
are at TA = 25°C, and VIN = 3.6 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–1%
0.1%
1%
UNIT
BOOST
IMATCH (1)
LED current matching ILED1 50 µA ≤ ILED ≤ 25 mA, 2.7 V ≤ VIN ≤ 5 V (linear
to ILED2 to ILED3
or exponential mode)
Accuracy
Absolute accuracy (ILED1,
ILED2, ILED3)
ILED_MIN
Minimum LED current (per
string)
50 µA ≤ ILED ≤ 25 mA, 2.7 V ≤ VIN ≤ 5 V (linear
or exponential mode)
–3%
PWM or I2C current control (linear or
exponential mode)
0.1%
3%
50
µA
25
mA
1/3
(0.3%)
LSB
ILED_MAX
Maximum LED current (per
string)
RDNL
IDAC ratio-metric DNL
exponential mode only
VHR
Regulated current sink
headroom voltage
ILED = 25 mA
210
ILED = 5 mA
100
VHR_MIN
Current sink minimum
headroom voltage
ILED = 95% of nominal, ILED = 5 mA
Efficiency
Typical efficiency
VIN = 3.7 V, ILED = 5 mA/string, Typical
Application circuit (3x7 LEDs), (POUT/PIN)
RNMOS
NMOS switch on resistance ISW = 250 mA
ICL
NMOS switch current limit
VOVP
Output overvoltage
protection
2.7 V ≤ VIN ≤ 5 V
ON threshold, 2.7 V ≤ VIN ≤ 5 V
35
Switching frequency
DMAX
Maximum boost duty cycle
Shutdown current
2.7 V ≤ VIN ≤ 5 V, boost
frequency
shift = 0
OCP = 00
575
750
875
OCP = 01
860
1000
1110
OCP = 10
1100
1250
1400
OCP = 11
1350
1500
1650
OVP = 00
16
17
17.5
OVP = 01
23
24
25
OVP = 10
30
31
32
OVP = 11
37
38
39
Boost
frequency
select = 0
Boost
frequency
select = 1
mV
Ω
0.29
0.5
ƒSW
500
525
950
1000
1050
92%
94%
Chip enable bit = 0, SDA = SCL = IN or GND,
2.7 V ≤ VIN ≤ 5 V
1.2
5
135
Hysteresis
mA
V
V
475
Thermal shutdown
TSD
50
87%
OVP
Hysteresis
ISHDN
mV
kHz
µA
°C
15
PWM INPUT
Min ƒPWM
50
Max ƒPWM
tMIN_ON
tMIN_OFF
(1)
Sample rate = 24 MHz
Minimum pulse ON time
Minimum pulse OFF time
50
Hz
kHz
Sample rate = 24 MHz
183.3
Sample rate = 4 MHz
1100
Sample rate = 800 kHz
5500
Sample rate = 24 MHz
183.3
Sample rate = 4 MHz
1100
Sample rate = 800 kHz
5500
ns
ns
LED Current Matching between strings is given as the worst case matching between any two strings. Matching is calculated as ((ILEDX –
ILEDY)/(ILEDX + ILEDY)) × 100.
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Electrical Characteristics (continued)
Minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), typical values
are at TA = 25°C, and VIN = 3.6 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.5
5
ms
11
bits
tSTART-UP
Turnon delay from
shutdown to backlight on
PWM input active, PWM = logic high,HWEN
input from low to high, ƒPWM = 10 kHz (50% duty
cycle)
PWMRES
PWM input resolution
1.6 kHz ≤ ƒPWM ≤ 12 kHz, PWM hysteresis = 00,
PWM sample rate = 11
VIH
Input logic high
HWEN, ASEL, SCL, SDA, PWM inputs
1.25
VIN
VIL
Input logic low
HWEN, ASEL, SCL, SDA, PWM inputs
0
0.4
PWM pulse filter = 00
tGLITCH
PWM input glitch rejection
tPWM_STBY
PWM shutdown period
0
15
PWM pulse filter = 01
60
100
140
PWM pulse filter = 10
90
150
210
PWM pulse filter = 11
120
200
280
Sample rate = 24 MHz
0.54
0.6
0.66
Sample rate = 4 MHz
2.7
3
3.3
22.5
25
27.5
Sample rate = 800 kHz
UNIT
V
ns
ms
6.6 I2C Timing Requirements
See Figure 1
MIN
MAX
UNIT
t1
SCL clock period
2.5
µs
t2
Data in setup time to SCL high
100
ns
t3
Data out stable after SCL low
0
ns
t4
SDA low Setup Time to SCL low (start)
100
ns
t5
SDA high hold time after SCL high (stop)
100
ns
t1
SCL
t5
t4
SDA_IN
t2
SDA_OUT
t3
Figure 1. I2C Timing
6
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6.7 Typical Characteristics
17.3
0.53
MAX -40 degC
MAX 30 degC
MAX 85 degC
MAX 125 degC
17.2
17.1
OVP THRESHOLD (V)
OVP HYSTERESIS (V)
0.525
0.52
0.515
-40 degC
30 degC
0.51
85 degC
17.0
16.9
16.8
16.7
16.6
16.5
16.4
125 degC
16.3
C001
Figure 3. 17-V OVP Threshold
MAX -40 degC
MIN -40 degC
MAX 30 degC
MIN 30 degC
MIN 85 degC
MAX 85 degC
MIN 85 degC
MIN 125 degC
MAX 125 degC
MIN 125 degC
MAX -40 degC
MIN -40 degC
MAX 30 degC
MIN 30 degC
MAX 85 degC
MAX 125 degC
31.3
31.1
24.0
OVP THRESHOLD (V)
OVP THRESHOLD (V)
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
24.1
3.25
VIN (V)
C001
Figure 2. OVP Hysteresis
24.2
3.00
VIN (V)
2.75
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.50
0.505
24.3
MIN -40 degC
MIN 30 degC
MIN 85 degC
MIN 125 degC
23.9
23.8
23.7
23.6
23.5
30.9
30.7
30.5
23.4
23.3
30.3
MIN -40 degC
MAX 30 degC
MIN 30 degC
MAX 85 degC
MIN 85 degC
MAX 125 degC
MIN 125 degC
0.45
0.4
0.35
RDSON (Ohms)
OVP THRESHOLD (V)
5.50
5.25
5.00
C001
Figure 5. 31-V OVP Threshold
MAX -40 degC
38.0
37.8
37.6
37.4
0.3
0.25
0.2
0.15
125 degC
0.1
85 degC
0.05
30 degC
37.2
-40 degC
0
5.50
5.25
5.00
VIN (V)
4.75
4.50
4.25
4.00
3.75
3.50
3.25
Figure 6. 38-V OVP Threshold
3.00
C001
2.75
2.50
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
4.75
4.50
4.25
4.00
3.75
3.50
38.2
3.25
38.4
3.00
VIN (V)
C001
Figure 4. 24-V OVP Threshold
38.6
2.75
2.50
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
C001
Figure 7. RDSON
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Typical Characteristics (continued)
3.5
3
2.5
SWITCHING IQ (mA)
2.5
ISHDN (uA)
3
125 degC
85 degC
30 degC
-40 degC
2
1.5
1
2
1.5
125 degC
1
85 degC
0.5
0.5
0
0
30 degC
-40 degC
45
825
40
775
PEAK CURRENT (A)
VHR_MIN (mV)
875
35
125 degC
85 degC
725
675
-40 degC
30 degC
625
85 degC
30 degC
125 degC
575
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
3.00
20
2.75
2.50
-40 degC
VIN (V)
C001
C001
Open Loop
ILED = 5 mA
Figure 11. 750-mA OCP Current
Figure 10. VHR MIN
1,110
1,400
1,350
PEAK CURRENT (A)
1,060
PEAK CURRENT (A)
5.50
5.25
5.00
4.75
4.50
C001
No Load
Figure 9. IQ Current (Switching)
50
25
4.25
fSW= 1 Mhz
30
4.00
3.75
3.50
3.25
3.00
VIN (V)
C001
Figure 8. Shutdown Current
1,010
960
-40 degC
30 degC
910
85 degC
125 degC
860
1,300
1,250
1,200
-40 degC
30 degC
1,150
85 degC
125 degC
1,100
VIN (V)
C001
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
Open Loop
C001
Open Loop
Figure 12. 1000-mA OCP Current
8
2.75
2.50
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
HWEN = GND
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Figure 13. 1250-mA OCP Current
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Typical Characteristics (continued)
1,650
PEAK CURRENT (A)
1,600
1,550
1,500
1,450
-40 degC
30 degC
1,400
85 degC
125 degC
1,350
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
C001
Open Loop
Figure 14. 1500-mA OCP Current
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7 Detailed Description
7.1 Overview
The LM36923H is an inductive boost plus three current sinks white-LED driver designed for powering from one to
three strings of white LEDs used in display backlighting. The device operates over the 2.5-V to 5.5-V input
voltage range. The 11-bit LED current is set via an I2C interface, via a logic level PWM input, or a combination of
both.
7.2 Functional Block Diagram
SW
Overvoltage
Protection
17V
24V
32V
38V
IN
HWEN
OVP
0.29 Ÿ
Fault Detection
Overvoltage
LED String Short
LED String Open
Current Limit
Thermal Shutdown
LED
Fault
ASEL
OVP
Thermal
Shutdown
135oC
TSD
OCP
Boost Control
Boost Switching
Frequency
1MHz
800kHz
500kHz
400kHz
250kHz
200kHz
Auto
Frequency
Mode
I2C Address
Select
Boost Current
Limit
750mA
1000mA
1250mA
1500mA
SDA
I2C Interface
Min Headroom
Select
SCL
Adaptive
Headroom
Current Sinks
LED1
PWM Sample Rate
800kHz
4MHz
24MHz
PWM
PWM Sampler
11 Bit
Brightness
Code
LED Current Ramping
No ramp
0.125ms/step
0.25ms/step
0.5ms/step
1ms/step
2ms/step
4ms/step
8ms/step
16ms/step
LED Current
Mapping
Exponential
Linear
LED2
LED3
LED String
Enables
GND
10
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7.3 Feature Description
7.3.1 Enabling the LM36923H
The LM36923H has a logic level input HWEN which serves as the master enable/disable for the device. When
HWEN is low the device is disabled, the registers are reset to their default state, the I2C bus is inactive, and the
device is placed in a low-power shutdown mode. When HWEN is forced high the device is enabled, and I2C
writes are allowed to the device.
7.3.1.1 Current Sink Enable
Each current sink in the device has a separate enable input. This allows for a 1-string, 2-string, or 3-string
application. The default is with three strings enabled. Once the correct LED string configuration is programmed,
the device can be enabled by writing the chip enable bit high (register 0x10 bit[0]), and then either enabling PWM
and driving PWM high, or writing a non-zero code to the brightness registers.
The default setting for the device is with the chip enable bit set to 1, PWM input enabled, and the device in linear
mapped mode. Therefore, on power up once HWEN is driven high, the device enters the standby state and
actively monitors the PWM input. After a non-zero PWM duty cycle is detected the LM36923H converts the duty
cycle information to the linearly weighted 11-bit brightness code. This allows for operation of the device in a
stand-alone configuration without the need for any I2C writes. Figure 15 and Figure 16 describe the start-up
timing for operation with both PWM controlled current and with I2C controlled current.
VIN
HWEN
PWM
ILED
tHWEN_PWM
tPWM_DAC
tDD_LED
tDAC_LED
tPWM_STBY
Figure 15. Enabling the LM36923H via PWM
VIN
HWEN
I2C
I2C Registers In
Reset
I2C Data Valid
I2C Brightness
Data Sent
ILED
tHWEN_I2C
tBRT_DAC
tDAC_LED
Figure 16. Enabling the LM36923H via I2C
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Feature Description (continued)
7.3.2
LM36923H Start-Up
The LM36923H can be enabled or disabled in various ways. When disabled, the device is considered shutdown,
and the quiescent current drops to ISHDN. When the device is in standby, it returns to the ISHDN current level
retaining all programmed register values. Table 1 describes the different operating states for the LM36923H.
Table 1. LM36923H Operating Modes
2
(1)
LED CURRENT
LED STRING
ENABLES
0x10 bits[3:1]
PWM INPUT
I C BRIGHTNESS
REGISTERS
0x18 bits[2:0]
0x19 bits[7:0]
BRIGHTNESS
MODE
0x11 bits[6:5]
DEVICE
ENABLE
0x10 bit[0]
XXX
X
XXX
XX
0
0
X
XXX
XX
1
Off, device standby
At least one
enabled
X
0
00
1
Off, device in standby
At least one
enabled
X
Code > 000
00
1
ILED = 50 µA ×
1.003040572Code
See (1)
At least one
enabled
0
XXX
01
1
Off, device in standby
At least one
enabled
PWM Signal
XXX
01
1
ILED = 50 µA ×
1.003040572CodeSee (1)
At least one
enabled
0
XXX
10 or 11
1
At least one
enabled
X
0
10 or 11
1
Off, device in standby
At least one
enabled
PWM Signal
Code > 000
10 or 11
1
ILED = 50 µA ×
1.003040572CodeSee (1)
(EXP MAPPING)
0x11 bit[7] = 1
(LIN MAPPING)
0x11 bit[7] = 0
Off, device disabled
LED = 37.806 µA + 12.195
µA × Code
See (1)
LED = 37.806 µA + 12.195
µA × Code
See (1)
Off, device in standby
LED = 37.806 µA + 12.195
µA × Code
See (1)
Code is the 11-bit code output from the ramper (see Figure 21, Figure 23, Figure 25, Figure 27). This can be the I2C brightness code,
the converted PWM duty cycle or the 11-bit product of both.
7.3.3 Brightness Mapping
There are two different ways to map the brightness code (or PWM duty cycle) to the LED current: linear and
exponential mapping.
7.3.3.1 Linear Mapping
For linear mapped mode the LED current increases proportionally to the 11-bit brightness code and follows the
relationship:
+.'& = 37.806ä# +12.195ä# × %K@A
(1)
This is valid from codes 1 to 2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I2C
brightness code, the digitized PWM duty cycle, or the product of the two.
7.3.3.2 Exponential Mapping
In exponential mapped mode the LED current follows the relationship:
+.'& = 50J# × 1.003040572%K@A
(2)
This results in an LED current step size of approximately 0.304% per code. This is valid for codes from 1 to
2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I2C brightness code, the digitized PWM
duty cycle, or the product of the two. Figure 17 details the LED current exponential response.
The 11-bit (0.304%) per code step is small enough such that the transition from one code to the next in terms of
LED brightness is not distinguishable to the eye. This therefore gives a perfectly smooth brightness increase
between adjacent codes.
12
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LED Current (mA)
25
2.5
0.25
0.025
0
256
512
768
1024
1280
1536
1792
11 Bit Brightness Code
2048
C006
Figure 17. LED Current vs Brightness Code (Exponential Mapping)
7.3.4 PWM Input
The PWM input is a sampled input which converts the input duty cycle information into an 11-bit brightness code.
The use of a sampled input eliminates any noise and current ripple that traditional PWM controlled LED drivers
are susceptible to.
The PWM input uses logic level thresholds with VIH_MIN = 1.25 V and VIL_MAX = 0.4 V. Because this is a sampled
input, there are limits on the max PWM input frequency as well as the resolution that can be achieved.
7.3.4.1 PWM Sample Frequency
There are four selectable sample rates for the PWM input. The choice of sample rate depends on three factors:
1. Required PWM Resolution (input duty cycle to brightness code, with 11 bits max)
2. PWM Input Frequency
3. Efficiency
7.3.4.1.1 PWM Resolution and Input Frequency Range
The PWM input frequency range is 50 Hz to 50 kHz. To achieve the full 11-bit maximum resolution of PWM duty
cycle to the LED brightness code (BRT), the input PWM duty cycle must be ≥ 11 bits, and the PWM sample
period (1/ƒSAMPLE) must be smaller than the minimum PWM input pulse width. Figure 18 shows the possible
brightness code resolutions based on the input PWM frequency. The minimum PWM frequency for each PWM
sample rate is described in PWM Timeout.
12
24MHz
4MHz
800kHz
Maximum Achievable Resolution (bits)
11
10
9
8
7
6
0.1kHz
1.0kHz
10.0kHz
Input PWM Frequency
C001
Figure 18. PWM Sample Rate, Resolution, and PWM Input Frequency
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7.3.4.1.2 PWM Sample Rate and Efficiency
Efficiency is maximized when the lowest ƒSAMPLE is chosen as this lowers the quiescent operating current of the
device. Table 2 describes the typical efficiency tradeoffs for the different sample clock settings.
Table 2. PWM Sample Rate Trade-Offs
PWM SAMPLE RATE
(ƒSAMPLE)
TYPICAL INPUT CURRENT, DEVICE ENABLED
ILED = 10 mA/string, 2 × 7 LEDs
TYPICAL EFFICIENCY
(0x12 Bits[7:6])
ƒSW = 1 MHz
VIN = 3.7 V
0
1.03 mA
89.7%
1
1.05 mA
89.6%
1X
1.35 mA
89.4%
7.3.4.1.2.1 PWM Sample Rate Example
The number of bits of resolution on the PWM input varies according to the PWM Sample rate and PWM input
frequency.
Table 3. PWM Resolution vs PWM Sample Rate
PWM
FREQUENCY
(kHz)
RESOLUTION
(PWM SAMPLE RATE = 800 kHz)
RESOLUTION
(PWM SAMPLE RATE = 4 MHz)
RESOLUTION
(PWM SAMPLE RATE = 24 MHz)
0.4
11
11
11
2
8.6
11
11
12
6.1
8.4
11
7.3.4.2 PWM Hysteresis
To prevent jitter at the input PWM signal from feeding through the PWM path and causing oscillations in the LED
current, the LM36923H offers seven selectable hysteresis settings. The hysteresis works by forcing a specific
number of 11-bit LSB code transitions to occur in the input duty cycle before the LED current changes. Table 4
describes the hysteresis. The hysteresis only applies during the change in direction of brightness currents. Once
the change in direction has taken place, the PWM input must over come the required LSB(s) of the hysteresis
setting before the brightness change takes effect. Once the initial hysteresis has been overcome and the
direction in brightness change remains the same, the PWM to current response changes with no hysteresis.
Table 4. PWM Input Hysteresis
HYSTERESIS SETTING
(0x12 Bits[4:2])
MIN CHANGE IN PWM
PULSE WIDTH (Δt)
REQUIRED TO CHANGE
LED CURRENT, AFTER
DIRECTION CHANGE
(for ƒPWM < 11.7 kHz)
MIN CHANGE IN PWM
DUTY CYCLE (ΔD)
REQUIRED TO CHANGE
LED CURRENT AFTER
DIRECTION CHANGE
EXPONENTIAL MODE
LINEAR MODE
000 (0 LSB)
1/(ƒPWM × 2047)
0.05%
0.30%
0.05%
14
MIN (ΔILED), INCREASE FOR INITIAL CODE
CHANGE
001 (1 LSB)
1/(ƒPWM × 1023)
0.10%
0.61%
0.10%
010 (2 LSBs)
1/(ƒPWM × 511)
0.20%
1.21%
0.20%
011 (3 LSBs)
1/(ƒPWM × 255)
0.39%
2.40%
0.39%
100 (4 LSBs)
1/(ƒPWM × 127)
0.78%
4.74%
0.78%
101 (5 LSBs)
1/(ƒPWM × 63)
1.56%
9.26%
1.56%
110 (6 LSBs)
1/(ƒPWM × 31)
3.12%
17.66%
3.12%
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tJITTER
tJITTER
D/fPWM
1/fPWM
x
x
x
D is tJITTER x fPWM or equal to #/6%¶V = ¨' [ 2048 codes.
For 11-bit resolution, #LSBs is equal to a hysteresis setting of LN(#/6%¶V)/LN(2).
For example, with a tJITTER of 1 µs and a fPWM of 5 kHz, the hysteresis setting should be:
LN(1 µ s x 5 kHz x 2048)/LN(2) = 3.35 (4 LSBs).
Figure 19. PWM Hysteresis Example
7.3.4.3 PWM Step Response
The LED current response due to a step change in the PWM input is approximately 2 ms to go from minimum
LED current to maximum LED current.
7.3.4.4 PWM Timeout
The LM36923H PWM timeout feature turns off the boost output when the PWM is enabled and there is no PWM
pulse detected. The timeout duration changes based on the PWM Sample Rate selected which results in a
minimum supported PWM input frequency. The sample rate, timeout, and minimum supported PWM frequency
are summarized in Table 5.
Table 5. PWM Timeout and Minimum Supported PWM Frequency vs PWM Sample Rate
MINIMUM SUPPORTED PWM
FREQUENCY
SAMPLE RATE
TIMEOUT
0.8 MHz
25 msec
48 Hz
4 MHz
3 msec
400 Hz
24 MHz
0.6 msec
2000 Hz
7.3.5 LED Current Ramping
There are 8 programmable ramp rates available in the LM36923H. These ramp rates are programmable as a
time per step. Therefore, the ramp time from one current set-point to the next, depends on the number of code
steps between currents and the programmed time per step. This ramp time to change from one brightness setpoint (Code A) to the next brightness set-point (Code B) is given by:
¿P = 4=IL_N=PA × :%K@A $ F%K@A# F1;
(3)
For example, assume the ramp is enabled and set to 1 ms per step. Additionally, the brightness code is set to
0x444 (1092d). Then the brightness code is adjusted to 0x7FF (2047d). The time the current takes to ramp from
the initial set-point to max brightness is:
¿P =
1IO
× :0T7(( F 0T444 F 1; = 954IO
OPAL
(4)
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7.3.6 Regulated Headroom Voltage
REGULATED HEADROOM VOLTAGE (V)
In order to optimize efficiency, current accuracy, and string-to-string matching the LED current sink regulated
headroom voltage (VHR) varies with the target LED current. Figure 20 details the typical variation of VHR with
LED current. This allows for increased solution efficiency as the dropout voltage of the LED driver changes.
Furthermore, in order to ensure that both current sinks remain in regulation whenever there is a mismatch in
string voltages, the minimum headroom voltage between VLED1, VLED2, VLED3 becomes the regulation point
for the boost converter. For example, if the LEDs connected to LED1 require 12 V, the LEDs connected to LED2
require 12.5 V , and the LEDs connected to LED3 require 13 V at the programmed current, then the voltage at
LED1 is VHR + 1 V, the voltage at LED2 is VHR + 0.5 V, and the voltage at LED3 is regulated at VHR. In other
words, the boost makes the cathode of the highest voltage LED string the regulation point.
240
220
200
180
160
140
120
100
80
50.0
5.0
0.5
0.1
LED Current (mA)
C001
Figure 20. LM36923H Typical Exponential Regulated Headroom Voltage vs Programmed LED Current
7.4 Device Functional Modes
7.4.1 Brightness Control Modes
The LM36923H has four brightness control modes:
1. I2C Only (brightness mode 00)
2. PWM Only (brightness mode 01)
3. I2C × PWM with ramping only between I2C codes (brightness mode 10)
4. I2C × PWM with ramping between I2C × PWM changes (brightness mode 11)
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Device Functional Modes (continued)
7.4.1.1 I2C Only (Brightness Mode 00)
In brightness control mode 00 the I2C Brightness registers are in control of the LED current, and the PWM input
is disabled. The brightness data (BRT) is the concatenation of the two brightness registers (3 LSBs) and (8
MSBs) (registers 0x18 and 0x19, respectively). The LED current only changes when the MSBs are written,
meaning that to do a full 11-bit current change via I2C, first the 3 LSBs are written and then the 8 MSBs are
written. In this mode the ramper only controls the time from one I2C brightness set-point to the next (see
Figure 21).
VOUT
Boost
Digital Domain
Analog Domain
Min VHR
RAMP_RATE Bits
ILED1
ILED2
ILED3
Driver_1
BRT Code = I2C
Code
I2C Brightness Reg
DACi
Ramper
Mapper
Driver_2
DAC
Driver_3
MAP_MODE
RAMP_EN
Figure 21. Brightness Control 00 (I2C Only)
ILED_t1
Ramp Rate
tRAMP
ILED_t0
t0
t1
2
1.
At time t0 the I C Brightness Code is changed from 0x444 (1092d) to 0x7FF (2047d)
2.
Ramp Rate programmed to 1ms/step
3.
Mapping Mode set to Linear
4.
ILED_t0 = 1092 × 12.213 µA = 13.337 mA
5.
ILED_t1 = 2047 × 12.213 µA = 25 mA
6.
tRAMP = (t1 – t0) = 1ms/step × (2047 – 1092 – 1) = 954 ms
Figure 22. I2C Brightness Mode 00 Example (Ramp Between I2C Code Changes)
7.4.1.2 PWM Only (Brightness Mode 01)
In brightness mode 01, only the PWM input sets the brightness. The I2C code is ignored. The LM36923 samples
the PWM input and determines the duty cycle; this measured duty cycle is translated into an 11-bit digital code.
The resultant code is then applied to the internal ramper (see Figure 23).
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Device Functional Modes (continued)
VOUT
Boost
Digital Domain
Analog Domain
Min VHR
ILED1
RAMP_RATE Bits
ILED2
ILED3
Driver_1
BRT Code =
2047 × Duty Cycle
DACi
PWM Input
PWM Detector
Ramper
Mapper
RAMP_EN
MAP_MODE
Driver_2
DAC
Driver_3
Figure 23. Brightness Control 01 (PWM Only)
ILED_t1
Ramp Rate
tRAMP
ILED_t0
t0
t1
1.
At time t0 the PWM duty cycle changed from 25% to 100%
2.
Ramp Rate programmed to 1 ms/step
3.
Mapping Mode set to Linear
4.
ILED_t0 = 25 mA × 0.25 = 6.25 mA
5.
ILED_t1 = 25 mA × 1 = 25 mA
6.
tRAMP = (t1 – t0) = 1 ms/step × (2047 × 1 – 2047 × 0.25 – 1) = 1534 ms
Figure 24. Brightness Control Mode 01 Example (Ramp Between Duty Cycle Changes)
7.4.1.3 I2C + PWM Brightness Control (Multiply Then Ramp) Brightness Mode 10
In brightness control mode 10 the I2C Brightness register and the PWM input are both in control of the LED
current. In this case the I2C brightness code is multiplied with the PWM duty cycle to produce an 11-bit code
which is then sent to the ramper. In this mode ramping is achieved between I2C and PWM currents (see
Figure 25).
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Device Functional Modes (continued)
VOUT
Digital Domain
Analog Domain
Boost
Min VHR
RAMP_RATE Bits
ILED1
I2C Brightness Reg
Ramper
ILED2
ILED3
Driver_1
BRT Code =
I2C × Duty Cycle
DACi
Mapper
Driver_2
DAC
Driver_3
RAMP_EN
PWM
Detector
PWM Input
MAP_MODE
Figure 25. Brightness Control 10 (I2C + PWM)
ILED_t1
Ramp Rate
tRAMP
ILED_t0
t0
t1
1.
At time t0 the I2C Brightness code changed from 0x444 (1092d) to 0x7FF (2047d)
2.
At time t0 the PWM duty cycle changed from 50% to 75%
3.
Ramp Rate programmed to 1ms/step
4.
Mapping Mode set to Linear
5.
ILED_t0 = 1092 × 12.213 µA × 0.5 = 6.668 mA
6.
ILED_t1 = 2047 × 12.213 µA × 0.75 = 18.75 mA
7.
tRAMP = (t1 – t0) = 1 ms/step × (2047 × 0.75 – 1092 × 0.5 – 1) = 988 ms
Figure 26. Brightness Control Mode 10 Example (Multiply Duty Cycle then Ramp)
7.4.1.4 I2C + PWM Brightness Control (Ramp Then Multiply) Brightness Mode 11
In brightness control mode 11 both the I2C brightness code and the PWM duty cycle control the LED current. In
this case the ramper only changes the time from one I2C brightness code to the next. The PWM duty cycle is
multiplied with the I2C brightness code at the output of the ramper (see Figure 27).
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Device Functional Modes (continued)
VOUT
Boost
Digital Domain
Analog Domain
Min VHR
RAMP_RATE Bits
ILED1
ILED2
ILED3
Driver_1
BRT Code =
I2C × Duty Cycle
I2C Brightness Reg
DACi
Ramper
Mapper
RAMP_EN
MAP_MODE
DAC
Driver_2
Driver_3
PWM Input
PWM Detector
Figure 27. Brightness Control 11 (I2C + PWM)
ILED_t1
ILED_t0+
Ramp
Rate
ILED_t0-
tRAMP
t0
t1
1.
At time t0 the I2C Brightness code changed from 0x444 (1092d) to 0x7FF (2047d)
2.
At time t0 the PWM duty cycle changed from 50% to 75%
3.
Ramp Rate programmed to 1 ms/step
4.
Mapping Mode set to Linear
5.
ILED_t0– = 1092 × 12.213 µA × 0.5 = 6.668 mA
6.
ILED_t0+ = 1092 × 12.213 µA × 0.75 = 10.002 mA
7.
tRAMP = (t1 – t0) = 1 ms/step × (2047 – 1092 – 1) = 954 ms
Figure 28. Brightness Control Mode 11 Example (Ramp Current Then Multiply Duty Cycle)
7.4.2 Boost Switching Frequency
The LM36923H has two programmable switching frequencies: 500 kHz and 1 MHz. These are set via the Boost
Control 1 register 0x13 bit [5]. Once the switching frequency is set, this nominal value can be shifted down by
12% via the boost switching frequency shift bit (register 0x13 bit[6]). Operation at 500 kHz is better suited for
configurations which use a 10-µH inductor or use the auto-frequency mode and switch over to 500 kHz at lighter
loads. Operation at 1 MHz is primarily beneficial at higher output currents, where the average inductor current is
much larger than the inductor current ripple. For maximum efficiency across the entire load current range the
device incorporates an automatic frequency shift mode (see Auto-Switching Frequency).
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Device Functional Modes (continued)
7.4.2.1 Minimum Inductor Select
The LM36923H can use inductors in the range of 4.7 µH to 10 µH. In order to optimize the converter response to
changes in VIN and load, the Min Inductor Select bit (register 0x13 bit[4]) should be selected depending on which
value of inductance is chosen. For 10-µH inductors this bit should be set to 1. For less than 10 µH, this bit should
be set to 0.
7.4.3 Auto-Switching Frequency
To take advantage of frequency vs load dependent losses, the LM36923H has the ability to automatically change
the boost switching frequency based on the magnitude of the load current. In addition to the register
programmable switching frequencies of 500 kHz and 1 MHz, the auto-frequency mode also incorporates a low
frequency selection of 250 kHz. It is important to note that the 250-kHz frequency is only accessible in autofrequency mode and has a maximum boost duty cycle (DMAX) of 50%.
Auto-frequency mode operates by using 2 programmable registers (Auto Frequency High Threshold (register
0x15) and Auto Frequency Low Threshold (0x16)). The high threshold determines the switchover from 1 MHz to
500 kHz. The low threshold determines the switchover from 500 kHz to 250 kHz. Both the High and Low
Threshold registers take an 8-bit code which is compared against the 8 MSB of the brightness register (register
0x19). Table 6 details the boundaries for this mode.
Table 6. Auto-Switching Frequency Operation
BRIGHTNESS CODE MSBs (Register 0x19 bits[7:0])
BOOST SWITCHING FREQUENCY
< Auto Frequency Low Threshold (register 15 Bits[7:0])
250 kHz (DMAX = 50%)
> Auto Frequency Low Threshold (Register 15 Bits[7:0]) or < Auto
Frequency High Threshold (Register 14 Bits[7:0])
500 kHz
≥ Auto Frequency High Threshold (register 14 Bits[7:0])
1 MHz
Automatic-frequency mode is enabled whenever there is a non-zero code in either the Auto-Frequency High or
Auto-Frequency Low registers. To disable the auto-frequency shift mode, set both registers to 0x00. When
automatic-frequency select mode is disabled, the switching frequency operates at the programmed frequency
(Register 0x13 bit[5]) across the entire LED current range. Table 7 provides a guideline for selecting the autofrequency 250-kHz threshold setting; the actual setting needs to be verified in the application.
Table 7. Auto Frequency 250-kHz Threshold Settings
CONDITION
(Vƒ = 3.2 V, ILED = 25 mA)
INDUCTOR (µH)
RECOMMENDED AUTO FREQUENCY
LOW THRESHOLD MAXIMUM VALUE
(NO SHIFT)
OUTPUT POWER AT AUTO
FREQUENCY SWITCHOVER
(W)
3 × 4 LEDs
10
0x17
0.079
3 × 5 LEDs
10
0x15
0.089
3 × 6 LEDs
10
0x13
0.097
3 × 7 LEDs
10
0x11
0.101
3 × 8 LEDs
10
0x0f
0.102
7.4.4
I2C Address Select (ASEL)
The LM36923H provides two I2C slave address options. When ASEL = GND the slave address is set to 0x36.
When ASEL = VIN the slave address is set to 0x37. This static input pin is read on power up (VIN > 1.8 V and
HWEN > VIH) and must not be changed after power up.
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7.4.5 Fault Protection/Detection
7.4.5.1 Overvoltage Protection (OVP)
The LM36923H provides four OVP thresholds (17 V, 24 V, 32 V, and 38 V). The OVP circuitry monitors the boost
output voltage (VOUT) and protects OUT and SW from exceeding safe operating voltages in case of open load
conditions or in the event the LED string voltage requires more voltage than the programmed OVP setting. The
OVP thresholds are programmed in register 13 bits[3:2]. The operation of OVP differentiates between two
overvoltage conditions (see Case 1 OVP Fault Only (OVP Threshold Hit and All Enabled Current Sink Inputs >
40 mV) , Case 1 OVP Fault Only (OVP Threshold Hit and All Enabled Current Sink Inputs > 40 mV) , and Case
2b OVP Fault and Open LED String Fault (OVP Threshold Duration and Any Enabled Current Sink Input ≤ 40
mV) ).
7.4.5.1.1 Case 1 OVP Fault Only (OVP Threshold Hit and All Enabled Current Sink Inputs > 40 mV)
In steady-state operation with VOUT near the OVP threshold a rapid change in VIN or brightness code can result in
a momentary transient excursion of VOUT above the OVP threshold. In this case the boost circuitry is disabled
until VOUT drops below OVP – hysteresis (1 V). Once this happens the boost is re-enabled and steady state
regulation continues. If VOUT remains above the OVP threshold for > 1 ms the OVP Flag is set (register 0x1F
bit[0]).
7.4.5.1.2 Case 2a OVP Fault and Open LED String Fault (OVP Threshold Occurrence and Any Enabled Current Sink
Input ≤ 40 mV)
When any of the enabled LED strings is open the boost converter tries to drive VOUT above OVP and at the same
time the open string(s) current sink headroom voltage(s) (LED1, LED2, LED3) drop to 0. When the LM36923H
detects three occurrences of VOUT > OVP and any enabled current sink input (VLED1 or VLED2, VLED3) ≤ 40 mV,
the OVP Fault flag is set (register 0x1F bit[0]), and the LED Open Fault flag is set (register 0x1F bit[4]).
7.4.5.1.3 Case 2b OVP Fault and Open LED String Fault (OVP Threshold Duration and Any Enabled Current Sink
Input ≤ 40 mV)
When any of the enabled LED strings is open the boost converter tries to drive VOUT above OVP and at the same
time the open string(s) current sink headroom voltage(s) (LED1, LED2, LED3) drop to 0. When the LM36923H
detects VOUT > OVP for > 1 msec and any enabled current sink input (VLED1 or VLED2, VLED3) ≤ 40 mV, the OVP
Fault flag is set (register 0x1F bit[0]), and the LED Open Fault flag is set (register 0x1F bit[4]).
7.4.5.1.4 OVP/LED Open Fault Shutdown
The LM36923H has the option of shutting down the device when the OVP flag is set. This option can be enabled
or disabled via register 0x1E bit[0]. When the shutdown option is disabled the fault flag is a report only. When the
device is shut down due to an OVP/LED String Open fault, the fault flags register must be read back before the
LM36923H can be re-enabled.
7.4.5.1.5 Testing for LED String Open
The procedure for detecting an open in a LED string is:
• Apply power the the LM36923H.
• Enable all LED strings (Register 0x10 = 0x0F).
• Set maximum brightness (Register 0x18 = 0x07 and Register 0x19 = 0xFF).
• Set the brightness control (Register 0x11 = 0x00).
• Open LED1 string.
• Wait 4 msec.
• Read LED open fault (Register 0x1F).
• If bit[4] = 1, then a LED open fault condition has been detected.
• Connect LED1 string.
• Repeat the procedure for the other LED strings.
22
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7.4.5.2 Voltage Limitations on LED1, LED2, and LED3
The inputs to current sinks LED1, LED2 , and LED3 are rated for 30 V (absolute maximum voltage). This is lower
than the boost output capability as set by the OVP threshold (maximum specification) of 39 V. To ensure that the
current sink inputs remain below their absolute maximum rating, the LED configuration between LED1 or LED2
or LED3 must not have a voltage difference between strings so that VLED1/2/3 have a voltage greater than 30 V.
7.4.5.3 LED String Short Fault
The LM36923H can detect an LED string short fault. This happens when the voltage between VIN and any
enabled current sink input has dropped below (1.5 V). This test can only be performed on one LED string at a
time. Performing this test with more than one LED string enabled can result in a faulty reading. The procedure for
detecting a short in a LED string is:
• Apply power the LM36923H.
• Enable only LED1 string (Register 0x10 = 0x03).
• Enable short fault (Register 0x1E = 0x01.
• Set maximum brightness (Register 0x18 = 0x07 and Register 0x19 = 0xFF).
• Set the brightness control (Register 0x11 = 0x00).
• Wait 4 msec.
• Read LED short fault (Register 0x1F).
• If bit[3] = 1, then a LED short fault condition has been detected.
• Set chip enable and LED string enable low (Register 0x10 = 0x00).
• Repeat the procedure for the other LED strings.
7.4.5.4 Overcurrent Protection (OCP)
The LM36923H has four selectable OCP thresholds (750 mA, 1000 mA, 1250 mA, and 1500 mA). These are
programmable in register 0x13 bits[1:0]. The OCP threshold is a cycle-by-cycle current limit and is detected in
the internal low-side NFET. Once the threshold is hit the NFET turns off for the remainder of the switching period.
7.4.5.4.1 OCP Fault
If enough overcurrent threshold events occur, the OCP Flag (register 0x1F bit[1]) is set. To avoid transient
conditions from inadvertently setting the OCP Flag, a pulse density counter monitors OCP threshold events over
a 128-µs period. If 8 consecutive 128-µs periods occur where the pulse density count has found two or more
OCP events,then the OCP Flag is set.
During device start-up and during brightness code changes, there is a 4-ms blank time where OCP events are
ignored. As a result, if the device starts up in an overcurrent condition there is an approximate 5-ms delay before
the OCP Flag is set.
7.4.5.4.2 OCP Shutdown
The LM36923H has the option of shutting down the device when the OCP flag is set. This option can be enabled
or disabled via register 0x1E bit[1]. When the shutdown option is disabled, the fault flag is a report only. When
the device is shut down due to an OCP fault, the fault flags register must be read back before the LM36923H can
be re-enabled.
7.4.5.5 Device Overtemperature
Thermal shutdown (TSD) is triggered when the device die temperature reaches 135˚C. When this happens the
boost stops switching, and the TSD Flag (register 0x1F bit[2]) is set. The boost automatically starts up again
when the die temperature cools down to 120°C.
7.4.5.5.1 Overtemperature Shutdown
The LM36923H has the option of shutting down the device when the TSD flag is set. This option can be enabled
or disabled via register 0x1E bit[2]. When the shutdown option is disabled the fault flag is a report only. When the
device is shutdown due to a TSD fault, the Fault Flags register must be read back before the LM36923H can be
re-enabled.
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7.5 Programming
7.5.1 I2C Interface
7.5.1.1 Start and Stop Conditions
The LM36923H is configured via an I2C interface. START (S) and STOP (P) conditions classify the beginning
and the end of the I2C session Figure 29. A START condition is defined as SDA transitioning from HIGH to LOW
while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH.
The I2C master always generates the START and STOP conditions. The I2C bus is considered busy after a
START condition and free after a STOP condition. During the data transmission the I2C master can generate
repeated START conditions. A START and a repeated START conditions are equivalent function-wise. The data
on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can
only be changed when SCL is LOW.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 29. I2C Start and Stop Conditions
7.5.1.2 I2C Address
The 7-bit chip address for the LM36923 is 0x36 with ASEL connected to GND and 0x37 with ASEL connected to
a logic high voltage. After the START condition the I2C master sends the 7-bit chip address followed by an eighth
bit read or write (R/W). R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following
the chip address selects the register address to which the data is written. The third byte contains the data for the
selected register.
7.5.1.3 Transferring Data
Every byte on the SDA line must be eight bits long with the most significant bit (MSB) transferred first. Each byte
of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse, (9th clock pulse),
is generated by the master. The master then releases SDA (HIGH) during the 9th clock pulse. The LM36923H
pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each
byte has been received.
7.5.1.4 Register Programming
For glitch free operation, the following bits and/or registers should only be programmed while the LED Enable
bits are 0 (Register 0x10, Bit [3:1] = 0) and Device Enable bit is 1 (Register 0x10, Bit[0] = 1) :
1. Register 0x11 Bit[7] (Mapping Mode)
2. Register 0x11 Bits[6:5] (Brightness Mode)
3. Register 0x11 Bit[4] (Ramp Enable)
4. Register 0x11 Bit[3:1] (Ramp Rate)
5. Register 0x12 Bits[7:6] (PWM Sample Rate)
6. Register 0x12 Bits[5] (PWM Polarity)
7. Register 0x12 Bit[3:2] (PWM Hysteresis)
8. Register 0x12 Bit[3:2] (PWM Pulse Filter)
9. Register 0x15 (auto frequency high threshold)
10. Register 0x16 (auto frequency low threshold)
24
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7.6 Register Maps
Note: Read of reserved (R) or write-only register returns 0.
Table 8. Revision (0x00)
Bits [7:4]
Bits [3:0]
R
Revision Code
Table 9. Software Reset (0x01)
Software Reset
Bit [0]
Bits [7:1]
R
0 = Normal Operation
1 = Device Reset (automatically resets back to 0)
Table 10. Enable (0x10)
LED2
Enable
Bit [2]
LED3 Enable
Bit [3]
Bits [7:4]
R
0 = Disabled
1 = Enabled
(Default)
LED1
Enable
Bit [1]
Device
Enable
Bit [0]
0=
0=
0=
Disabled
Disabled
Disabled
1 = Enabled 1 = Enabled 1 = Enabled
(Default)
(Default)
(Default)
Table 11. Brightness Control (0x11)
Mapping Mode
Bit [7]
0 = Linear (default)
1 = Exponential
Brightness
Mode
Bits [6:5]
00 = Brightness
Register Only
01 = PWM Duty
Cycle Only
10 = Multiply
Then Ramp
(Brightness
Register ×
PWM)
11 = Ramp
Then Multiply
(Brightness
Register ×
PWM) (default)
Ramp Enable
Bits [4]
Ramp Rate
Bit [3:1]
0 = Ramp Disabled (default)
1 = Ramp Enabled
000 = 0.125
ms/step
(default)
001 = 0.250
ms/step
010 = 0.5
ms/step
011 = 1
ms/step
100 = 2
ms/step
101 = 4
ms/step
110 = 8
ms/step
111 = 16
ms/step
Bits [0]
R
Table 12. PWM Control (0x12)
PWM Sample Rate
Bit [7:6]
PWM Input
Polarity
Bit [5]
00 = 800 kHz
01 = 4 MHz
1X = 24 MHz (default)
0 = Active Low
1 = Active High
(default)
PWM Hysteresis
Bits [4:2]
000 = None
001 = 1 LSB
010 = 2 LSBs
011 = 3 LSBs
100 = 4 LSBs (default)
101 = 5 LSBs
110 = 6 LSBs
111 = N/A
PWM Pulse Filter
Bit [1:0]
00 = No Filter
01 = 100 ns
10 = 150 ns
11 = 200 ns (default)
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Table 13. Boost Control 1 (0x13)
Reserved
Bit [7]
N/A
Boost Switching
Frequency Shift
Bit [6]
Boost Switching Frequency
Select
Bit [5]
0 = –12% Shift
1 =No Shift (default)
0 = 500 kHz
1 = 1 MHz (default)
Minimum
Inductor
Select
Bit [4]
Overvoltage
Protection
(OVP)
Bits [3:2]
Current Limit
(OCP)
Bits [1:0]
0 = 4.7 µH
(default)
1 = 10 µH
00 = 17 V
01 = 24 V
10 = 31 V
11 = 38 V
(default)
00 = 750 mA
01 = 1000 mA
10 = 1250 mA
11 = 1500 mA
(default)
Table 14. Auto Frequency High Threshold (0x15)
Auto Frequency High Threshold (500 kHz to 1000 kHz)
Bits [7:0]
Compared against the 8 MSBs of 11-bit brightness code (default = 00000000).
Table 15. Auto Frequency Low Threshold (0x16)
Auto Frequency High Threshold (250 kHz to 500 kHz)
Bits [7:0]
Compared against the 8 MSBs of 11-bit brightness code (default = 00000000).
Table 16. Brightness Register LSBs (0x18)
Bits [7:3]
I2C Brightness Code (LSB)
Bits [2:0]
R
This is the lower 3 bits of the 11-bit brightness code (default = 111).
Table 17. Brightness Register MSBs (0x19)
I2C Brightness Code (MSB)
Bits [7:0]
This is the upper 8 bits of the 11-bit brightness code (default = 11111111).
Table 18. Fault Control (0x1E)
Reserved
Bits [7:4]
R
LED Short
Fault Enable
Bit [3]
0 = LED Short
Fault Detection
is disabled
(default).
1 = LED Short
Fault Detection
is enabled
TSD Shutdown Disable
Bit [2]
0 = When the TSD Flag is set,
the device is forced into
shutdown.
1 = No shutdown (default)
OCP
Shutdown
Disable
Bit [1]
0 = When the
OCP Flag is
set, the device
is forced into
shutdown.
1 = No
shutdown
(default)
OVP/LED
Open
Shutdown
Disable
Bit [0]
0 = When
the OVP
Flag is set,
the device
is forced
into
shutdown.
1 = No
shutdown
(default)
Table 19. Fault Flags (0x1F)
Reserved
Bits [7:5]
R
26
LED Open
Fault
Bit [4]
LED Short
Fault
Bit [3]
TSD Fault
Bit [2]
OCP Fault
Bit [1]
1 = LED
String Open
Fault
1 = LED
Short Fault
1 = Thermal Shutdown
Fault
1 = Current Limit
Fault
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OVP
Fault
Bit [0]
1=
Output
Overvolta
ge Fault
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM36923H provides a complete high-performance LED lighting solution for mobile handsets. The LM36923H
is highly configurable and can support multiple LED configurations.
8.2 Typical Application
Figure 30. LM36923H Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Minimum input voltage (VIN)
2.7 V
LED parallel/series configuration
3×5
LED maximum forward voltage (Vƒ)
3.2 V
Efficiency
82%
The number of LED strings, number of series LEDs, and minimum input voltage are needed in order to calculate
the peak input current. This information guides the designer to make the appropriate inductor selection for the
application. The LM36923H boost converter output voltage (VOUT) is calculated: number of series LEDs × Vƒ +
0.23 V. The LM36923H boost converter output current (IOUT) is calculated: number of parallel LED strings × 25
mA. The LM36923H peak input current is calculated using Equation 5.
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8.2.2 Detailed Design Procedure
Table 20. Typical Application Component List
CONFIGURATION
L1
D1
COUT
3p7s, 3p8s
VLF504012MT-100M
VLF504012MT-150M
NSR0530P2T5G
C2012X7R1H105K085AC
3p6s
VLF504012MT-220M
NSR0530P2T5G
C2012X7R1H105K085AC
3p5s
VLF403210MT-100M
NSR0530P2T5G
C2012X7R1H105K085AC
3p4s
VLF302510MT-100M
NSR0530P2T5G
C2012X7R1H105K085AC
8.2.2.1 Component Selection
8.2.2.1.1 Inductor
The LM36923H requires a typical inductance in the range of 4.7 µH to 10 µH. When selecting the inductor,
ensure that the saturation rating for the inductor is high enough to accommodate the peak inductor current of the
application (IPEAK) given in the inductor datasheet. The peak inductor current occurs at the maximum load
current, the maximum output voltage, the minimum input voltage, and the minimum switching frequency setting.
Also, the peak current requirement increases with decreasing efficiency. IPEAK can be estimated using
Equation 5:
+2'#- =
8176 × +176
8+0
8+0 × K
+
× l1 +
p
8+0 × K
2 × B59 × .
8176
(5)
Also, the peak current calculated above is different from the peak inductor current setting (ISAT). The NMOS
switch current limit setting (ICL_MIN) must be greater than IPEAK from Equation 5 above.
8.2.2.1.2 Output Capacitor
The LM36923H requires a ceramic capacitor with a minimum of 0.4 µF of capacitance at the output, specified
over the entire range of operation. This ensures that the device remains stable and oscillation free. The 0.4 µF of
capacitance is the minimum amount of capacitance, which is different than the value of capacitor. Capacitance
would take into account tolerance, temperature, and DC voltage shift.
Table 21 lists possible output capacitors that can be used with the LM36923H. Figure 31 shows the DC bias of
the four TDK capacitors. The useful voltage range is determined from the effective output voltage range for a
given capacitor as determined by Equation 6:
&% 8KHP=CA &AN=PEJC R
0.38µ(
:1 F 6KH; × :1 F 6AIL_?K;
(6)
Table 21. Recommended Output Capacitors
NOMINAL
CAPACITANCE
(µF)
TOLERANCE (%)
TEMPERATURE
COEFFICIENT (%)
RECOMMENDED MAX
OUTPUT VOLTAGE
(FOR SINGLE
CAPACITOR)
50
1
±10
±15
22
50
2.2
±10
±15
24
0603
35
2.2
±10
±15
12
0603
50
1
±10
±15
15
PART NUMBER
MANUFACTURER
CASE
SIZE
VOLTAGE
RATING (V)
C2012X5R1H105K085AB
TDK
0805
C2012X5R1H225K085AB
TDK
0805
C1608X5R1V225K080AC
TDK
C1608X5R1H105K080AB
TDK
For example, with a 10% tolerance, and a 15% temperature coefficient, the DC voltage derating must be ≥ 0.38 /
(0.9 × 0.85) = 0.5 µF. For the C1608X5R1H225K080AB (0603, 50-V) device, the useful voltage range occurs up
to the point where the DC bias derating falls below 0.523 µF, or around 12 V. For configurations where VOUT is >
15 V, two of these capacitors can be paralleled, or a larger capacitor such as the C2012X5R1H105K085AB must
be used.
28
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Capacitance (µF)
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2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
C2012X5R1H105K085AB
C2012X5R1H225K085AB
C1608X5R1V225K080AC
C1608X5R1H105K080AB
0
2
4
6
8
10
12
14
16
18
20
22
24
26
DC Bias
28
C006
Figure 31. DC Bias Derating for 0805 Case Size and
0603 Case Size 35-V and 50-V Ceramic Capacitors
8.2.2.1.3 Input Capacitor
The input capacitor in a boost is not as critical as the output capacitor. The input capacitor primary function is to
filter the switching supply currents at the device input and to filter the inductor current ripple at the input of the
inductor. The recommended input capacitor is a 2.2-µF ceramic (0402, 10-V device) or equivalent.
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8.2.3 Application Curves
L1 = 4.7 µH (VLF504012-4R7M) or 10 µH (VLF504015-100M) as noted in graphs, D1 = NSR240P2T5G, LEDs are Samsung
SPMWHT325AD5YBTMS0, temperature = 25°C, VIN = 3.7 V, unless otherwise noted.
Three String, AF Enabled, 10 uH, 3.7V
95%
90%
90%
85%
85%
BOOST EFFICIENCY
BOOST EFFICIENCY
Two String, AF Enabled -12%, 10 uH, 3.7V
95%
80%
75%
2p4s
2p6s
70%
2p8s
65%
2p10s
2p12s
60%
75%
3p8s
65%
BOOST EFFICIENCY
BOOST EFFICIENCY
80%
2p4s
2p6s
2p8s
2p10s
2p12s
75%
3p4s
3p6s
70%
3p8s
65%
3p10s
3p12s
BOOST EFFICIENCY
80%
Two String, 443kHz, 10 uH, 3.7V
75%
2p4s
70%
2p6s
2p8s
65%
2p10s
3p10s
2p12s
60%
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
C001
Figure 36. Boost Efficiency vs Series LEDs
80
80%
3p12s
70
60
85%
3p8s
50
85%
3p6s
40
90%
3p4s
C001
Figure 35. Boost Efficiency vs Series LEDs
90%
75%
30
20
10
0
60
50
40
30
20
10
0
LED CURRENT (mA)
C001
Three String, 443kHz, 10 uH, 3.7V
BOOST EFFICIENCY
80%
60%
Figure 34. Boost Efficiency vs Series LEDs
LED CURRENT (mA)
80
85%
60%
70
60
50
40
30
85%
LED CURRENT (mA)
30
20
90%
65%
10
0
90%
70%
C001
Three String, AF Enabled -12%, 10 uH, 3.7V
95%
60%
3p12s
Figure 33. Boost Efficiency vs Series LEDs
Two String, AF Enabled, 10 uH, 3.7V
65%
3p10s
LED CURRENT (mA)
95%
70%
3p6s
C001
Figure 32. Boost Efficiency vs Series LEDs
75%
3p4s
70%
60%
60
50
40
30
20
10
0
LED CURRENT (mA)
80%
C001
Figure 37. Boost Efficiency vs Series LEDs
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L1 = 4.7 µH (VLF504012-4R7M) or 10 µH (VLF504015-100M) as noted in graphs, D1 = NSR240P2T5G, LEDs are Samsung
SPMWHT325AD5YBTMS0, temperature = 25°C, VIN = 3.7 V, unless otherwise noted.
90%
85%
85%
80%
80%
BOOST EFFICIENCY
BOOST EFFICIENCY
Three String, 500kHz, 10 uH, 3.7V
90%
75%
3p4s
70%
3p6s
3p8s
65%
3p12s
2p4s
70%
2p6s
2p8s
65%
2p10s
BOOST EFFICIENCY
85%
3p10s
3p12s
80%
75%
2p8s
65%
BOOST EFFICIENCY
3p10s
3p12s
C001
Two String, 1Mhz, 10 uH, 3.7V
80%
75%
2p4s
2p6s
70%
2p8s
65%
2p10s
2p12s
60%
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
C001
Figure 42. Boost Efficiency vs Series LEDs
60
85%
3p8s
50
85%
3p6s
40
90%
3p4s
30
90%
80%
20
10
80
70
60
50
40
30
20
10
0
95%
LED CURRENT (mA)
2p12s
Figure 41. Boost Efficiency vs Series LEDs
Three String, 1Mhz, 10 uH, 3.7V
60%
2p10s
LED CURRENT (mA)
95%
65%
2p6s
C001
Figure 40. Boost Efficiency vs Series LEDs
70%
2p4s
70%
60%
LED CURRENT (mA)
75%
Two String, 887kHz, 10 uH, 3.7V
0
60%
60
85%
3p8s
50
90%
65%
40
90%
3p6s
30
95%
3p4s
20
Three String, 887kHz, 10 uH, 3.7V
80%
C001
Figure 39. Boost Efficiency vs Series LEDs
95%
70%
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
C001
Figure 38. Boost Efficiency vs Series LEDs
75%
2p12s
60%
LED CURRENT (mA)
BOOST EFFICIENCY
75%
3p10s
60%
BOOST EFFICIENCY
Two String, 500kHz, 10 uH, 3.7V
C001
Figure 43. Boost Efficiency vs Series LEDs
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L1 = 4.7 µH (VLF504012-4R7M) or 10 µH (VLF504015-100M) as noted in graphs, D1 = NSR240P2T5G, LEDs are Samsung
SPMWHT325AD5YBTMS0, temperature = 25°C, VIN = 3.7 V, unless otherwise noted.
Three String, 443kHz, 4.7 uH, 3.7V
90%
85%
BOOST EFFICIENCY
85%
BOOST EFFICIENCY
Two String, 443kHz, 4.7 uH, 3.7V
90%
80%
75%
3p8s
3p6s
70%
80%
75%
2p12s
2p10s
2p8s
70%
2p6s
3p4s
C001
Figure 45. Boost Efficiency vs Series LEDs
Two String, 500kHz, 4.7 uH, 3.7V
90%
85%
BOOST EFFICIENCY
85%
80%
75%
3p8s
3p6s
70%
80%
75%
2p12s
2p10s
2p8s
70%
2p6s
3p4s
65%
50
40
30
20
C001
Figure 47. Boost Efficiency vs Series LEDs
Three String, 887kHz, 4.7 uH, 3.7V
90%
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
C001
Figure 46. Boost Efficiency vs Series LEDs
Two String, 887kHz, 4.7 uH, 3.7V
90%
85%
BOOST EFFICIENCY
85%
BOOST EFFICIENCY
2p4s
65%
LED CURRENT (mA)
80%
75%
3p10s
3p8s
70%
3p6s
3p4s
75%
2p12s
2p10s
2p8s
70%
2p6s
2p4s
50
40
30
20
LED CURRENT (mA)
C001
Figure 48. Boost Efficiency vs Series LEDs
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
80%
65%
65%
32
50
40
30
20
LED CURRENT (mA)
C001
Three String, 500kHz, 4.7 uH, 3.7V
90%
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
Figure 44. Boost Efficiency vs Series LEDs
BOOST EFFICIENCY
2p4s
65%
65%
C001
Figure 49. Boost Efficiency vs Series LEDs
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L1 = 4.7 µH (VLF504012-4R7M) or 10 µH (VLF504015-100M) as noted in graphs, D1 = NSR240P2T5G, LEDs are Samsung
SPMWHT325AD5YBTMS0, temperature = 25°C, VIN = 3.7 V, unless otherwise noted.
Three String, 1Mhz, 4.7 uH, 3.7V
90%
85%
85%
BOOST EFFICIENCY
BOOST EFFICIENCY
Two String, 1Mhz, 4.7 uH, 3.7V
90%
80%
75%
3p10s
3p8s
70%
3p6s
80%
75%
2p12s
2p10s
2p8s
70%
2p6s
3p4s
65%
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
LED CURRENT (mA)
2p4s
65%
LED CURRENT (mA)
C001
Figure 50. Boost Efficiency vs Series LEDs
C001
Figure 51. Boost Efficiency vs Series LEDs
100
25
Exponential
Linear
23
20
LED CURRENT (mA)
CURRENT (mA)
10
1
0.1
18
15
13
10
8
5
3
0
0.80
0.60
Matching(1-2)
Matching(1-3)
Matching (2-3)
0.40
MATCHING (%)
0.40
MATCHING (%)
2048
1792
1536
1280
1024
C001
Figure 53. LED Current vs Brightness Code
Matching(1-2)
Matching(1-3)
Matching (2-3)
0.60
768
BRIGHTNESS CODE
C001
Figure 52. LED Current vs Brightness Code (Exponential
Mapping)
0.80
512
BRIGHTNESS CODE
256
2048
1920
1792
1664
1536
1408
1280
1152
1024
896
768
640
512
384
256
128
0
0
0.01
0.20
0.00
-0.20
0.20
0.00
-0.20
-0.40
-0.40
-0.60
-0.60
-0.80
-0.80
2048
1920
1792
1664
1536
1408
1280
1152
1024
896
768
640
512
384
256
128
0
2048
1920
1792
1664
1536
1408
1280
1152
1024
896
768
640
512
384
256
128
0
BRIGHTNESS CODE
BRIGHTNESS CODE
C001
Figure 54. LED Matching (Exponential Mapping)
C001
Figure 55. LED Matching (Linear Mapping)
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L1 = 4.7 µH (VLF504012-4R7M) or 10 µH (VLF504015-100M) as noted in graphs, D1 = NSR240P2T5G, LEDs are Samsung
SPMWHT325AD5YBTMS0, temperature = 25°C, VIN = 3.7 V, unless otherwise noted.
1.80
Accuracy I1
Accuracy I2
Accuracy I3
1.80
1.60
1.40
1.40
1.20
1.00
0.80
0.60
1.20
1.00
0.80
0.60
C001
Figure 57. LED Current Accuracy
Exponential Mapping, 25C, 3.7V
Linear Mapping, 25C, 3.7V
0.35
VH1
VH2
VH1
VH2
0.30
VH3
VH3
0.25
0.25
HEADROOM VOLTAGE (V)
HEADROOM VOLTAGE (V)
2048
1792
1536
1280
1024
768
512
BRIGHTNESS CODE
C001
Figure 56. LED Current Accuracy
0.30
256
BRIGHTNESS CODE
0
2048
1792
1536
1280
1024
0.00
768
0.20
0.00
512
0.20
256
0.40
0
0.40
0.35
Accuracy I1
Accuracy I2
Accuracy I3
1.60
ACCURACY (%)
ACCURACY (%)
Linear Mapping, 25C, 3.7V
Exponential Mapping, 25C, 3.7V
2.00
0.20
0.15
0.10
0.05
0.00
0.10
0.05
2048
1792
1536
1280
1024
1.6
768
512
256
0
BRIGHTNESS CODE
C001
Figure 58. LED Headroom Voltage (Mis-Matched Strings)
C001
Figure 59. LED Headroom Voltage (Mis-Matched Strings)
24Mhz
4Mhz
0.8Mhz
1.4
QUIESCENT CURRENT (mA)
0.15
0.00
2048
1792
1536
1280
1024
768
512
256
0
BRIGHTNESS CODE
0.20
1.2
1.0
0.8
0.6
0.4
5.50
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
VIN (V)
C001
Figure 60. Current vs PWM Sample Frequency
34
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9 Power Supply Recommendations
9.1 Input Supply Bypassing
The LM36923H is designed to operate from an input supply range of 2.5 V to 5.5 V. This input supply should be
well regulated and be able to provide the peak current required by the LED configuration and inductor selected
without voltage drop under load transients (start-up or rapid brightness change). The resistance of the input
supply rail should be low enough such that the input current transient does not cause the LM36923H supply
voltage to droop more than 5%. Additional bulk decoupling located close to the input capacitor (CIN) may be
required to minimize the impact of the input supply rail resistance.
10 Layout
10.1 Layout Guidelines
The inductive boost converter of the LM36923H device detects a high switched voltage (up to VOVP) at the SW
pin, and a step current (up to ICL) through the Schottky diode and output capacitor each switching cycle. The high
switching voltage can create interference into nearby nodes due to electric field coupling (I = CdV/dt). The large
step current through the diode and the output capacitor can cause a large voltage spike at the SW pin and the
OUT pin due to parasitic inductance in the step current conducting path (V = Ldi/dt). Board layout guidelines are
geared towards minimizing this electric field coupling and conducted noise. Figure 61 highlights these two noisegenerating components.
Voltage Spike
VOUT + VF Schottky
Pulsed voltage at SW
IPEAK
Current through
Schottky and
COUT
IAVE = IIN
Current through
Inductor
Parasitic
Circuit Board
Inductances
Affected Node
due to Capacitive Coupling
LCD Display
Cp1
L
Lp1
D1
Lp2
Up to 38V
2.5 V to 5.5 V
COUT
IN
SW
Lp3
CIN
LM36923H
OUT
LED1
LED2
LED3
GND
Figure 61. SW Pin Voltage (High Dv/Dt) and Current Through Schottky Diode and COUT (High Di/Dt)
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Layout Guidelines (continued)
The following list details the main (layout sensitive) areas of the inductive boost converter of the LM36923 device
in order of decreasing importance:
• Output Capacitor
– Schottky Cathode to COUT+
– COUT– to GND
• Schottky Diode
– SW pin to Schottky Anode
– Schottky Cathode to COUT+
• Inductor
– SW Node PCB capacitance to other traces
• Input Capacitor
– CIN+ to IN pin
10.1.1 Boost Output Capacitor Placement
Because the output capacitor is in the path of the inductor current discharge path it detects a high-current step
from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series
path from the cathode of the diode through COUT and back into the GND pin of the LM36923H device GND pin
contributes to voltage spikes (VSPIKE = LP_ × di/dt) at SW and OUT. These spikes can potentially over-voltage the
SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close to the cathode of the
Schottky diode as possible, and COUT− must be connected as close to the GND pin of the device as possible.
The best placement for COUT is on the same layer as the LM36923H in order to avoid any vias that can add
excessive series inductance.
10.1.2 Schottky Diode Placement
In the boost circuit of the LM36923H device the Schottky diode is in the path of the inductor current discharge.
As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off and the
diode turns on. Any inductance in series with the diode causes a voltage spike (VSPIKE = LP_ × di/dt) at SW and
OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor and
into GND. Connecting the anode of the diode as close to the SW pin as possibleand the cathode of the diode as
close to COUT as possible reduces the inductance (LP_) and minimize these voltage spikes.
10.1.3 Inductor Placement
The node where the inductor connects to the LM36923H device SW pin has 2 issues. First, a large switched
voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be
capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces
connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this
path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.
To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection
must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high
impedance nodes that are more susceptible to electric field coupling must be routed away from SW and not
directly adjacent or beneath. This is especially true for traces such as SCL, SDA, HWEN, ASEL, and PWM. A
GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.
Lastly, limit the trace resistance of the VIN to inductor connection and from the inductor to SW connection by use
of short, wide traces.
10.1.4 Boost Input Capacitor Placement
For the LM36923H boost converter, the input capacitor filters the inductor current ripple and the internal
MOSFET driver currents during turnon of the internal power switch. The driver current requirement can range
from 50 mA at 2.7 V to over 200 mA at 5.5 V with fast durations of approximately 10 ns to 20 ns. This appears
as high di/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of
the input capacitor to the IN pin and to the GND pin is critical because any series inductance between IN and
CIN+ or CIN− and GND can create voltage spikes that could appear on the VIN supply line and in the GND
36
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Layout Guidelines (continued)
plane. Close placement of the input bypass capacitor at the input side of the inductor is also critical. The source
impedance (inductance and resistance) from the input supply, along with the input capacitor of the LM36923H,
form a series RLC circuit. If the output resistance from the source (RS) is low enough the circuit is underdamped
and has a resonant frequency (typically the case). Depending on the size of LS the resonant frequency could
occur below, close to, or above the LM36923H switching frequency. This can cause the supply current ripple to
be:
1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the
LM36923H switching frequency;
2. Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency; or
3. Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency.
Figure 62 shows the series RLC circuit formed from the output impedance of the supply and the input capacitor.
The circuit is redrawn for the AC case where the VIN supply is replaced with a short to GND, and the LM36923H
+ Inductor is replaced with a current source (ΔIL). Equation 1 is the criteria for an underdamped response.
Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of LS,
RS, and CIN. As an example, consider a 3.6-V supply with 0.1 Ω of series resistance connected to CIN through 50
nH of connecting traces. This results in an underdamped input-filter circuit with a resonant frequency of 712 kHz.
Because both the 1-MHz and 500-kHz switching frequency options lie close to the resonant frequency of the
input filter, the supply current ripple is probably larger than the inductor current ripple. In this case, using
equation 3, the supply current ripple can be approximated as 1.68 times the inductor current ripple (using a 500kHz switching frequency) and 0.86 times the inductor current ripple using a 1-MHz switching frequency.
Increasing the series inductance (LS) to 500 nH causes the resonant frequency to move to around 225 kHz, and
the supply current ripple to be approximately 0.25 times the inductor current ripple (500-kHz switching frequency)
and 0.053 times for a 1-MHz switching frequency.
'IL
ISUPPLY
RS
LS
LM36923H
L
SW
+
IN
VIN Supply
-
CIN
ISUPPLY
LS
RS
CIN
'IL
2
1.
RS
1
>
LS x CIN 4 x LS2
2. f RESONANT =
1
2S LS x CIN
3. I SUPPLYRIPP LE | 'IL x
1
2S x 500 kHz x CIN
2
·
§
1
2
¸
RS + ¨¨2S x 500 kHz x LS ¸
2
S
x
500
kHz
x
C
IN
¹
©
Figure 62. Input RLC Network
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10.2 Layout Example
Inner or
Bottom Layer
Diode
VIA
Input Cap
ASEL
5.0 mm
Top Layer
Inductor
Output Cap
6.5 mm
Figure 63. LM36923H Layout Example
38
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM36923HYFFR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
12
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
36923H
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Feb-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM36923HYFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
12
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.5
B0
(mm)
K0
(mm)
P1
(mm)
1.99
0.75
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM36923HYFFR
DSBGA
YFF
12
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0012
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
0.8 TYP
0.4 TYP
D
SYMM
C
1.2
TYP
B
D: Max = 1.756 mm, Min =1.695 mm
E: Max = 1.355 mm, Min =1.295 mm
A
12X
0.015
0.3
0.2
C A
1
2
3
0.4 TYP
SYMM
B
4222191/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.23)
1
2
3
A
(0.4) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222191/A 07/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0012
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X ( 0.25)
(R0.05) TYP
1
2
3
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222191/A 07/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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