MC14538B Dual Precision Retriggerable/Resettable Monostable Multivibrator The MC14538B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an accurate output pulse over a wide range of widths, the duration and accuracy of which are determined by the external timing components, CX and RX. Output Pulse Width T = RX @ CX (secs) RX = W CX = Farads http://onsemi.com Features • • • • • • • • • • • Unlimited Rise and Fall Time Allowed on the A Trigger Input Pulse Width Range = 10 ms to 10 s Latched Trigger Inputs Separate Latched Reset Inputs 3.0 Vdc to 18 Vdc Operational Limits Triggerable from Positive (A Input) or Negative−Going Edge (B−Input) Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range Pin−for−pin Compatible with MC14528B and CD4528B (CD4098) Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with Supplies Up to 6 V NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant Value Unit V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Operating Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) July, 2014 − Rev. 11 SOEIAJ−16 F SUFFIX CASE 966 16 16 14538BG AWLYYWW 14538BG AWLYWW 1 1 16 1 SOIC−16WB 16 14 538B ALYWG G MC14538B ALYWG 1 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 TSSOP−16 DT SUFFIX CASE 948F SOIC−16 −0.5 to +18.0 VDD SOIC−16WB DW SUFFIX CASE 751G MARKING DIAGRAMS MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol SOIC−16 D SUFFIX CASE 751B TSSOP−16 A WL, L YY, Y WW, W G or G SOEIAJ−16 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14538B/D MC14538B PIN ASSIGNMENT BLOCK DIAGRAM CX VSS 1 16 VDD CX/RXA 2 15 VSS RESET A 3 14 CX/RXB AA 4 13 RESET B BA 5 12 AB QA 6 11 BB QA 7 10 QB VSS 8 9 QB 1 4 5 1 ms 10 ms 100 ms 1 ms 10 ms VDD 2 A B Q1 6 Q1 RESET 7 3 CX ONE−SHOT SELECTION GUIDE 100 ns MC14528B MC14536B MC14538B RX 100 ms RX 15 1s 12 10 s 23 HR 5 MIN. MC14541B MC4538A* 11 VDD 14 A Q2 B Q2 RESET 10 9 13 RX AND CX ARE EXTERNAL COMPONENTS. VDD = PIN 16 VSS = PIN 8, PIN 1, PIN 15 *LIMITED OPERATING VOLTAGE (2 - 6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE ORDERING INFORMATION Package Shipping† MC14538BDG SOIC−16 (Pb−Free) 48 Units / Rail NLV14538BDG* SOIC−16 (Pb−Free) 48 Units / Rail MC14538BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14538BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC14538BDTR2G TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel NLV14538BDTR2G* TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel MC14538BDWG SOIC−16 WB (Pb−Free) 47 Units / Rail NLV14538BDWG* SOIC−16 WB (Pb−Free) 47 Units / Rail MC14538BDWR2G SOIC−16 WB (Pb−Free) 1000 Units / Tape & Reel NLV14538BDWR2G* SOIC−16 WB (Pb−Free) 1000 Units / Tape & Reel MC14538BFG SOEIAJ−16 (Pb−Free) 50 Units / Rail MC14538BFELG SOEIAJ−16 (Pb−Free) 2000 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14538B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol VDD Vdc − 55_C 25_C 125_C Min Max Min Typ (Note 2) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current, Pin 2 or 14 Iin 15 − ±0.05 − ±0.00001 ±0.05 − ±0.5 mAdc Input Current, Other Inputs Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance, Pin 2 or 14 Cin − − − − 25 − − − pF Input Capacitance, Other Inputs (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) Q = Low, Q = High IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Quiescent Current, Active State (Both) (Per Package) Q = High, Q = Low IDD 5.0 10 15 − − − 2.0 2.0 2.0 − − − 0.04 0.08 0.13 0.20 0.45 0.70 − − − 2.0 2.0 2.0 mAdc IT 5.0 10 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink Total Supply Current at an external load capacitance (CL) and at external timing network (RX, CX) (Note 3) mAdc IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf where: IT in mA (one monostable switching only), where: CX in mF, CL in pF, RX in k ohms, and where: f in Hz is the input frequency. mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ OPERATING CONDITIONS External Timing Resistance RX − 5.0 − (Note 4) kW External Timing Capacitance CX − 0 − No Limit (Note 5) mF 4. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MW.. 5. If CX > 15 mF, use discharge protection diode per Fig. 11. http://onsemi.com 3 MC14538B SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol Output Rise Time tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/pF) CL + 20 ns tTLH Output Fall Time tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time A or B to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 255 ns tPLH, tPHL = (0.36 ns/pF) CL + 132 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns tPLH, tPHL VDD Vdc Min Typ (Note 7) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns ns 5.0 10 15 − − − 300 150 100 600 300 220 5.0 10 15 − − − 250 125 95 500 250 190 5 10 15 − − − − − − 15 5 4 ms B Input 5 10 15 − − − 300 1.2 0.4 1.0 0.1 0.05 ms A Input 5 10 15 Reset to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 205 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) CL + 82 ns Input Rise and Fall Times Reset Input Pulse Width A, B, or Reset ns tr, tf − No Limit tWH, tWL 5.0 10 15 170 90 80 85 45 40 − − − ns Retrigger Time trr 5.0 10 15 0 0 0 − − − − − − ns Output Pulse Width — Q or Q Refer to Figures 8 and 9 CX = 0.002 mF, RX = 100 kW T ms 5.0 10 15 198 200 202 210 212 214 230 232 234 CX = 0.1 mF, RX = 100 kW 5.0 10 15 9.3 9.4 9.5 9.86 10 10.14 10.5 10.6 10.7 ms CX = 10 mF, RX = 100 kW 5.0 10 15 0.91 0.92 0.93 0.965 0.98 0.99 1.03 1.04 1.06 s 5.0 10 15 − − − ±1.0 ±1.0 ±1.0 ±5.0 ±5.0 ±5.0 % Pulse Width Match between circuits in the same package. CX = 0.1 mF, RX = 100 kW 100 [(T1 – T2)/T1] 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14538B VDD VDD P1 RX 2 (14) CX + C1 - Vref1 1 (15) ENABLE + C2 - Vref2 ENABLE R Q OUTPUT LATCH S Q N1 A VSS 4 (12) 6(10) 7(9) CONTROL 5 (11) B RESET QR S 3 (13) NOTE: Pins 1, 8 and 15 must be externally grounded QR R RESET LATCH Figure 1. Logic Diagram (1/2 of DevIce Shown) VDD 500 pF 0.1 mF CERAMIC ID RX ′ RX VSS CX ′ CX Vin VSS CX/RX A B Q RESET Q A′ Q′ B′ Q′ 20 ns CL 20 ns VDD 90% CL CL 10% Vin 0V CL RESET′ VSS Figure 2. Power Dissipation Test Circuit and Waveforms VDD INPUT CONNECTIONS RX ′ RX VSS PULSE GENERATOR PULSE GENERATOR PULSE GENERATOR A Characteristics *CL = 50 pF CX ′ CX VSS CX/RX B Q RESET Q A′ Q′ B′ CL CL CL Q′ CL RESET′ VSS Reset A B tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD PG1 VDD tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD VSS PG2 tPLH(R), tPHL(R), tWH, tWL PG3 PG1 PG2 *Includes capacitance of probes, wiring, and fixture parasitic. NOTE: Switching test waveforms for PG1, PG2, PG3 are shown In Figure 4. Figure 3. Switching Test Circuit http://onsemi.com 5 PG1 = PG2 = PG3 = MC14538B 90% 10% tTHL 50% A tTLH tWH 50% tTHL B VDD tTLH 90% 10% 50% VDD tWL tTHL RESET tPHL 90% 10% tPLH 50% tTHL tPLH T 50% Q tPHL Q 50% tTHL tPLH 90% 10% 50% trr tPHL 50% tTLH tPHL tWL tTLH 90% 10% 50% VDD 50% 50% 50% TA = 25°C RX = 100 kW CX = 0.1 mF NORMALIZED PULSE WIDTH CHANGE WITH RESPECT TO VALUE AT VDD = 10 V (%) RELATIVE FREQUENCY OF OCCURRENCE Figure 4. Switching Test Waveforms 0% POINT PULSE WIDTH VDD = 5.0 V, T = 9.8 ms VDD = 10 V, T = 10 ms VDD = 15 V, T = 10.2 ms 1.0 0.8 0.6 0.4 0.2 0 RX = 100 kW CX = 0.1 mF 2 1 0 1 2 5 -4 -2 0 2 4 T, OUTPUT PULSE WIDTH (%) Figure 5. Typical Normalized Distribution of Units for Output Pulse Width 6 7 8 9 10 11 12 VDD, SUPPLY VOLTAGE (VOLTS) TOTAL SUPPLY CURRENT ( μA) FUNCTION TABLE Inputs RX = 100 kW, CL = 50 pF ONE MONOSTABLE SWITCHING ONLY VDD = 15 V 5.0 V 10 10 V 1.0 0.1 0.001 14 Figure 6. Typical Pulse Width Variation as a Function of Supply Voltage VDD 1000 100 13 0.1 1.0 10 Reset A H H L H H H H H L 100 OUTPUT DUTY CYCLE (%) Figure 7. Typical Total Supply Current versus Output Duty Cycle http://onsemi.com 6 Outputs B Q Q H L Not Triggered Not Triggered L, H, L H L, H, Not Triggered Not Triggered X X X X L H Not Triggered 15 RX = 100 kW CX = 0.1 mF VDD = 15 V 2 1 VDD = 10 V 0 VDD = 5 V -1 TYPICAL NORMALIZED ERROR WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%) TYPICAL NORMALIZED ERROR WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%) MC14538B RX = 100 kW CX = .002 mF 3.0 2.0 1.0 0 -1.0 -2 VDD = 15 V VDD = 10 V -2.0 VDD = 5.0 V -3.0 -60 -40 -20 0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (°C) 120 140 -60 -40 Figure 8. Typical Error of Pulse Width Equation versus Temperature -20 0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (°C) Figure 9. Typical Error of Pulse Width Equation versus Temperature THEORY OF OPERATION 1 3 4 A 2 B 5 RESET Vref2 Vref2 CX/RX Vref2 Vref2 Vref1 Vref1 Vref1 Vref1 Q T 120 140 T T 1 Positive edge trigger 4 Positive edge re−trigger (pulse lengthening) 2 Negative edge trigger 5 Positive edge re−trigger (pulse lengthening) 3 Positive edge trigger Figure 10. Timing Operation http://onsemi.com 7 MC14538B TRIGGER OPERATION on Reset sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor P1 ➄. When the voltage on the capacitor reaches Vref 2, the reset latch will clear, and will then be ready to accept another pulse. It the Reset input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Reset input, the output pulse T can be made significantly shorter than the minimum pulse width specification. The block diagram of the MC14538B is shown in Figure 1, with circuit operation following. As shown in Figure 1 and 10, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD (while inputs B and Reset are held to VDD) a valid trigger is recognized, which turns on comparator C1 and N−channel transistor N1 ➀. At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until Vref1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals Vref 2, comparator C2 changes state, causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 ➁. This ends at the timing cycle with the monostable in the quiescent state, waiting for the next trigger. In the quiescent state, CX is fully charged to VDD causing the current through resistor RX to be zero. Both comparators are “off” with total device current due only to reverse junction leakages. An added feature of the MC14538B is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input waveform. POWER−DOWN CONSIDERATIONS Large capacitance values can cause problems due to the large amount of energy stored. When a system containing the MC14538B is powered down, the capacitor voltage may discharge from VDD through the standard protection diodes at pin 2 or 14. Current through the protection diodes should be limited to 10 mA and therefore the discharge time of the VDD supply must not be faster than (VDD). (C) / (10 mA). For example, if VDD = 10 V and CX = 10 mF, the VDD supply should discharge no faster than (10 V) x (10 mF) / (10 mA) = 10 ms. This is normally not a problem since power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VDD to zero volts occurs, the MC14538B can sustain damage. To avoid this possibility use an external clamping diode, DX, connected as shown in Fig. 11. Dx Cx RETRIGGER OPERATION Rx VDD VSS The MC14538B is retriggered if a valid trigger occurs ➂ followed by another valid trigger ➃ before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from Vref 1, but has not yet reached Vref 2, will cause an increase in output pulse width T. When a valid retrigger is initiated ➃, the voltage at CX/RX will again drop to Vref 1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. VDD Q Q RESET Figure 11. Use of a Diode to Limit Power Down Current Surge RESET OPERATION The MC14538B may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse http://onsemi.com 8 MC14538B TYPICAL APPLICATIONS CX RX CX RX VDD RISING-EDGE TRIGGER A Q B Q VDD RISING-EDGE A TRIGGER B Q Q B = VDD RESET = VDD CX RESET = VDD CX RX VDD VDD A = VSS Q B FALLING-EDGE TRIGGER RX Q A B Q Q FALLING-EDGE TRIGGER RESET = VDD RESET = VDD Figure 12. Retriggerable Monostables Circuitry Figure 13. Non−Retriggerable Monostables Circuitry NC A B Q NC Q NC CD VDD VDD Figure 14. Connection of Unused Sections http://onsemi.com 9 MC14538B PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 B M S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 10 MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC14538B PACKAGE DIMENSIONS SOIC−16 WB DW SUFFIX CASE 751G−03 ISSUE D A D 9 1 8 16X M T A h X 45 _ MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ S B S L A 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. B B 14X e A1 H E 0.25 8X M B M 16 q C T SEATING PLANE SOLDERING FOOTPRINT 16X 0.58 11.00 1 16X 1.27 PITCH 1.62 DIMENSIONS: MILLIMETERS http://onsemi.com 11 MC14538B PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 12 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC14538B PACKAGE DIMENSIONS SOEIAJ−16 F SUFFIX CASE 966 ISSUE A 16 LE 9 Q1 M_ E HE 1 L 8 DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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