TI1 LM49150TL/NOPB Mono class d audio subsystem with earpiece driver and stereo ground referenced headphone amplifier Datasheet

LM49150, LM49150TLEVAL
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LM49150
SNAS439C – AUGUST 2008 – REVISED MAY 2013
Mono Class D Audio Subsystem with Earpiece
Driver and Stereo Ground Referenced Headphone Amplifiers
Check for Samples: LM49150, LM49150TLEVAL
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
•
2
E S Class D Amplifier
Ground Referenced Headphone Outputs —
Eliminates Output Coupling Capacitors
I2C Volume and Mode Control
Mono Earpiece Amplifier
Flexible Output for Speaker and Headphone
Output
20–Bump DSBGA Package
Soft Enable Function
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection
Low Supply Current
Micro-Power Shutdown
KEY SPECIFICATIONS
•
•
•
•
•
Output power at VDD = 5V:
– Speaker: RL = 8Ω BTL, THD+N ≤ 1%: 1.25W
(typ)
– Headphone: RL = 32Ω SE, THD+N ≤ 1%:
42mW (typ)
– Earpiece: RL = 8Ω SE, THD+N ≤ 1%: 135mW
(typ)
Output power at VDD = 3.3V:
– Speaker: RL = 8Ω BTL, THD+N ≤ 1%:
520mW (typ)
– Headphone: RL = 32Ω BTL, THD+N ≤ 1%:
42mW (typ)
– Earpiece: RL = 8Ω SE, THD+N ≤ 1%: 35mW
(typ)
Output Offset
– LS Mode: 9mV (typ)
– HP Mode: 1mV (typ)
– Earpiece: 1mV (typ)
Single Supply Operation (VDD): 2.7 to 5.5V
I2C Single Supply Operation: 1.7 to 5.5V
APPLICATIONS
•
•
•
Mobile Phones
PDAs
Portable Electronics
DESCRIPTION
The LM49150 is a fully integrated audio subsystem
designed for portable handheld applications such as
cellular phones. Part of TI's PowerWise™ product
family, the LM49150 consumes very low power in the
various modes of operation and still providing great
audio performance. The LM49150 combines a 1.25W
mono E2S (Enhanced Emission Suppression) class D
amplifier, 135mW Class AB earpiece amplifier,
42mW/channel stereo ground reference headphone
amplifiers, volume control, and mixing circuitry into a
single device.
The filterless class D amplifier delivers 1.25W into an
8Ω load with <1% THD+N with a 5V supply. The E2S
class D amplifier features a patented, ultra low EMI
PWM architecture that significantly reduces RF
emissions while preserving audio quality. The
42mW/channel headphone drivers feature TI’s
ground referenced architecture that creates a groundreferenced output from a single supply, eliminating
the need for bulky and expensive DC-blocking
capacitors, saving space and minimizing cost.
The LM49150 features a fully differential mono input,
and two single-ended stereo inputs. The three inputs
can be mixed/multiplexed to either the speaker or
headphone amplifiers. Each input channel has an
independent, 32-step digital volume control. The
headphone output stage features an additional, 8step gain control, while the speaker output stage has
a selectable 6dB or 12dB gain. The mixer, volume
control and device mode select are controlled through
an I2C compatible serial interface.
The LM49150’s superior click and pop suppression
eliminates audible transients on power-up/down and
during shutdown. The LM49150 is available in a ultrasmall 20-bump DSBGA package (2.225mm X
2.644mm).
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerWise is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM49150, LM49150TLEVAL
SNAS439C – AUGUST 2008 – REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Typical Application
VDD
LSVDD
Cs7
1 PF
Cs1
2.2 PF
Cs2
0.1 PF
Bypass
Amp
CIN4
1 PF
INM+
+
+
CIN3
1 PF
INM+
- 6 dB
LSOUT+
+6
Class D
+12 dB
Volume
- 80 ~ + 18 dB
-
Speaker
8
LSOUT-
CIN2
INR
Mixer
Volume
- 80 ~ + 18 dB
+
0.22 PF
and
Output
Headphone
-18 dB - 0 dB
(8 steps)
HPL
Headphone
-18 dB - 0 dB
(8 steps)
HPR
Mode
CIN1
+
0.22 PF
Cs6
BYPASS
+
Select
Volume
- 80 ~ + 18 dB
INL
Bias
2.2 PF
VO (LDO)
LDO
2
I CVDD
SDA
SCL
+
Cs3
Cs4
2.2 PF
0.1 PF
2
I C
Interface
Charge Pump
CPVss
GND
CPN
Cs5
2.2 PF
CPGND
CPP
C1
2.2 PF
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
2
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Connection Diagram
1
2
3
4
A
I C VDD
GND
LSOUT-
LSOUT+
B
VDD
SDA
SCL
LSVDD
C
INL
INR
BYPASS
CPVSS
D
INM-
VO(LDO)
CPN
CPP
E
INM+
HPR
HPL
CPGND
2
Figure 2. 20 Bump DSBGA Package - Top View
(Bump Side Down)
See Package Number YZR0020KGA
BUMP DESCRIPTIONS
Bump
Name
Description
A1
2
2
I CVDD
I C Power Supply
A2
GND
Ground
A3
LSOUT-
Inverting Loudspeaker Output
A4
LSOUT+
Non-Inverting Loudspeaker Output
B1
VDD
Analog Power Supply
B2
SDA
I2C Data Input
B3
SCL
I2C Clock Input
B4
LSVDD
C1
INL
Loudspeaker Power Supply
Left Channel Input
C2
INR
Right Channel Input
C3
BYPASS
C4
CPVSS
D1
INM-
D2
VO(LDO)
D3
CPN
Charge Pump Flying Capacitor - Negative Terminal
D4
CPP
Charge Pump Flying Capacitor - Positive Terminal
E1
INM+
Mono Channel Non-Inverting Input
E2
HPR
Right Channel Headphone Amplifier Output
E3
HPL
Left Channel Headphone Amplifier Output
E4
CPGND
Mid-Rail Supply Bypass
Charge Pump Output
Mono Channel Inverting Input
Internal LDO Output
Charge Pump Ground
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Product Folder Links: LM49150 LM49150TLEVAL
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Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (1)
6.0V
−65°C to +150°C
Storage Temperature
Input Voltage
−0.3 to VDD +0.3
Power Dissipation (4)
Internally Limited
ESD Rating (5)
2.0kV
ESD Rating (6)
200V
Junction Temperature
150°C
Soldering Information
See AN-1112 “Micro SMD Wafer Level Chip Scale Package”
(Literature Number SNVA009)
θJA (typ) - YZR0020KGA
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
46.1°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Operating Ratings
−40°C to 85°C
Temperature Range
2.7V ≤ VDD ≤ 5.5V
Supply Voltage
Supply Voltage (I2C)
1.7V ≤ I2CVDD ≤ 5.5V
Electrical Characteristics 3.3V (1)
The following specifications apply for VDD = LSVDD = 3.3V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
Parameter
LM49150
Conditions
Typical (2)
Limits (3)
Units
(Limits)
VIN = 0, No Load
IDD
Supply Current
LS mode 1
3.7
5
mA (max)
HP mode 8
4.7
6.7
mA (max)
EP Bypass mode
0.8
1.2
mA (max)
7
9.5
mA (max)
LS + HP mode 5 and mode 10
ISD
VOS
LS mode 1, GAMP_SD = 1
3
4
mA (max)
HP mode 8, GAMP_SD = 1
4.3
6.1
mA (max)
0.04
1
µA (max)
VIN = 0V, LS, RL = 8Ω
LS Gain = 6dB, Stereo mode 10
9
40
mV (max)
VIN = 0V, HP, RL = 32Ω
Ground Referenced, Stereo mode 10
1
5
mV (max)
0.8
5
mV (max)
Shutdown Current
Output Offset Voltage
VIN = 0V, EP Bypass only, RL = 8Ω
(1)
(2)
(3)
4
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
Datasheet min/max specification limits are ensured by test or statistical analysis.
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Electrical Characteristics 3.3V(1) (continued)
The following specifications apply for VDD = LSVDD = 3.3V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
PO
THD+N
η
Parameter
Conditions
Output Power
Total Harmonic Distortion + Noise
Efficiency
LM49150
Typical (2)
Limits (3)
Units
(Limits)
LS mode 1, THD+N = 1%, f = 1kHz
LS Gain = 6dB, RL = 4Ω
845
LS mode 1, THD+N = 1%, f = 1kHz
LS Gain = 6dB, RL = 8Ω
520
HP mode 8, THD+N = 1%, f = 1kHz
HP Attenuation = 0dB, RL = 16Ω
42
HP mode 8, THD+N = 1%, f = 1kHz
HP Attenuation = 0dB, RL = 32Ω
43
39
mW (min)
EP Bypass only, THD+N = 1%, f = 1kHz
RL = 8Ω
35
28
mW (min)
mW
450
mW (min)
mW
LS mode 1, f = 1kHz
POUT = 250mW; RL = 8Ω
0.02
%
HP mode 8, f = 1kHz
POUT = 20mW; RL = 32Ω
0.009
%
EP Bypass only, f = 1kHz
POUT = 20mW; RL = 8Ω
0.15
%
88
%
EP Bypass
11
μV
LS; Mode 1
41
μV
LS; Mode 2
41
μV
LS; Mode 3
43
μV
HP; Mode 4
9
μV
HP; Mode 8
10
μV
HP; Mode 12
12
μV
LS output
A-weighted,
inputs terminated to AC GND, Output referred
∈OUT
Output Noise
VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω, CB = 2.2µF,
All audio inputs terminated to AC GND, output referred
EP Bypass
95
dB
LS; Mode 1
72
dB
LS; Mode 2
67
dB
LS; Mode 3
71
dB
HP; Mode 4
91
dB
HP; Mode 8
83
dB
HP; Mode 12
81
dB
±0.2
dB
-92
dB
Loudspeaker Output; LS Gain = 6dB
PSRR
Power Supply Rejection Ratio
Headphone Output, HP Attenuation = 0dB
Volume Control Step Size Error
Maximum Attenuation
Digital Volume Control Range
AM
Mute Attenuation
Volume Step 2
-46.5
-49
-44
dB (min)
dB (max)
Maximum Gain
18
17
19
dB (min)
dB (max)
HP
98
dB
LS
98
dB
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Electrical Characteristics 3.3V(1) (continued)
The following specifications apply for VDD = LSVDD = 3.3V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
Limits (3)
Units
(Limits)
Maximum gain setting
12.9
10
15
kΩ (min)
kΩ (max)
Maximum attenuation setting
111
90
130
kΩ (min)
kΩ (max)
62
50
80
kΩ (min)
kΩ (max)
Conditions
Mono Channel Input Impedance
LIN and RIN Input Impedance
ZIN
LM49150
Typical (2)
Parameter
EP Bypass Resistance
CMRR
Common-Mode Rejection Ratio
XTALK
Crosstalk
TON
Turn-On Time
f = 217Hz, VCM = 1VP-P, RL = 8Ω
EP Bypass
55
dB
f = 217Hz, VCM = 1VP-P, RL = 8Ω
LS, Mode 1
55
dB
f = 217Hz, VCM = 1VP-P, RL = 32Ω
HP, Mode 4
61
dB
HP mode 8; PO = 12mW
RL = 32Ω, f = 1kHz
78
dB
CB = 2.2μF, HP,
Normal Turn-On Mode
27
ms
CB = 2.2μF, HP,
Fast Turn-On Mode
15
ms
Electrical Characteristics 5.0V (1) (2)
The following specifications apply for VDD = LSVDD = 5.0V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
Parameter
LM49150
Conditions
Typical (3)
Limits (2)
Units
(Limits)
VIN = 0, No Load
IDD
ISD
VOS
(1)
(2)
(3)
6
Supply Current
LS mode 1
4.5
mA
HP mode 8
4.9
mA
EP Bypass Mode
0.9
mA
LS + HP Mode 5 and Mode 10
7.7
mA
LS Mode 1, GAMP_SD = 1
3.7
mA
HP Mode 8, GAMP_SD = 1
4.4
Shutdown Current
Output Offset Voltage
mA
0.02
1
µA (max)
VIN = 0V, LS, RL = 8Ω
LS Gain = 6dB, Stereo Mode 10
9
40
mV (max)
VIN = 0V, HP, RL = 32Ω
Ground Reference, Stereo Mode 10
1
5
mV (max)
VIN = 0V, EP Bypass only, RL = 8Ω
1
5
mV (max)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
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LM49150, LM49150TLEVAL
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SNAS439C – AUGUST 2008 – REVISED MAY 2013
Electrical Characteristics 5.0V(1)(2) (continued)
The following specifications apply for VDD = LSVDD = 5.0V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
PO
THD+N
η
Parameter
Conditions
Output Power
Total Harmonic Distortion + Noise
Efficiency
LM49150
Typical (3)
Limits (2)
Units
(Limits)
LS Mode 1, THD+N = 1%, f = 1kHz
LS Gain = 6dB, RL = 4Ω
2.1
W
LS Mode 1, THD+N = 1%, f = 1kHz
LS Gain = 6dB, RL = 8Ω
1.25
W
HP Mode 8, THD+N = 1%, f = 1kHz
HP Attenuation = 0dB, RL = 16Ω
42
mW
HP Mode 8, THD+N = 1%, f = 1kHz
HP Attenuation = 0dB, RL = 32Ω
42
mW
EP Bypass Only, THD+N = 1%
f = 1kHz, RL = 8Ω
135
mW
LS Mode 1, f = 1kHz
POUT = 600mW; RL = 8Ω
0.015
%
HP Mode 8, f = 1kHz
POUT = 20mW; RL = 32Ω
0.01
%
EP Bypass only, f = 1kHz,
POUT = 60mW; RL = 8Ω
0.08
%
88
%
EP Bypass
10
μV
LS; Mode 1
40
μV
LS; Mode 2
47
μV
LS; Mode 3
48
μV
HP; Mode 4
9
μV
HP; Mode 8
10
μV
HP; Mode 12
11
μV
LS Output
A-weighted,
inputs terminated to AC GND, Output referred
∈OUT
Output Noise
VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω, CB = 2.2µF,
All audio inputs terminated to AC GND; output referred
EP Bypass
97
dB
LS; Mode 1
75
dB
LS; Mode 2
71
dB
LS; Mode 3
71
dB
HP; Mode 4
91
dB
HP; Mode 8
80
dB
HP; Mode 12
79
dB
±0.2
dB
-92
dB
Loudspeaker Output; LS Gain = 6dB
PSRR
Power Supply Rejection Ratio
Headphone Output, HP Attenuation = 0dB
Volume Control Step Size Error
Maximum Attenuation
Digital Volume Control Range
AM
ZIN
Mute Attenuation
Mono Channel Input Impedance
LIN and RIN Input Impedance
Volume Step 2
-46.5
-49
-44
dB (min)
dB (max)
Maximum Gain
18
17
19
dB (min)
dB (max)
HP
98
LS
98
dB
Maximum gain setting
12
kΩ
Maximum attenuation setting
111
EP Bypass Resistance
62
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dB
kΩ
50
80
kΩ (min)
kΩ (max)
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Electrical Characteristics 5.0V(1)(2) (continued)
The following specifications apply for VDD = LSVDD = 5.0V, AV = 0dB, Loudspeaker RL = 15μH+8Ω+15μH, Earpiece RL = 8Ω, f
= 1kHz, unless otherwise specified. Limits apply for TA = 25C. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Symbol
CMRR
Parameter
Common-Mode Rejection Ratio
XTALK
Crosstalk
TON
Turn-On Time
LM49150
Conditions
Typical (3)
Limits (2)
Units
(Limits)
f = 217Hz, VCM = 1VP-P , RL = 8Ω
EP Bypass
55
dB
f = 217Hz, VCM = 1VP-P, RL = 8Ω
LS, Mode 1
55
dB
f = 217Hz, VCM = 1VP-P, RL = 32Ω
HP, Mode 4
61
dB
HP mode 8; PO = 12mW
RL = 32Ω, f = 1kHz
78
dB
CB = 2.2μF, HP,
Normal Turn-On Mode
27
ms
CB = 2.2μF, HP,
Fast Turn-On Mode
15
ms
I2C micro (1)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2C_VDD ≤ 5.5V, unless otherwise specified.
Symbol
(1)
(2)
(3)
(4)
8
Parameter
Conditions
LM49150
Typical (2)
Limits (3) (4)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Human body model, applicable std. JESD22-A114C.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Machine model, applicable std. JESD22-A115-A.
Submit Documentation Feedback
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I2C micro (1)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
Symbol
(1)
(2)
(3)
Parameter
Conditions
LM49150
Typical
(2)
Limits (3)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
250
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
t6
I2C Data Hold Time
250
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49150 LM49150TLEVAL
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL = 8Ω, POUT = 300mW
Speaker Mode 1
1
1
0.1
0.1
THD + N (%)
THD + N (%)
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, POUT = 250mW
Speaker Mode 1
0.01
0.01
0.001
20
100
1k
10k 20k
0.001
20
100
Figure 4.
THD+N vs Frecuency
VDD = 5V, RL = 8Ω, POUT = 600mW
Speaker Mode 1
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, POUT = 20mW
Headphone Mode 8
1
0.1
0.1
0.01
0.01
0.001
20
0.001
100
1k
10k 20k
20
100
FREQUENCY (Hz)
Figure 6.
THD+N vs Frequency
VDD = 3.6V, RL = 8Ω, POUT = 20mW
Headphone Mode
THD+N vs Frequency
VDD = 5V, RL = 32Ω, POUT = 20mW
Headphone Mode 8
1
THD + N (%)
THD + N (%)
10k 20k
FREQUENCY (Hz)
0.01
0.1
0.01
20
100
1k
10k 20k
0.001
20
FREQUENCY (Hz)
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100
1k
10k 20k
FREQUENCY (Hz)
Figure 7.
10
1k
Figure 5.
0.1
0.001
10k 20k
Figure 3.
1
1
1k
FREQUENCY (Hz)
THD + N (%)
THD + N (%)
FREQUENCY (Hz)
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 3.6V, RL = 8Ω, POUT = 30mW
Earpiece Bypass Mode
10
10
1
1
THD + N (%)
THD + N (%)
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, POUT = 20mW
Earpiece Bypass Mode
0.1
0.01
0.1
0.01
0.001
20
100
0.001
20
10k 20k
1k
100
FREQUENCY (Hz)
10k 20k
1k
FREQUENCY (Hz)
Figure 9.
Figure 10.
THD+N vs Frequency
VDD = 5V, RL = 8Ω, POUT = 60mW
Earpiece Bypass Mode
THD+N vs Output Power
RL = 8Ω, f = 1kHz
Speaker Mode 1
10
100
1
10
THD + N (%)
THD + N (%)
VDD = 5V
0.1
VDD = 3.3V
1
VDD = 3.6V
0.01
0.001
20
0.1
100
0.01
10k 20k
1k
1m
1
5
Figure 11.
Figure 12.
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Headphone Mode 8
THD+N vs Output Power
VDD = 3.6V, RL = 32Ω, f = 1kHz
Headphone Mode 8
100
100
10
10
1
0.1
0.01
0.001
1m
10m
OUTPUT POWER (W)
THD + N (%)
THD + N (%)
FREQUENCY (Hz)
1
0.1
0.01
100m
10m
0.001
1m
OUTPUT POWER (W)
Figure 13.
10m
100m
OUTPUT POWER (W)
Figure 14.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Headphone Mode 8
THD+N vs Output Power
RL = 8Ω, f = 1kHz
Earpiece Bypass Mode
100
100
VDD = 5V
10
THD + N (%)
THD + N (%)
10
1
0.1
VDD = 3.6V
VDD = 3.3V
1
0.1
0.01
0.001
1m
0.01
100m
10m
1m
1
100m
Figure 15.
Figure 16.
CMRR vs Frequency
VDD = 3.3V, VCM = 1VP-P RL = 8Ω
Loudspeaker Mode 1
CMRR vs Frequency
VDD = 3.3V, VCM = 1VP-P RL = 32Ω
Headphone Mode 4
-20
-20
-30
-30
CMRR (dB)
CMRR (dB)
OUTPUT POWER (W)
-40
-50
-40
-50
-60
-60
-70
10
10m
OUTPUT POWER (W)
100
1k
10k
-70
10
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17.
Figure 18.
CMRR vs Frequency
VDD = 3.3V, VCM = 1VP-P RL = 8Ω
Earpiece Bypass Mode
Crosstalk vs Frequency
VDD = 3.3V, VCM = 1VP-P RL = 32Ω
Headphone Mode 8
-50
-50
-55
-60
CROSSTALK (dB)
CMRR (dB)
-55
-60
-65
-70
-75
-80
-65
-85
-70
10
100
1k
10k
100k
-90
10
100
FREQUENCY (Hz)
Figure 19.
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1k
10k
100k
FREQUENCY (Hz)
Figure 20.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200VP-P RL = 8Ω
Loudspeaker Mode 2
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200mVP-P RL = 8Ω
Loudspeaker Mode 1
-50
-50
-60
-60
-70
-70
-80
10
100
1k
10k
-80
10
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21.
Figure 22.
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200VP-P RL = 32Ω
Headphone Mode 4
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200VP-P RL = 32Ω
Headphone Mode 8
-40
-50
-50
-60
PSRR (dB)
PSRR (dB)
-60
-70
-80
-70
-80
-90
-100
10
-90
100
1k
10k
-100
10
100k
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23.
Figure 24.
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200VP-P RL = 8Ω
Earpiece Bypass Mode
Efficiency vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Speaker Mode 1
-50
100k
100
90
-60
80
EFFICIENCY (%)
PSRR (dB)
-70
-80
-90
70
60
50
40
30
20
-100
10
-110
10
0
100
1k
10k
100k
0
200
400
600
FREQUENCY (Hz)
OUTPUT POWER (mW)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Efficiency vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Speaker Mode 1
100
100
90
90
80
80
70
70
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Power
VDD = 3.6V, RL = 8Ω, f = 1kHz
Speaker Mode 1
60
50
40
30
60
50
40
30
20
20
10
10
0
0
0
200
400
600
800
0
200
400
600
800
1000 1200
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 27.
Figure 28.
Power Dissipation vs Output Power
RL = 8Ω, f = 1kHz
Speaker Mode 1
Power Dissipation vs Output Power
RL = 32Ω, f = 1kHz
Headphone Mode 8
POWER DISSIPATION (mW)
200
VDD = 5V
150
100
V DD = 3.6V
V DD = 3.3V
50
0
0
250
500
750
1000 1250
1500
OUTPUT POWER (mW)
Figure 29.
Figure 30.
Power Dissipation vs Output Power
RL = 8Ω, f = 1kHz
Earpiece Bypass Mode
Output Power vs Supply Voltage
RL = 8Ω, f = 1kHz
Speaker Mode 1
2000
OUTPUT POWER (mW)
1750
1500
THD+N = 10%
1250
1000
750
THD+N = 1%
500
250
0
2.5
3
3.5
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
Figure 31.
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Figure 32.
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Typical Performance Characteristics (continued)
Output Power vs Supply Voltage
RL = 32Ω, f = 1kHz
Headphone Mode 8
Output Power vs Supply Voltage
RL = 8Ω, f = 1kHz
Earpiece Bypass Mode
70
200
THD+N = 10%
OUTPUT POWER (mW)
OUTPUT POWER (mW)
60
50
40
30
THD+N = 1%
20
10
0
2.5
3
3.5
4
4.5
5
160
THD+N = 10%
120
80
THD+N = 1%
40
0
2.5
5.5
3
SUPPLY VOLTAGE (V)
4
4.5
5
5.5
Figure 33.
Figure 34.
Supply Current vs Supply Voltage
Headphone Mode 1, No Load
Supply Current vs Supply Voltage
Earpiece Bypass Mode, No Load
1
5.2
0.95
SUPPLY CURRENT (mA)
5
SUPPLY CURRENT (mA)
3.5
SUPPLY VOLTAGE (V)
4.8
4.6
Gain Amp ON
4.4
0.9
0.85
0.8
0.75
4.2
Gain Amp OFF
4
2.5
3
3.5
4
4.5
5
5.5
0.7
2.5
3
3.5
4
4.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 35.
Figure 36.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM49150 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49150
and the master can communicate at clock rates up to 400kHz. Figure 37 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49150 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 38). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 39). The LM49150 device address
is 11111000.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM49150's I2C interface is powered up through the I2CVDD pin. The LM49150's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
I2C BUS FORMAT
The I2C bus format is shown in Figure 39. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LM49150 is a WRITE-ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM49150 receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM49150 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 37. I2C Timing Diagram
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SDA
SCL
S
P
START condition
STOP condition
Figure 38. Start and Stop Diagram
SCL
SDA
START
MSB
DEVICE ADDRESS
R/W
LSB
ACK
MSB
REGISTER DATA
LSB
ACK
STOP
Figure 39. Start and Stop Diagram
Table 1. Chip Address
B7
B6
B5
B4
B3
B2
B1
B0 (R/W)
1
1
1
1
1
0
0
0
Chip Address
Table 2. Control Registers
B7
B6
B5
B4
B3
B2
B1
B0
Shutdown Control
0
0
Spread
Spectrum
GAMP_SD
0
I2CVDD_SD
Turn_On _Time
PWR_On
Output Mode Control
0
1
EP Bypass
HPR_SD
MC3
(HP L&R)
MC2
(HP Mono)
MC1
(LS L&R)
MC0
(LS Mono)
Output Gain Control
1
0
0
INPUT_MUTE
LS_GAIN
HP_GAIN2
HP_GAIN1
HP_GAIN0
Mono Input Volume
Control
1
0
1
MG4
MG3
MG2
MG1
MG0
Left Input Volume
Control
1
1
0
LG4
LG3
LG2
LG1
LG0
Right Input Volume
Control
1
1
1
RG4
RG3
RG2
RG1
RG0
Table 3. Shutdown Control Register
Bit
Name
B5
Spread Spectrum
B4
Value
GAMP_SD
B3
B2
B1
B0
Description
0
Spread Spectrum Disabled
1
Spread Spectrum Enabled
0
Normal Operation
1
Disables the gain amplifiers that are not in use, to minimize IDD.
Recommended for Output Modes 1, 2, 4, 5, 8, 10
0
I2CVDD_SD
Turn_On_Time
PWR_On
0
I2CVDD acts as an active low RESET input. If I2CVDD drops below 1.1V,
the device resets and the I2C registers are restored to their default
state.
1
Normal Operation. I2CVDD voltage does not reset the device.
0
Normal Turn-On Time (27ms)
1
Fast Turn-On Time (15ms)
0
Device Disabled
1
Device Enabled
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Table 4. Output Mode Control Register
Bit
Name
B5
EP Bypass
B4
HPR_SD
Value
Description
0
Normal Output Mode Operation
1
Speaker and Headphone amplifier goes into shutdown mode and
enables Receiver Bypass path
0
Normal Operation
1
Disables Right Headphone Output
Table 5. Output Mode Selection (See (1))
(1)
18
Output
Mode
Number
MC3
MC2
MC1
MC0
LS Output
HP R Output
HP L Output
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
GP x M
SD
SD
2
0
0
1
0
2 x (GL x L + GR x R)
SD
SD
2 x (GL x L + GR x R)
+ GP x M
SD
SD
3
0
0
1
1
4
0
1
0
0
SD
GP x M/2
GP x M/2
5
0
1
0
1
GP x M
GP x M/2
GP x M/2
6
0
1
1
0
2 x (GL x L + GR x R)
GP x M/2
GP x M/2
GP x M/2
GP x M/2
7
0
1
1
1
2 x (GL x L + GR x R)
+ GP x M
8
1
0
0
0
SD
GR x R
GL x L
9
1
0
0
1
GP x M
GR x R
GL x L
10
1
0
1
0
2 x (GL x L + GR x R)
GR x R
GL x L
2 x (GL x L + GR x R)
+ GP x M
GR x R
GL x L
11
1
0
1
1
12
1
1
0
0
SD
GR x R + GP x M/2
GL x L + GP x M/2
13
1
1
0
1
GP x M
GR x R + GP x M/2
GL x L + GP x M/2
14
1
1
1
0
2 x (GL x L + GR x R)
GR x R + GP x M/2
GL x L + GP x M/2
15
1
1
1
1
2 x (GL x L + GR x R)
+ GP x M
GR x R + GP x M/2
GL x L + GP x M/2
MC3: HP Select L and R In
MC2: HP Select Mono In
MC1: Loud Speaker Select L and R In
MC0: Loud Speaker Select Mono In
M : Phone In (Mono)
R: Right In
L: Left In
SD: Shutdown
GP: Phone In (Mono) Volume Control Gain
GR: Right Stereo Volume Control Gain
GL: Left Stereo Volume Control Gain
MC1
MC0
LSOUT
0
0
SD
0
1
M
1
0
L+R
1
1
M+L+R
MC3
MC2
HPR Output
HPL Output
0
0
SD
SD
0
1
M
M
1
0
L
R
1
1
M+L
M+R
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Table 6. Output Gain Control (Loudspeaker)
Bit
LS_GAIN
Value
Gain (dB)
0
+6
1
+12
Table 7. Headphone Output Gain Setting
HP_Gain2
HP_Gain1
HP_Gain0
0
0
0
Gain (dB)
0
0
0
1
–1.2
0
1
0
–2.5
0
1
1
–4.0
1
0
0
–6.0
1
0
1
–8.5
1
1
0
–12
1
1
1
–18
Table 8. Volume Control Table
Volume Step
(1)
(2)
xG4
(1)
xG3
xG2
xG1
xG0
Gain (dB) (2)
1
0
0
0
0
0
–80.00
2
0
0
0
0
1
–46.50
3
0
0
0
1
0
–40.50
4
0
0
0
1
1
–34.50
5
0
0
1
0
0
–30.00
6
0
0
1
0
1
–27.00
7
0
0
1
1
0
–24.00
8
0
0
1
1
1
–21.00
9
0
1
0
0
0
–18.00
10
0
1
0
0
1
–15.00
11
0
1
0
1
0
–13.50
12
0
1
0
1
1
–12.00
13
0
1
1
0
0
–10.50
14
0
1
1
0
1
–9.00
15
0
1
1
1
0
–7.50
16
0
1
1
1
1
–6.00
17
1
0
0
0
0
–4.50
18
1
0
0
0
1
–3.00
19
1
0
0
1
0
–1.50
20
1
0
0
1
1
0.00
21
1
0
1
0
0
1.50
22
1
0
1
0
1
3.00
23
1
0
1
1
0
4.50
24
1
0
1
1
1
6.00
25
1
1
0
0
0
7.50
26
1
1
0
0
1
9.00
27
1
1
0
1
0
10.50
28
1
1
0
1
1
12.00
29
1
1
1
0
0
13.50
x = M, L and R
Gain / Attenuation is from input to output
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Table 8. Volume Control Table (continued)
Volume Step
xG4
(1)
xG3
xG2
xG1
xG0
Gain (dB) (2)
30
1
1
1
0
1
15.00
31
1
1
1
1
0
16.50
32
1
1
1
1
1
18.00
SHUTDOWN FUNCTION
The LM49150 features the following shutdown controls.
Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it
disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so
the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized.
Bit B0 (PWR_On) of the SHUTDOWN CONTROL register is the global shutdown control for the entire device.
Set PWR_On = 0 for normal operation. PWR_On = 1 overrides any other shutdown control bit.
OUTPUT MODE CONTROL
In the LM49150 OUTPUT MODE CONTROL register (Table 4), Bit B5 (EP Bypass) controls the operation of the
Earpiece Bypass path. If EP Bypass = 0, it would act under normal output mode operation set by bits B3, B2, B1,
and B0. If EP Bypass = 1, it overrides the B3, B2, B1, and B0 Bits and enables the Receiver Bypass path, a
class AB amplifier, to the speaker output.
Bit B4 (HPR_SD) of the OUPUT MODE CONTROL register controls the right headphone shutdown. If HPR_SD
= 1, the right headphone output is disabled.
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49150 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM49150 can be used without input coupling capacitors
when configured with a differential input signal.
SINGLE-ENDED INPUT CONFIGURATION
The left and right stereo inputs of the LM49150 are configured for single-ended sources (see Figure 1).
INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49150. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using Equation 1 below.
f = 1 / 2πRINCIN
(Hz)
Where
•
value of RIN is given in the Electrical Characteristics Table.
(1)
High-pass filtering the audio signal helps protect the speakers. When the LM49150 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not
amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance
matching and improved CMRR and PSRR.
20
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INPUT MIXER/MULTIPLEXER
The LM49150 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of LM49150. Multiple input paths can be
selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the
selected channel. Table 5 shows how the input signals are mixed together for each possible input selection.
CLASS D AMPLIFIER
The LM49150 features a high-efficiency, filterless, class D amplifier, which features a filterless modulation
scheme. When there is no input signal applied, the output switches between VDD and GND at a 50% duty cycle.
Since the outputs of the LM49150 class D amplifier are differential and in phase, the result is zero net voltage
across the speaker and no load current during the ideal state, thus conserving power. The switching frequency of
each output is 300kHz.
When an input signal is applied, the duty cycle (pulse width) changes. For increasing output voltages, the duty
cycle of one output increases while the duty cycle of the output decreases. For decreasing output voltages, the
converse occurs. The difference between the two pulse widths yields the differential output voltage across the
load.
SPREAD SPECTRUM
The LM49150 features a filterless spread spectrum modulation scheme. The switching frequency varies by +/30% about a 300kHz center frequency, reducing the wideband spectral content, reducing EMI emissions radiated
by the speaker and associated cables and traces. When a fixed frequency class D exhibits large amounts of
spectral energy at multiples of switching frequency, the spread spectrum architecture of the LM49150 spreads
that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio
reproduction, efficiency, or PSRR. To enable spread spectrum, set the spread spectrum bit, B5 = 1 of the
SHUTDOWN CONTROL register (see Table 3).
ENHANCED EMMISIONS SUPPRESSION (E2S)
The LM49150 features TI’s patented E2S system that reduces EMI, while maintaining high quality audio
reproduction and efficiency. The LM49150 features Edge Rate Control (ERC) that greatly reduces the high
frequency components of the output square waves by controlling the output rise and fall times, slowing the
transitions to reduce RF emissions, while optimizing THD+N and efficiency performance.
LDO GENERAL INFORMATION
The LM49150 has different supplies for each portion of the device, allowing for the optimum combination of
headroom, power dissipation and noise immunity. The speaker amplifiers are powered from LSVDD. The ground
reference headphone amplifiers are powered from the internal LDO. The separate power supplies allow the
loudspeaker amplifier to operate from a higher voltage for maximum headroom, while the headphone amplifiers
operate from a lower voltage, improving power dissipation.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49150 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF)
are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving
board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In
traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that
not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass
response. Because the LM49150 does not require the output coupling capacitors, the low frequency response of
the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the
ground referenced output nearly doubles the available dynamic range of the LM49250 headphone amplifiers
when compared to a traditional headphone amplifier operating from the same supply voltage.
CHARGE PUMP CAPACITOR SELECTION
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
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CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A
C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued
C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON)
of the charge pump switches and the ESR of C1 and Cs5 dominate the output impedance. A lower value
capacitor can be used in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (Cs5)
The value and ESR of the hold capacitor (Cs5) directly affects the ripple on CPVSS. Increasing the value of Cs5
reduces output ripple. Decreasing the ESR of Cs5 reduces both output ripple and charge pump output
impedance. A lower value capacitor can be used in systems with low maximum output power requirements.
LM49150 Demoboard Bill Of Materials
Table 9. Bill Of Materials
Location
Qty
CIN2, CIN1
2
0.22uF, 1206, 10V, X7R Ceramic Capacitor
Description
GRM319R71C224KA01D
Part Number
Manufacturer
Murata
CS4, CS2
2
0.1uF, 0805, 10V, X7R Ceramic Capacitor
GRM219R71C104KA01D
Murata
CS7
1
1.0uF, 0805, 10V, X7R Ceramic Capacitor
GRM21BR71A105KA01L
Murata
CIN3, CIN4
2
1.0uF 1206, 10V, X7R Ceramic Capacitor
GRM319R71C105KAA3D
Murata
CS5, C1
2
2.2uF, 0603, 10V, X7R, Ceramic Capacitor
GRM188R71A225KE15D
Murata
CS1, CS3, CS6
3
2.2uF, Size A, Tantalum Capactior
293D225X9010A2TE3
Vishay
U2
1
LM49150, 16 bump DSBGA
LM49510
CRCW06035R1KJNEA
R1, R2
2
5K ohm 1/10W 0.05% 0603 SMD
J11, J12, J13, J14
4
3–Header
J1, J2, J3, J7, J8,
J9, J10
7
2–Header
J6
1
Header_3M 8516–4500PL
U1
1
Headphone Jack
TI
Vishay
Layout Guidelines
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM49150 and the load results in decreased output power and efficiency. Trace
resistance between the power supply and the GND of the LM49150 has the same effect as a poorly regulated
supply, increased ripple and reduced peak output power. Use wide traces, for power-supply inputs and amplifier
outputs to minimize losses due to trace resistance, as well as providing heat dissipation from the device. Proper
grounding improves audio performance, minimizes crosstalk between channels and prevents switching noise
from interfering with audio signal. Use of power and ground planes is recommended.
The following recommendations should be considered when laying out the different grounds of the LM49150.
Refer to the Demo Board Schematic for the corresponding component designators. Bypass capacitors for AVDD
(CS7), LSVDD (CS1, CS2), VO(LDO) (CS3, CS4) should be grounded to the GND pin via a ground plane. Bypass
capacitor for CPVSS(CS5) should be grounded via a wide trace or a ground plane to the CPGND pin. The
headphone grounds should be connected to the GND via a separate trace also. This will help prevent noise from
the charge pump from feeding into the power supplies and the output.
Place all digital components and digital signal traces as far as possible from analog components and traces. Do
not run digital and analog traces in parallel on the same PCB layer.
22
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SNAS439C – AUGUST 2008 – REVISED MAY 2013
Demo Board Schematic
Figure 40. LM49150 Demo Board Schematic
PC Board Layout
Figure 41. Top Silkscreen Layer
Figure 42. Top Layer
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LM49150, LM49150TLEVAL
SNAS439C – AUGUST 2008 – REVISED MAY 2013
24
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Figure 43. Layer 2
Figure 44. Layer 3
Figure 45. Bottom Layer
Figure 46. Bottom Silkscreen
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SNAS439C – AUGUST 2008 – REVISED MAY 2013
REVISION HISTORY
Rev
Date
1.0
08/27/08
Initial release.
Description
1.01
09/09/08
Edited Table 6.
1.02
03/04/09
Added the Layout Guidelines section.
C
05/03/13
Changed layout of National Data Sheet to TI format.
Copyright © 2008–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM49150TL/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YZR
20
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
GK7
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM49150TL/NOPB
Package Package Pins
Type Drawing
SPQ
DSBGA
250
YZR
20
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
8.4
Pack Materials-Page 1
2.34
B0
(mm)
K0
(mm)
P1
(mm)
2.85
0.76
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM49150TL/NOPB
DSBGA
YZR
20
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0020xxx
0.600±0.075
D
E
TLA20XXX (Rev D)
D: Max = 2.681 mm, Min =2.621 mm
E: Max = 2.251 mm, Min =2.191 mm
4215053/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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