OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 LM4548A AC '97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and Texas Instruments 3D Sound Check for Samples: LM4548A FEATURES DESCRIPTION • • The LM4548A is an audio codec for PC systems which is fully PC98 compliant and performs the analog intensive functions of the AC '97 Rev 2 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4548A provides 90 dB of Dynamic Range. 1 • • • • • • AC '97 Rev 2 Compliant High Quality Sample Rate Conversion from 4 kHz to 48 kHz in 1 Hz Increments Multiple Codec Support True Line Level Output with Separate Gain Control Texas Instruments' 3D Sound Stereo Enhancement Circuitry Advanced Power Management Support Digital 3.3V and 5V Supply Options Extended Temperature: −40°C ≤ TA ≤ 85°C APPLICATIONS • • • Desktop PC Audio Systems on PCI Cards, AMR Cards, or with Motherboard Chips Sets Featuring AC Link Portable PC Systems as on MDC Cards, or with a Chipset or Accelerator Featuring AC Link General and Multi-Channel Audio Frequency Systems KEY SPECIFICATIONS • • • Analog Mixer Dynamic Range : 97 dB (typ) DAC Dynamic Range : 89 dB (typ) ADC Dynamic Range : 90 dB (typ) The LM4548A was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo ADCs and DACs and analog mixers with access to 4 stereo and 4 mono inputs. Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono and 2 stereo outputs, each with attenuation and mute control. The LM4548A supports Texas Instruments' 3D Sound stereo enhancement and a comprehensive sample rate conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution of 1 Hz to convert any rate in the range 4 kHz – 48 kHz. Sample timing from the ADCs and sample request timing for the DACs are completely deterministic to ease task scheduling and application software development. These features together with an extended temperature range also make the LM4548A suitable for non-PC codec applications. The LM4548A features the ability to connect several codecs together using the Extended AC Link configuration of one dedicated serial data signal to the Controller per codec. LM4548A systems support up to 8 simultaneous channels of streaming data on Input Frames (Codec to Controller) while Output Frames (Controller to Codec) carry 2 streams to multiple codecs. The LM4548A may also be used in systems with the Texas Instruments LM4550 to support up to 6 simultaneous channels of streaming data on Output Frames. The AC '97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM * *0 dB/20 dB MONO MIX 6 MS AUX VIDEO S EL E C T CD LINE_IN PHONE PC_BEEP MIX * 6 MONO_OUT LINE_OUT 10 12 14 16 G A M G A M G A M G A M G A M MONO VOLUME: 06h Atten Mute LINE LEVEL VOLUME: 04h Atten Mute STEREO MIX 0A LNLVL_OUT 0E 6 0C D13, 20h CODEC IDENTITY SELECT 6' ADC 6' ADC 18 16 $& ¶97 REGISTERS 18h * ID0# ID1# 18 1Ch GAIN MUTE M U X MIX1 G A M A M POWER SUPPLY & REFERENCES R E C O R D GAIN ATTEN MUTE 18 6' DAC 6' DAC 18 XTAL_IN XTAL_OUT AC LINK INTERFACE GAIN: D6,0Eh ADC SAMPLE RATE CONVERTER: 32h * MIC2 DAC SAMPLE RATE CONVERTER: 2Ch MIC1 SDATA_IN BIT_CLK SYNC SDATA_OUT RESET# POP NATIONAL 3D SOUND MASTER VOLUME: 02h Atten Mute 6 STEREO MIX 3D MIX2 STEREO SIGNAL PATH MONO SIGNAL PATH DIGITAL SIGNAL PATH NN G A M NN (HEX) Address of Analog Input Volume Control Register G A M Gain Attenuation Mute (Mute is default) * NNh Dm, NNh 2 Submit Documentation Feedback Asterisk denotes default setting after Cold Reset Control Register with hexadecimal address NN Control bit m in Register with hexadecimal address NN Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage 6.0V −65°C to +150°C Storage Temperature −0.3V to VDD +0.3V Input Voltage ESD Susceptibility (3) 2000V Pin 3 750V ESD Susceptibility (4) 200V Pin 3 100V Junction Temperature 150°C Soldering Information Vapor Phase (60 sec.) LQFP Package 215°C Infrared (15 sec.) 220°C θJA (typ) – PT (1) 74°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine Model, 220 pF – 240 pF discharged through all pins. (2) (3) (4) OPERATING RATINGS TMIN ≤ TA ≤ TMAX (1) Temperature Range −40°C ≤ TA ≤ 85°C Analog Supply Range 4.2V ≤ AVDD ≤ 5.5V Digital Supply Range 3.0V ≤ DVDD ≤ 5.5V The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX– TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4548A, TJMAX = 150°C. The typical junction-to-ambient thermal resistance is 74°C/W for package number PT. (1) ELECTRICAL CHARACTERISTICS (1) (2) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48 kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. Symbol Parameter Conditions LM4548A Typical (3) Limit (4) Units (Limits) AVDD Analog Supply Range 4.2 5.5 V (min) V (max) DVDD Digital Supply Range 3.0 5.5 V (min) V (max) DIDD Digital Quiescent Power Supply Current DVDD = 5 V DVDD = 3.3 V 43 20 mA mA AIDD Analog Quiescent Power Supply Current 53 mA IDSD Digital Shutdown Current 500 µA (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are measured at 25°C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 3 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48 kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. Symbol Parameter IASD Analog Shutdown Current VREF Reference Voltage PSRR Power Supply Rejection Ratio LM4548A Conditions Typical (3) Limit (4) 30 Units (Limits) µA 2.23 V 40 dB Analog Loopthrough Mode (5) THD Dynamic Range (6) CD Input to Line Output, -60 dB Input THD+N, A-Weighted Total Harmonic Distortion VO = -3 dB, f = 1 kHz, RL = 10 kΩ 97 90 dB (min) 0.01 0.02 % (max) Analog Input Section LINE_IN, AUX, CD, VIDEO, PC_BEEP, PHONE VIN Line Input Voltage VIN Mic Input with 20 dB Gain VIN Mic Input with 0 dB Gain Xtalk Crosstalk CD Left to Right -95 ZIN Input Impedance (6) All Analog Inputs 40 CIN Input Capacitance 15 pF CD Left to Right 0.01 dB 0 dB to 22.5 dB 1.5 dB 86 dB 1.5 dB 86 dB 18 Bits Interchannel Gain Mismatch 1 Vrms 0.1 Vrms 1 Vrms dB 10 kΩ (min) Record Gain Amplifier - ADC AS Step Size AM Mute Attenuation (6) Mixer Section AS Step Size +12 dB to -34.5 dB AM Mute Attenuation Analog to Digital Converters Resolution Dynamic Range (7) Frequency Response -60 dB Input THD+N, A-Weighted 90 -1 dB Bandwidth 20 86 dB (min) kHz Digital to Analog Converters Resolution THD 18 Dynamic Range (7) -60 dB Input THD+N, A-Weighted Total Harmonic Distortion VIN = -3 dB, f = 1 kHz, RL = 10 kΩ Frequency Response 89 dB (min) 0.01 % 20 - 21 k Hz Group Delay (7) DT Bits 85 2 ms (max) Out of Band Energy (8) -40 dB Stop Band Rejection 70 dB Discrete Tones -96 dB 1.5 dB 86 dB TBD Ω Analog Output Section AS Step Size AM Mute Attenuation ZOUT Output Impedance (7) 0 dB to -46.5 dB All Analog Outputs Digital I/O (7) VIH (5) (6) (7) (8) 4 0.40 x DVDD High level input voltage V (min) Loopthrough mode describes a path from an analog input through the analog mixers to an analog output. These specifications are ensured by design and characterization; they are not production tested. These specifications are ensured by design and characterization; they are not production tested. Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1 Vrms DAC output. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 5V, Fs = 48 kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. Symbol Parameter LM4548A Conditions Typical (3) Limit (4) Units (Limits) VIL Low level input voltage 0.30 x DVDD V (max) VOH High level output voltage 0.50 x DVDD V (min) VOL Low level output voltage 0.20 x DVDD V (max) IL Input Leakage Current AC Link inputs ±10 µA IL Tri state Leakage Current High impedance AC Link outputs IDR Output drive current AC Link outputs ±10 µA 5 mA 12.288 MHz Digital Timing Specifications (7) FBC BIT_CLK frequency TBCP BIT_CLK period TCH BIT_CLK high FSYNC SYNC frequency TSP TSH 81.4 Variation of BIT_CLK duty cycle from 50% ns ±20 % (max) 48 kHz SYNC period 20.8 µs SYNC high pulse width 1.3 µs TSL SYNC low pulse width 19.5 µs TDSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 15 ns (min) TDHOLD Hold Time for codec data input Hold time of SDATA_OUT from falling edge of BIT_CLK 5 ns (min) TSSETUP Setup Time for codec SYNC input SYNC to rising edge of BIT_CLK TBD ns (min) TSHOLD Hold Time for codec SYNC input Hold time of SYNC from rising edge of BIT_CLK TBD ns (min) TCO Output Valid Delay Output Delay of SDATA_IN from rising edge of BIT_CLK 15 ns (max) TRISE Rise Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns (max) TFALL Fall Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns (max) TRST_LOW RESET# active low pulse width For Cold Reset 1.0 µs (min) TRST2CLK RESET# inactive to BIT_CLK start up For Cold Reset TSH SYNC active high pulse width TSYNC2CLK TBD TBD 162.8 ns (min) For Warm Reset 1.3 TBD µs (min) SYNC inactive to BIT_CLK start up For Warm Reset TBD 162.8 ns (min) TS2_PDOWN AC Link Power Down Delay Delay from end of Slot 2 to BIT_CLK, SDATA_IN low 1 µs (max) TSUPPLY2RST Power On Reset Time from minimum valid supply levels to end of Reset 1 µs (min) TSU2RST Setup to trailing edge of RESET# For ATE Test Mode 15 ns (min) TRST2HZ Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns (max) Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 5 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com TIMING DIAGRAMS TBCH BIT_CLK BIT_CLK TCO TBCL TBCP SDATA_IN TDHOLD TSH TDSETUP SYNC SDATA_OUT TSL TSSETUP TSP SYNC Figure 1. Clocks SYNC BIT_CLK SDATA_IN SDATA_OUT TRISE TSHOLD Figure 2. Data Delay, Setup and Hold TFALL 90% 90% 10% Input: VIH Output: VOH Input: VIL Output: VOL 10% Figure 3. Digital Rise and Fall Figure 4. Legend TRST_LOW TRST2CLK RESET# BIT_CLK TSUPPLY2RST DVDD (min), AVDD (min) DVDD, AVDD Figure 5. Power On Reset TRST_LOW TRST2CLK RESET# BIT_CLK Figure 6. Cold Reset TSH TSYNC2CLK SYNC BIT_CLK Figure 7. Warm Reset 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 TYPICAL APPLICATION AVDD 27 nH. 3.3V or 5V Digital Supply 5V Analog Supply + + 1 PF 0.1 PF 1.0 PF 1.0 PF 1.0 PF Microphone Inputs 1.0 PF 1.0 PF Mono Inputs 1.0 PF 14 15 21 + Auxiliary Input 22 12 13 LINE_OUT_L LINE_IN_R LINE_OUT_R CD_L LNLVL_OUT_L CD_GND LNLVL_OUT_R CD_R VIDEO_L MONO_OUT VIDEO_R Z97 Digital Controller 6 8 10 11 33 pF 2 1 M: 33 pF 3 36 39 41 37 1.0 PF 1.0 PF 1.0 PF 1.0 PF 1.0 PF Line Output True Line Level Output Mono Output AVDD AUX_L AUX_R VREF 10 k: 27 + MIC1 MIC2 LM4548A PC_BEEP $& µ97 Rev 2 Codec 0.1 PF VREF_OUT 3DN PHONE 3DP 5 35 + + + 17 + 1.0 PF + Video Input + 16 1.0 PF + 20 + 1.0 PF LINE_IN_L + + 18 19 1.0 PF DVDD2 + 1.0 PF DVDD1 + + + 24 + CD Input 23 1.0 PF + 1.0 PF Line Input 0.1 PF 9 1 AVDD + 25 1 PF SDATA_OUT ID0# BIT_CLK ID1# 28 VREF Output (For external microphone bias) 0.022 PF Optional: for National 3D Sound 33 34 45 46 3.3 PF NC NC Default setting: Primary Codec (ID 00) SDATA_IN SYNC RESET# XTAL_IN XTAL_OUT 24.576 MHz AVSS DVSS1 DVSS2 26 4 7 Analog Ground Digital Ground NC NC NC NC NC NC NC NC NC NC NC 29 30 31 32 38 40 42 43 44 47 48 NC NC NC NC NC NC NC NC NC NC NC All NC pins should normally be left floating. See Pin Descriptions for details Connect Grounds at a single point underneath or close to the package Figure 8. LM4548A Typical Application Circuit, Single Codec, 1 Vrms Inputs Application Hints • • • • • • The LM4548A must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram VREF must be pulled high to AVDD with a 10 kΩ resistor to ensure correct operation Don't leave unused inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor (e.g. 0.1 µF) Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the CD channels and should be connected to the CD source ground (Analog Ground may also be acceptable) through a 1 µF capacitor If using a non-standard AC Link controller take care to keep the SYNC and SDATA_IN signals low during Cold Reset to avoid entering the ATE or Vendor test modes by mistake The PC_Beep input should be explicitly muted if not used since it defaults to 0 dB gain on reset, unlike the mute default of the other analog inputs. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 7 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Digital +3.3V Supply +7.5V - +20V C33 0.33 PF PC_BEEP AUXILIARY INPUT HEADER 2 C24 R17 1 PF 6.81k R16 Optional for LM4548A. Will improve transient response L1 27 nH. C11 0.1 PF C23 + 6.81k 9 4 7 C22 12 1 PF 15 14 20 19 18 24 23 28 + C21 R11 1 PF 6.81k C20 + R10 R8 C19 6.81k 22 C12 17 0.1 PF 16 13 R7 1 PF 6.81k R6 C18 R2 R19 10k C13 0.1 PF R4 2.2k C7 220 pF R3 C17 C30 2.2 PF C31 3.3 PF PC_BEEP AUX_R AUX_L CD_R CD_GND CD_L LINE_IN_R LINE_IN_L VREF_OUT 41 39 NC NC NC NC NC NC NC NC NC NC NC 29 30 31 32 38 40 42 43 44 47 48 LINE_OUT_R LINE_OUT_L 36 35 C27 1 PF ID0# ID1# 34 33 XTAL_IN C8 1k R24 47k SYNC RESET# MONO_OUT LM4548A 3DP BIT_CLK LNLVL_OUT_R LNLVL_OUT_L MIC2 VIDEO_R VIDEO_L PHONE 3DN SDATA_OUT 37 MIC1 VREF SDATA_IN SDATA_IN SDATA_OUT BIT_CLK SYNC RESET# XTAL_OUT 2 3 Y1 24.576 MHz 0.022 PF C29 1 PF C28 1 PF 1 PF C1 33 pF C2 33 pF R23 10k R22 10k C6 220 pF 4 3 5 2 1 TRUE LINE LEVEL JACK J6 LNLVL_OUT C5 220 pF LINE OUTPUT JACK C26 1 PF R25 1 M: + 47 27 DVSS1 DVSS2 U1 8 5 6 10 11 R21 10k C4 220 pF + 4 3 5 2 1 R5 1 PF 6.81k + 6.81k 45 46 25 AVDD + AVDD + 4 3 5 2 1 21 + LINE INPUT JACK R9 1 PF 6.81k + 6.81k 26 AVSS + 6.81k 1 DVDD1 C9 0.1 PF + R12 J3 CD_IN C25 R13 1 PF 6.81k + 6.81k + C16 1 PF C14 1 PF DVDD2 + R14 4 3 2 1 + R15 1 PF 6.81k CD INPUT HEADER J2 MIC1 Optional. Not required if LM78M05 is < 4 in. from an input filtering capacitor C32 0.1 PF GND + 6.81k J4 AUX_IN MICROPHONE JACK AVDD U2 3 + R18 4 3 2 1 J1 LINE_IN LM78M05 VIN VOUT 1 R20 10k 4 3 5 2 1 J5 LINE_OUT C3 220 pF R1 0: DGND AGND Figure 9. LM4548A Reference Design, Typical Application, Single Codec, 1 Vrms and 2 Vrms Inputs, EMC Output Filters 8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 MONO_OUT NC LNLVL_OUT_L NC LNLVL_OUT_R NC NC NC ID0# ID1# NC NC Connection Diagram 48 47 46 45 44 43 42 41 40 39 38 37 DVDD1 1 36 LINE_OUT_R XTL_IN 2 35 LINE_OUT_L XTL_OUT DVSS1 3 34 3DP 4 33 3DN SDATA_OUT 5 32 NC BIT_CLK DVSS2 6 31 NC 30 NC SDATA_IN DVDD2 8 29 LM4548A $& µ97 Rev 2 Codec 7 9 28 NC VREF_OUT SYNC 10 27 VREF RESET# 11 26 AVSS PC_BEEP 12 25 AVDD LINE_IN_R MIC2 LINE_IN_L MIC1 CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE 13 14 15 16 17 18 19 20 21 22 23 24 48 Pin LQFP - Top View See Package Number PT PIN DESCRIPTIONS ANALOG I/O Name PC_BEEP PHONE AUX_L Pin 12 13 14 I/O Functional Description I Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level can be muted or adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix signal feeds both the Line Out and Line Level Out analog outputs and is also selectable at the Record Select Mux. I Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can be muted or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. The Stereo Mix signal feeds both the Line Out and Line Level Out analog stereo outputs and is also selectable at the Record Select Mux. I Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_L level can be muted (along with AUX_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 9 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com ANALOG I/O (continued) Name AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 10 Pin 15 16 17 18 19 20 21 22 I/O Functional Description I Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_R level can be muted (along with AUX_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. I Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level can be muted (along with VIDEO_R) or adjusted from +12 dB to 34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. I Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_R level can be muted (along with VIDEO_L) or adjusted from +12 dB to 34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. I Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted (along with CD_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is mixed into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. I AC Ground Reference This input is the reference for the signals on both CD_L and CD_R. CD_GND is not a DC ground and must be AC-coupled to the stereo source ground common to both CD_L and CD_R. CD_GND, CD_L and CD_R act together as a quasi-differential stereo input such that signals common to both CD_L and CD_R are rejected. This can improve the input SNR for a stereo source with a good common ground but precision resistors may be needed in any external attenuators to achieve the necessary balance between the two channels. I Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted (along with CD_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. I Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the right or left channels of the Record Select Mux for conversion on either or both channels of the stereo ADCs. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing adjustments via Mic Volume register, 0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to the stereo outputs Line Out and Line Level Out. Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h. I Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the right or left channels of the Record Select Mux for conversion on either or both channels of the stereo ADCs. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing adjustments via Mic Volume register, 0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to the stereo outputs Line Out and Line Level Out. Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 ANALOG I/O (continued) Name LINE_IN_L Pin 23 I/O Functional Description I Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_L level can be muted (along with LINE_IN_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. LINE_IN_R 24 I Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_R level can be muted (along with LINE_IN_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out. LINE_OUT_L 35 O Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2 via the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along with LINE_OUT_R) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps. LINE_OUT_R 36 O Right Stereo Channel Output This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2 via the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along with LINE_OUT_L) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps. O Mono Output This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2, after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1. The optional Texas Instruments 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in the General Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register. MIX=0 selects a microphone input. Output level can be muted or adjusted from 0 dB to -46.5 dB in 1.5 dB steps via the Mono Volume register, 06h. O Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_L amplitude can be muted (along with LNLVL_OUT_R) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps O Right Stereo Channel Output This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_R amplitude can be muted (along with LNLVL_OUT_L) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps MONO_OUT LNLVL_OUT_L LNLVL_OUT_R 37 39 41 DIGITAL I/O AND CLOCKING Name XTL_IN Pin 2 I/O Functional Description I 24.576 MHz crystal or oscillator input To complete the oscillator circuit use a fundamental mode crystal operating in parallel resonance and connect a 1 MΩ resistor across pins 2 and 3. Choose the load capacitors (Figure 9, C1, C2) to suit the load capacitance required by the crystal (e.g. C1 = C2 = 33 pF for a 20 pF crystal). This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at standard logic levels (VIH, VIL). This pin is only used when the codec is in Primary mode. It may be left open (NC) for any Secondary mode. XTL_OUT 3 O 24.576 MHz crystal output Used with XTAL_IN to configure a crystal oscillator. When the codec is used with an external oscillator this pin should be left open (NC). When the codec is configured in a Secondary mode this pin is not used and may be left open (NC). SDATA_OUT 5 I Input to codec This is the input for AC Link Output Frames from an AC '97 Digital Audio Controller to the LM4548A codec. These frames can contain both control data and DAC PCM audio data. This input is sampled by the LM4548A on the falling edge of BIT_CLK. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 11 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com DIGITAL I/O AND CLOCKING (continued) Name I/O Functional Description BIT_CLK 6 I/O AC Link clock An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC Link. The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal input (XTL_IN). This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and would normally use the AC Link clock generated by a Primary Codec. SDATA_IN 8 O Output from codec This is the output for AC Link Input Frames from the LM4548A codec to an AC '97 Digital Audio Controller. These frames can contain both codec status data and PCM audio data from the ADCs. The LM4548A clocks data from this output on the rising edge of BIT_CLK. I AC Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is sampled on the rising edge of BIT_CLK and the codec takes the first positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored. SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is used to clear a power down state on the codec AC Link interface. I Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# must be used to initialize the LM4548A after Power On when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the LINE_OUT stereo output. I Codec Identity ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID0 bit to “0”. If left open (NC), ID0# is pulled High by an internal pull-up resistor. I Codec Identity ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID register, 28h. If the ID01# pin (pin 46) is connected to ground then the ID1 bit (D15, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID1 bit to “0”. If left open (NC), ID1 is pulled high by an internal pull-up resistor. SYNC RESET# ID0# ID1# 12 Pin 10 11 45 46 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 POWER SUPPLIES AND REFERENCES Name Pin I/O Functional Description AVDD 25 I Analog supply AVSS 26 I Analog ground DVDD1 1 I Digital supply DVDD2 9 I Digital supply DVSS1 4 I Digital ground DVSS2 7 I Digital ground VREF 27 O Nominal 2.2 V internal reference Not intended to sink or source current. Use short traces to bypass (3.3 µF, 0.1 µF) this pin to maximize codec performance. This pin must be tied to AVDD with a 10 kΩ pull-up resistor. VREF_OUT 28 O Nominal 2.2 V reference output Can source up to 5 mA of current and can be used to bias a microphone. 3D SOUND AND NO-CONNECTS (NC) Name Pin I/O Functional Description These pins are used to complete the Texas Instruments 3D Sound stereo enhancement circuit. Connect a 0.022 µF capacitor between pins 3DP and 3DN. Texas Instruments3D Sound can be turned on and off via the 3D bit (D13) in the General Purpose register, 20h. Texas Instruments 3D Sound uses a fixed-depth type stereo enhancement circuit hence the 3D Control register, 22h is read-only and is not programmable. If Texas Instruments 3D Sound is not needed, these pins should be left open (NC). 3DP, 3DN 33,34 O NC 29, 30, 31, 32, 38, 40 , 42, 43, 44, 47, 48 NC These pins are not used and should be left open (NC). For second source applications these pins may be connected to a noise-free supply or ground (e.g. AVDD or AVSS), either directly or through a capacitor. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 13 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS 14 ADC Noise Floor DAC Noise Floor Figure 10. Figure 11. Line Out Noise Floor (Analog Loopthrough) Line Level Out Noise Floor (Analog Loopthrough) Figure 12. Figure 13. ADC Frequency Response DAC Frequency Response Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 LM4548A Register Map REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0D40h MR4 MR3 MR2 MR1 MR0 8000h 00h Reset 02h Master Volume Mute X X ML4 ML3 ML2 ML1 ML0 X X X 04h Line Level Volume Mute X X ML4 ML3 ML2 ML1 ML0 X X X MR4 MR3 MR2 MR1 MR0 8000h 06h Mono Volume Mute X X X X X X X X X X MM4 MM3 MM2 MM1 MM0 8000h 0Ah PC_Beep Volume Mute X X X X X X X X X X PV3 PV2 PV1 PV0 X 0000h 0Ch Phone Volume Mute X X X X X X X X X X GN4 GN3 GN2 GN1 GN0 8008h 0Eh Mic Volume Mute X X X X X X X X 20dB X GN4 GN3 GN2 GN1 GN0 8008h 10h Line In Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 12h CD Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 14h Video Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 16h Aux Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 18h PCM Out Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h 1Ah Record Select X X X X X SL2 SL1 SL0 X X X X X SR2 SR1 SR0 0000h 1Ch Record Gain Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h 20h General Purpose POP X 3D X X X MIX MS LPBK X X X X X X X 0000h 22h 3D Control (Read Only) X 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0101h 24h Reserved X X X X X X X X X X X X X X X X 0000h 26h Powerdown Ctrl/Stat PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh 28h Extended Audio ID ID1 ID0 X X X X 0 0 0 0 X X 0 X 0 VRA X001h 2Ah Extended Audio Ctrl/Status X X X X X X X X X X X X X X X VRA 0000h 2Ch PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 32h PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h X 5Ah Vendor Reserved 1 X X X X X X X X X X X X X X X X 0000h X 74h Vendor Reserved 2 X X X X X X X X X X X X X X X X 0000h X 7Ah Vendor Reserved 3 X X X X X X X X X X X X X X X X 0000h 7Ch Vendor ID1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 4E53h 7Eh Vendor ID2 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 4348h Output Volume Input Volume ADC Sources X Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 15 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION General The LM4548A codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital interface simultaneously. ADC Inputs and Outputs All four of the stereo analog inputs and three of the mono analog inputs can be selected for conversion by the 18-bit stereo ADC. Digital output from the left and right channel ADCs is always located in AC Link Input Frame slots 3 and 4 respectively. Input level to either ADC channel can be muted or adjusted from the Record Gain register, 1Ch. Adjustments are in 1.5 dB steps over a gain range of 0 dB to +22.5 dB and both channels mute together (D15). Input selection for the ADC is through the Record Select Mux controlled from the Record Select register, 1Ah, together with microphone selection controlled by the MS bit (D8) in the General Purpose register, 20h. One of the stereo inputs, CD_IN, uses a quasi-differential 3-pin interface where both stereo channel inputs are referenced to the third pin, CD_GND. CD_GND should be AC coupled to the source ground and provides common-mode feedback to cancel ground noise. It is not a DC ground. The other three stereo inputs, LINE_IN, AUX and VIDEO are 2-pin interfaces, single-ended for each stereo channel, with analog ground (AVSS) as the signal reference. Either of the two mono microphone inputs can be muxed to a programmable boost amplifier before selection for either channel of the ADC. The Microphone Mux is controlled by the Microphone Selection (MS) bit (D8) in the General Purpose register 20h and the 20 dB programmable boost is enabled by the 20dB bit (D6) in register 0Eh. The mono PHONE input may also be selected for either ADC channel. Analog Mixing: Mix1 Five analog inputs are available for mixing at the stereo mixer, MIX1 – all four stereo and one mono, namely the microphone input selected by MS (D8, reg 20h). Digital input to the codec can be directed to either MIX1 or to MIX2 after conversion by the 18-bit stereo DAC and level adjustment by the PCM Out Volume control register (18h). Each input to MIX1 may be muted or level adjusted using the appropriate Mixer Input Volume Register: Mic Volume (0Eh), Line_In Volume (10h), CD Volume (12h), Video Volume (14h), Aux Volume (16h) and PCM Out Volume (18h). The mono microphone input is mixed equally into left and right stereo channels but stereo mixing is orthogonal, i.e. left channels are only mixed with other left channels and right with right. The left and right amplitudes of any stereo input may be adjusted independently however mute for a stereo input acts on both left and right channels. DAC Mixing and 3D Processing Control of routing the DAC output to MIX1 or MIX2 is by the POP bit (D15) in the General Purpose register, 20h. If MIX1 is selected (default, POP=0) then the DAC output is available for processing by the Texas Instruments 3D Sound circuitry. If MIX2 is selected, the DAC output will bypass the 3D processing. This allows analog inputs to be enhanced by the analog 3D Sound circuitry prior to mixing with digital audio. The digital audio may then use alternative digital 3D enhancements. Texas Instruments 3D Sound circuitry is enabled by the 3D bit (D13) in the General Purpose register, 20h, and is a fixed depth implementation. The 3D Control register, 22h, is therefore not programmable (read-only). The 3D Sound circuitry defaults to disabled after reset. Analog Mixing: Mix2 MIX2 combines the output of MIX1 (Stereo Mix 3D) with the two mono analog inputs, PHONE and PC_BEEP, these each level-adjusted by the input control registers Phone Volume (0Ch) and PC_Beep Volume (0Ah) respectively. If selected by the POP bit (D15, reg 20h), the DAC output is also summed into MIX2. Stereo Mix The output of MIX2 is the signal, Stereo Mix. Stereo Mix is used to drive both the Line output (LINE_OUT) and the Line Level output (LNLVL_OUT) and can also be selected as the input to the ADC by the Record Select Mux. In addition, the two channels of Stereo Mix are summed to form a mono signal (Mono Mix) also selectable by the Record Select Mux as an input to either channel of the ADC. 16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 Stereo Outputs The output volume from LINE_OUT and LNLVL_OUT can be muted or adjusted by 0 dB to 45 dB in nominal 3 dB steps under the control of the output volume registers Master Volume (02h) and Line Level Volume (04h) respectively. As with the input volume registers, adjustments to the levels of the two stereo channels can be made independently but both left and right channels share a mute bit (D15). Mono Output The mono output (MONO_OUT) is driven by one of two signals selected by the MIX bit (D9) in the General Purpose register, 20h. The signal selected by default (MIX = 0) is the mono summation of the two channels of Stereo Mix 3D, the stereo output of the mixer MIX1. Setting the control bit MIX = 1, selects a microphone input, MIC1 or MIC2. The choice of microphone is controlled by the Microphone Select (MS) bit (D8) also in the General Purpose register, 20h. Analog Loopthrough and Digital Loopback Analog Loopthrough refers to an all-analog signal path from an analog input through the mixers to an analog output. Digital Loopback refers to a mixed-mode analog and digital signal path from an analog input through the ADC, looped-back (LPBK bit – D7, 20h) through the DAC and mixers to an analog output. Resets COLD RESET is performed when RESET# (pin 11) is pulled low for > 1 µs. It is a complete reset. All registers and internal circuits are reset to their default state. It is the onlt reset which clears the ATE and Vendor test modes. WARM RESET is performed when SYNC (pin 10) is held high for > 1 µs and the codec AC Link digital interface is in powerdown (PR4 = 1, Powerdown Control / Status register, 26h). It is used to clear PR4 and power up the AC Link digital interface but otherwise does not change the contents of any registers nor reset any internal circuitry. REGISTER RESET is performed when any value is written to the RESET register, 00h. It resets all registers to their default state and will modify circuit configurations accordingly but does not reset any other internal circuits. AC Link Serial Interface Protocol SLOT # 0 1 2 3 4 5 TAG CMD ADR CMD DATA PCM LEFT PCM RIGHT RSRV 6 7 8 9 10 11 12 SYNC AC LINK OUTPUT FRAMES: SDATA_OUT RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV RSRV Codec ID: to select target codec in multiple codec configurations AC LINK INPUT FRAMES: SDATA_IN TAG STAT ADR STAT DATA PCM LEFT PCM RIGHT RSRV RSRV RSRV RSRV RSRV Slot Request bits, 11 & 10: to request data from Output Frame slots 3 & 4 TAG PHASE DATA PHASE Figure 16. AC Link Bidirectional Audio Frame Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 17 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Tag Phase Data Phase 20.8 Ps (48 kHz) SYNC BIT_CLK SDATA_OUT End of previous Audio Frame Valid Frame Slot (1) Slot (4) ID1 ID0 Tag bits: &Œ u v ^o}š ^s o] _ ]š•, Codec ID Slot (x) = ³1´ LQGLFDWHV WLPH VORW x contains valid PCM data Codec ID = (ID1, ID0) - codec address for multiple codecs Bit 19 Bit 0 SLOT 1 Read / Write Request, Command Address Bit 19 Slot 2 Bit 0 Slot 12 SLOTS 2 to 12 Data: Command and Audio Figure 17. AC Link Output Frame AC Link Output Frame: SDATA_OUT, Controller Output to LM4548A Input The AC Link Output Frame carries control and PCM data to the LM4548A control registers and stereo DAC. Output Frames are carried on the SDATA_OUT signal which is an output from the AC '97 Digital Controller and an input to the LM4548A codec. As shown in Figure 16, Output Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. Each Frame consists of 256 bits with each of the twelve Data Slots containing 20 bits. Input and Output Frames are aligned to the same SYNC transition. Note that since the LM4548A is a two channel codec, it only accepts data in 4 of the twelve Data Slots – 2 for control, one each for PCM data to the left and right channel DACs. Data Slot 3 & 4 are used to stream data to the stereo DAC for all modes selected by the Identity pins ID1#, ID0#. A new Output Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller on a rising edge of BIT_CLK and, as shown in Figure 17 and Figure 18, the first tag bit in the Frame (“Valid Frame”) should be clocked from the controller by the next rising edge of BIT_CLK and sampled by the LM4548A on the following falling edge. The AC '97 Controller should always clock data to SDATA_OUT on a rising edge of BIT_CLK and the LM4548A always samples SDATA_OUT on the next falling edge. SYNC is sampled with the rising edge of BIT_CLK. The LM4548A checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high transition on SYNC) before 256 bits are received from the old Frame then the new Frame is ignored i.e. the data on SDATA_OUT is discarded until a valid new Frame is detected. The LM4548A expects to receive data MSB first, in an MSB justified format. SDATA_OUT: Slot 0 – Tag Phase The first bit of Slot 0 is designated the "Valid Frame" bit. If this bit is 1, it indicates that the current Output Frame contains at least one slot of valid data and the LM4548A will check further tag bits for valid data in the expected Data Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated tag bit equal to 1. Since it is a two channel codec the LM4548A can only receive data from four slots in a given frame and so only checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1 (Command Address), slot 2 (Command Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data for right DAC). 18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 The last two bits in the Tag contain the Codec ID used to select the target codec to receive the frame in multiple codec systems. When the frame is being sent to a codec in one of the Secondary modes the controller does not use bits 14 and 13 to indicate valid Command Address and Data in slots 1 and 2. Instead, this role is performed by the Codec ID bits – operation of the Extended AC Link assumes that the controller would not access a secondary codec unless it was providing valid Command Address and/or Data. When in one of the secondary modes the LM4548A only checks the tag bits for the Codec ID and for valid data in the two audio data slots 3 & 4. When sending an Output Frame to a Secondary mode codec, a controller should set tag bits 14 and 13 to zero. LM4548A samples SYNC assertion LM4548A samples first bit of SDATA_OUT SYNC BIT_CLK Valid Frame SDATA_OUT Slot (1) Slot (2) End of previous Audio Frame Figure 18. Start of AC Link Output Frame Slot 0, Output Frame Bit Description 15 Valid Frame Comment 14 Control register address 13 Control register data 12 Left DAC data in Slot 3 1 = Valid PCM Data in Slot 3 (Primary & all Secondary modes) 1 = Valid PCM Data in Slot 4 (Primary & all Secondary modes) 1 = Valid data in at least one slot. 1 = Valid Control Address in Slot 1 (Primary codec only) 1 = Valid Control Data in Slot 2 (Primary codec only) 11 Right DAC data in Slot 4 10:2 Not Used Controller should stuff these slots with “0”s 1,0 Codec ID (ID1, ID0) The codec ID is used in a multi-codec system to identify the target Secondary codec for the Control Register address and/or data sent in the Output Frame SDATA_OUT: Slot 1 – Read/Write, Control Address Slot 1 is used by a controller to indicate both the address of a target register in the LM4548A and whether the access operation is a register read or register write. The MSB of slot 1 (bit 19) is set to 1 to indicate that the current access operation is 'read'. Bits 18 through 12 are used to specify the 7-bit register address of the read or write operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC '97 controller. Slot 1, Output Frame Bits Description 19 Read/Write 18:12 Register Address 11:0 Reserved Comment 1 = Read 0 = Write Identifies the Status/Command register for read/write Controller should set to "0" Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 19 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com SDATA_OUT: Slot 2 – Control Data Slot 2 is used to transmit 16-bit control data to the LM4548A when the access operation is 'write'. The least significant four bits should be stuffed with zeros by the AC '97 controller. If the access operation is a register read, the entire slot, bits 19 through 0 should be stuffed with zeros. Slot 2, Output Frame Bits Description 19:4 Control Register Write Data Comment 3:0 Reserved Controller should stuff with zeros if operation is “read” Set to "0" SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC for all codec Primary and Secondary modes. Any unused bits should be stuffed with zeros. The LM4548A DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). Slots 3 & 4, Output Frame Bits Description 19:0 PCM DAC Data (Left /Right Channels) Comment Slots used to stream data to DACs for all Primary or Secondary modes. Set unused bits to "0" SDATA_OUT: Slots 5 to 12 – Reserved These slots are not used by the LM4548A and should all be stuffed with zeros by the AC '97 Controller. Tag Phase Data Phase 20.8 Ps (48 kHz) SYNC BIT_CLK SDATA_IN End of previous Audio Frame Codec Ready Slot (1) Slot (4) ^0_ ^0_ Bit 19 Tag bits: } Z Ç v ^o}š ^s o] _ ]š• Slot (x) = ³1´ LQGLFDWHV WLPH VORW x contains valid PCM data Bit 0 SLOT 1 Status Address / Slot Request bits for VSA Bit 19 Slot 2 Bit 0 Slot 12 SLOTS 2 to 12 Data: Status and Audio Figure 19. AC Link Input Frame AC Link Input Frame: SDATA_IN, Controller Input from LM4548A Output The AC Link Input Frame contains status and PCM data from the LM4548A control registers and stereo ADC. Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and an output from the LM4548A codec. As shown in Figure 16, Input Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the LM4548A. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the validity of the data in the four of the twelve following Data Slots that are used by the LM4548A. Each Frame consists of 256 bits with each of the twelve data slots containing 20 bits. 20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller on a rising edge of BIT_CLK and, as shown in Figure 19 and Figure 20, the first tag bit in the Frame (“Codec Ready”) is clocked from the LM4548A by the next rising edge of BIT_CLK. The LM4548A always clocks data to SDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next falling edge. The LM4548A samples SYNC on the rising edge of BIT_CLK. Input and Output Frames are aligned to the same SYNC transition. The LM4548A checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high transition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored i.e. no valid data is sent on SDATA_IN until a valid new Frame is detected. The LM4548A transmits data MSB first, in a MSB justified format. All reserved bits and slots are stuffed with "0"s by the LM4548A. LM4548A samples SYNC assertion LM4548A outputs first bit of SDATA_IN SYNC BIT_CLK Codec Ready SDATA_IN Slot (1) Slot (2) End of previous Audio Frame Figure 20. Start of AC Link Input Frame SDATA_IN: Slot 0 – Codec/Slot Status Bits The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link Input Frame indicates when the codec's AC Link digital interface and its status/control registers are fully operational. The digital controller is then able to read the LSBs from the Powerdown Control/Stat register (26h) to determine the status of the four main analog subsections. It is important to check the status of these subsections after Initialization, Cold Reset or the use of the powerdown modes in order to minimize the risk of distorting analog signals passed before the subsections are ready. The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1, 2, 3 and 4, respectively, are valid. Slot 0, Input Frame Bit Description Comment 15 Codec Ready Bit 1 = AC Link Interface Ready 14 Slot 1 data valid 1 = Valid Status Address or Slot Request 13 Slot 2 data valid 1 = Valid Status Data 12 Slot 3 data valid 1 = Valid PCM Data (Left ADC) 11 Slot 4 data valid 1 = Valid PCM Data (Right ADC) Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 21 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com SDATA_IN: Slot 1 – Status Address / Slot Request Bits This slot echoes (in bits 18 – 12) the 7-bit address of the codec control/status register received from the controller as part of a read-request in the previous frame. If no read-request was received, the codec stuffs these bits with zeros. Bits 11, 10 are Slot Request bits that support the Variable Rate Audio (VRA) capabilities of the LM4548A. For all codec Primary and Secondary modes, the left and right channels of the DAC take PCM data from slots 3 and 4 in the Output Frame respectively. The codec will therefore use bits 11 and 10 to request DAC data from these two slots. If bit 11 and 10 are set to 0, the controller should respond with valid PCM data in slots 3 and 4 of the next Output Frame. If bits 11 and 10 are set to 1, the controller should not send data. The codec has full control of the slot request bits. By default, data is requested in every frame, corresponding to a sample rate equal to the frame rate (SYNC frequency) – 48 kHz when XTAL_IN = 24.576 MHz. To send samples at a rate below the frame rate, a controller should set VRA = 1 (bit 0 in the Extended Audio Control/Status register, 2Ah) and program the desired rate into the PCM DAC Rate register, 2Ch. Both DAC channels operate at the same sample rate. Values for common sample rates are given in the Register Descriptions section (Sample Rate Control Registers, 2Ch, 32h) but any rate between 4 kHz and 48 kHz (to a resolution of 1 Hz) is supported. Slot Requests from the LM4548A are issued completely deterministically. For example if a sample rate of 8000 Hz is programmed into 2Ch then the LM4548A will always issue a slot request in every sixth frame. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800 Hz will cause slot requests to be spaced alternately five and six frames apart. This determinism makes it easy to plan task scheduling on a system controller and simplifies application software development. The LM4548A will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. For example, if the LM4548A is expecting data at a 8000 Hz rate yet the AC '97 Digital Audio Controller continues to send data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the DAC. The rest will be discarded. Bits 9 – 2 are request bits for slots not used by the LM4548A and are stuffed with zeros. Bits 1 and 0 are reserved and are also stuffed with zeros. Slot 1, Input Frame Bits Description 19 Reserved Comment 18:12 Status Register Index 11 Slot 3 Request bit (For left DAC PCM data) 0 = Controller should send valid data in Slot 3 of the next Output Frame 10 Slot 4 Request bit (For right DAC PCM data) 0 = Controller should send valid data in Slot 4 of the next Output Frame 9:2 Unused Slot Request bits Stuffed with "0"s by LM4548A 1,0 Reserved Stuffed with "0"s by LM4548A Stuffed with "0" by LM4548A Echo of the requested Status Register address 1 = Controller should not send Slot 3 data 1 = Controller should not send Slot 4 data SDATA_IN: Slot 2 – Status Data This slot returns 16-bit status data read from a codec control/status register. The codec sends the data in the frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request was made in the previous frame the codec will stuff this slot with zeros. Slot 2, Input Frame 22 Bits Description 19:4 Status Data 3:0 Reserved Comment Data read from a codec control/status register. Stuffed with “0”s if no read-request in previous frame. Stuffed with "0"s by LM4548A Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 SDATA_IN: Slot 3 – PCM Record Left Channel This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selected using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record Gain amplifier to the ADC. This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2 LSBs are stuffed with zeros. Table 1. Slot 3, Input Frame Bits Description 19:2 PCM Record Left Channel data Comment 1:0 Reserved 18-bit PCM sample from left ADC Stuffed with "0"s by LM4548A SDATA_IN: Slot 4 – PCM Record Right Channel This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record Gain amplifier to the ADC. This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2 LSBs are stuffed with zeros. Slot 4, Input Frame Bits Description 19:2 PCM Record Right Channel data Comment 1:0 Reserved 18-bit PCM sample from right ADC Stuffed with "0"s by LM4548A SDATA_IN: Slots 5 to 12 – Reserved Slots 5 – 12 of the AC Link Input Frame are not used for data by the LM4548A and are always stuffed with zeros. Register Descriptions Default settings are indicated by *. Reset Register (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values. If a read is performed on this register, the LM4548A will return a value of 0D40h. This value can be interpreted in accordance with the AC '97 specification to indicate that Texas Instruments 3D Sound is implemented and 18-bit data is supported for both the ADCs and DACs. Master Volume Register (02h) This output register allows the output level from either channel of the stereo LINE_OUT to be muted or attenuated over the range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are 5 bits of volume control for each channel and both stereo channels can be individually attenuated. The mute bit (D15) acts simultaneously on both stereo channels of LINE_OUT. Mute Mx4:Mx0 0 0 0000 0dB attenuation Function 0 1 1111 46.5dB attenuation 1 X XXXX *mute Default: 8000h Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 23 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Line Level Volume Register (04h) This output register allows the level from both channels of LNLVL_OUT to be muted or individually attenuated over the range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are 5 bits of volume control for each channel plus one mute bit. The mute bit (D15) acts on both channels. Operation of this register and LNLVL_OUT matches that of the Master Volume register and the LINE_OUT output. Mono Volume Register (06h) This output register allows the level from MONO_OUT to be muted or attenuated over the range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are 5 bits of volume control and one mute bit (D15). Mute MM4:MM0 Function 0 0 0000 0dB attenuation 0 1 1111 46.5dB attenuation 1 X XXXX *mute Default: 8000h PC Beep Volume Register (0Ah) This input register adjusts the level of the mono PC_BEEP input to the stereo mixer MIX2 where it is summed equally into both channels of the Stereo Mix signal. PC_BEEP can be both muted and attenuated over a range of 0 dB to 45 dB in nominal 3 dB steps. Note that the default setting for the PC_Beep Volume register is 0 dB attenuation rather than mute. Mute PV3:PV0 0 0000 *0dB attenuation Function 0 1111 45dB attenuation 1 XXXX mute Default: 0000h Mixer Input Volume Registers (Index 0Ch - 18h) These input registers adjust the volume levels into the stereo mixers MIX1 and MIX2. Each channel may be adjusted over a range of +12dB gain to 34.5dB attenuation in 1.5dB steps. For stereo ports, volumes of the left and right channels can be independently adjusted. Muting a given port is accomplished by setting the MSB to 1. Setting the MSB to 1 for stereo ports mutes both the left and right channels. The Mic Volume register (0Eh) controls an additional 20dB boost for the selected microphone input by setting the 20dB bit (bit D6). Mute Gx4:Gx0 0 0 0000 +12dB gain Function 0 0 1000 0dB gain 0 1 1111 34.5dB attenuation 1 X XXXX *mute Default: 8008h (mono registers); 8808h (stereo registers) 24 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 Record Select Register (1Ah) This register independently controls the sources for the right and left channels of the stereo ADC. The default value of 0000h corresponds to selecting the (mono) Mic input for both channels. SL2:SL0 Source for Left Channel ADC 0 *Mic input 1 CD input (L) 2 VIDEO input (L) 3 AUX input (L) 4 LINE_IN input (L) 5 Stereo Mix (L) 6 Mono Mix 7 PHONE input SR2:SR0 Source for Right Channel ADC 0 *Mic input 1 CD input (R) 2 VIDEO input (R) 3 AUX input (R) 4 LINE_IN input (R) 5 Stereo Mix (R) 6 Mono Mix 7 PHONE input Default: 0000h Record Gain Register (1Ch) This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record Select Mux and are selected via the Record Select Control register, 1Ah. The gain of each channel can be individually programmed from 0dB to +22.5dB in 1.5dB steps. Both channels can also be muted by setting the MSB to 1. Record Gain Register (1Ch) Mute Gx3:Gx0 0 1111 22.5dB gain Function 0 0000 0dB gain 1 XXXX *mute Default: 8000h Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 25 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com General Purpose Register (20h) This register controls many miscellaneous functions implemented on the LM4548A. The miscellaneous control bits include POP which allows the DAC output to bypass the Texas Instruments 3D Sound circuitry, 3D which enables or disables the Texas Instruments 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which controls the Microphone Selection mux and LPBK which connects the output of the stereo ADC to the input of the stereo DAC. LPBK provides a mixed-mode analog and digital loopback path between analog inputs and analog outputs. BIT POP 3D MIX MS LPBK Function PCM Out Path: *0 = 3D allowed 1 = 3D bypassed Texas Instruments 3D Sound: *0 = off 1 = on Mono output select: *0 = Mix 1 = Mic Mic select: *0 = MIC1 1 = MIC2 ADC/DAC Loopback: *0 = No Loopback 1 = Loopback Default: 0000h 3D Control Register (22h) This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2 Specification, the fixed depth and center characteristics of the Texas Instruments 3D Sound stereo enhancement. BIT POP 3D MIX MS LPBK Function PCM Out Path: *0 = 3D allowed 1 = 3D bypassed Texas Instruments 3D Sound: *0 = off 1 = on Mono output select: *0 = Mix 1 = Mic Mic select: *0 = MIC1 1 = MIC2 ADC/DAC Loopback: *0 = No Loopback 1 = Loopback Default: 0000h 26 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 Powerdown Control / Status Register (26h) This read/write register is used both to monitor subsystem readiness and also to program the LM4548A powerdown states. The 4 LSBs indicate status and 6 of the 8 MSBs control powerdown. The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage, Analog mixers and amplifiers, DAC section, ADC section. When the "Codec Ready" indicator bit in the AC Link Input Frame (SDATA_IN: slot 0, bit 15) is a "1", it indicates that the AC Link and AC '97 registers are in a fully operational state and that control and status information can be transferred. It does not indicate that the codec is ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determine that readiness, the Controller must check that the 4 LSBs of this register are set to “1” indicating that the appropriate audio subsections are ready. The powerdown bits PR0 – PR5 control internal subsections of the codec. They are implemented in compliance with AC '97 Rev 2 to support the standard device power management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification. PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits (MIX1, MIX2, Texas Instruments 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixer circuits as PR2. PR4 powers down the AC Link digital interface – see Figure 21 for signal powerdown timing. PR5 disables internal clocks. PR6 and PR7 are not used. BIT# BIT 0 ADC 1 = ADC section ready to transmit data Function: Status 1 DAC 1 = DAC section ready to accept data 2 ANL 1 = Analog mixers ready 3 REF 1 = VREF is up to nominal level BIT# BIT 8 PR0 1 = Powerdown ADCs and Record Select Mux Function: Powerdown 9 PR1 1 = Powerdown DACs 10 PR2 1 = Powerdown Analog Mixer (VREF still on) 11 PR3 1 = Powerdown Analog Mixer (VREF off) 12 PR4 1 = Powerdown AC Link digital interface (BIT_CLK off) 13 PR5 1 = Disable Internal Clock 14 PR6 Not Used 15 PR7 Not Used Default: 000Xh Extended Audio ID Register (28h) This read-only register identifies which AC '97 Extended Audio features are supported. The LM4548A features VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec support). VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0# (pins 46, 45). Codec mode selections are shown in the table below. Pin 46 (ID1#) Pin 45 (ID0#) D15,28h (ID1) D14,28h (ID0) Codec Identity Mode NC/VDD NC/VDD 0 0 Primary NC/VDD GND 0 1 Secondary 1 GND NC/VDD 1 0 Secondary 2 GND GND 1 1 Secondary 3 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 27 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Extended Audio Status/Control Register (2Ah) This read/write register provides status and control of the variable sample rate capabilities in the LM4548A. Setting the LSB of this register to "1" enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample rates to be programmed via registers 2Ch and 32h respectively. BIT VRA Function *0 = VRA off (Frame-rate sampling) 1 = VRA on Default: 0000h Sample Rate Control Registers (2Ch, 32h) These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DAC Rate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled via bit 0 of the Extended Audio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be any value from 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample rate, e.g. 800010 = 1F40h. Below is a list of the most common sample rates and the corresponding register (hex) values. Common Sample Rates SR15:SR0 Sample Rate (Hz) 1F40h 8000 2B11h 11025 3E80h 16000 5622h 22050 AC44h 44100 *BB80h *48000 Vendor ID Registers (7Ch, 7Eh) These two read-only (4E53h, 4348h) registers contain Texas Instruments' Vendor ID and Texas Instruments' LM45xx codec version designation. The first 24 bits represent the two ASCII characters “TI” which is Texas Instruments' Vendor ID for Microsoft's Plug and Play. The last 8 bits are the two binary-coded-decimal characters, 4, 8 and identify the codec to be an LM4548A Reserved Registers Do not write to reserved registers. In particular, do not write to registers 24h, 5Ah, 74h and 7Ah. All registers not listed in the LM4548A Register Map are reserved. Reserved registers will return 0000h if read. Low Power Modes The LM4548A provides 6 bits to control the powerdown state of internal analog and digital subsections and clocks. These 6 bits (PR0 – PR5) are located in the 8 MSBs of the Powerdown Control/Status register, 26h. The status of the four main analog subsections is given by the 4 LSBs in the same register, 26h. The powerdown bits are implemented in compliance with AC '97 Rev 2 to support the standard device power management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification. PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits (MIX1, MIX2, Texas Instruments 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixer circuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 21 for signal powerdown timing. PR5 disables internal clocks but leaves the crystal oscillator and BIT_CLK running (needed for minimum Primary mode powerdown dissipation in multi-codec systems). PR6 and PR7 are not used. After a subsection has undergone a powerdown cycle, the appropriate status bit(s) in the Powerdown Control/Status register (26h) must be polled to confirm readiness. In particular the startup time of the VREF circuitry depends on the value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel is recommended). 28 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 When the AC Link Digital Interface is powered down the codec output signals SDATA_IN and BIT_CLK (Primary mode) are cleared to zero and no control data can be passed between controller and codec(s). This powerdown state can be cleared in two ways: Cold Reset (RESET# = 0) or Warm Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all registers back to their default values (including clearing PR4) whereas Warm Reset only clears the PR4 bit and restarts the AC Link Digital Interface leaving all register contents otherwise unaffected. For Warm Reset ( see TIMING DIAGRAMS), the SYNC input is used asynchronously. The LM4548A codec allows the AC Link digital interface powerdown state to be cleared immediately so that its duration can be essentially as short as TSH, the Warm Reset pulse width. However, for conformance with AC '97 Rev 2, Warm Reset should not be applied within four frame times of powerdown i.e. the AC Link powerdown state should be allowed to last at least 82.8 µs. SYNC BIT_CLK SDATA_OUT Slot 12 Prev. Frame TAG Write to REG. 26h Data PR4 = 1 SDATA_IN Slot 12 Prev. Frame TAG Slot 0 Slot 1 Slot 2 Note: BIT_CLK and data transitions are not to scale TS2_PDOWN Figure 21. AC Link Powerdown Timing Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog and digital grounds separate, and connecting them together in only one place. Some designers show the connection as a zero ohm resistor, which allows naming the nets separately. Although it is possible to use a two layer board, it is recommended that a minimum of four layers be used, with the two inside layers being analog ground and digital ground. If EMI is a system consideration, then as many as eight layers have been successfully used. The 12 and 25 MHz. clocks can have significant harmonic content depending on the rise and fall times. With the exception of the digital VDD pins, (covered later) bypass capacitors should be very close to the package. The analog VDD pins should be supplied from a separate regulator to reduce noise. By operating the digital portion on 3.3V instead of 5V, an additional 0.5-0.7 db improvement can be obtained. Depending on power supply layout, routing, and capacitor ESR, a device instability can occur, resulting in increased noise on the outputs. This can be eliminated by adding an inductor in the digital supply line between the supply bypass capacitors and the DVDD pins, which increases the high frequency impedance of the supply as seen by the part. This “current starving” technique slows down internal rise and fall times, which will improve the signal to noise ratio, especially at low temperatures. In addition, the EMI radiated from the board is also reduced. Multiple Codecs Extended AC Link Up to four codecs can be supported on the extended AC Link. These multiple codec implementations should run off a common BIT_CLK generated by the Primary Codec. All codecs share the AC '97 Digital Controller output signals, SYNC, SDATA_OUT, and RESET#. Each codec, however, supplies its own SDATA_IN signal back to the controller, with the result that the controller requires one dedicated input pin per codec (Figure 22). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 29 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com By definition there can be one Primary Codec and up to three Secondary Codecs on an extended AC Link. The Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Secondary Codecs take identities equal to 01, 10 or 11. The Codec Identity is used as a chip select function. This allows the Command and Status registers in any of the codecs to be individually addressed although the access mechanism for Secondary Codecs differs slightly from that for a Primary. The Identity control pins, ID1#, ID0# (pins 46 and 45) are internally pulled up to DVDD. The Codec may therefore be configured as 'Primary' either by leaving ID1, ID0 open (NC) or by strapping them externally to Digital VDD. The difference between Primary and Secondary codec modes is in their timing source and in the Tag Bit handling in Output Frames for Command/Status register access. For a timing source, a Primary codec divides down by 2 the frequency of the signal on XTAL_IN and also generates this as the BIT_CLK output for the use of the controller and any Secondary codecs. Secondary codecs use BIT_CLK as an input and as their timing source and do not use XTAL_IN or XTAL_OUT. The use of Tag Bits is described below. Secondary Codec Register Access For Secondary Codec access, the controller must set the tag bits for Command Address and Data in the Output Frame as invalid (i.e. equal to 0). The Command Address and Data tag bits are in slot 0, bits 14 and 13 and Output Frames are those in the SDATA_OUT signal from controller to codec. The controller must also place the non-zero value (01, 10, or 11) corresponding to the Identity (ID1, ID0) of the target Secondary Codec into the Codec ID field (slot 0, bits 1 and 0) in that same Output Frame. The value set in the Codec ID field determines which of the three possible Secondary Codecs is accessed. Unlike a Primary Codec, a Secondary Codec will disregard the Command Address and Data tag bits when there is a match between the 2-bit Codec ID value (slot 0, bits 1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the Codec-ID/Identity match to indicate that the Command Address in slot 1 and Command Data in slot 2 are valid. When reading from a Secondary Codec, the controller must send the correct Codec ID bits (i.e. the target Codec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address (slot 1, bits 18 – 12). To write to a Secondary Codec, a controller must send the correct Codec ID bits when slot 1 contains a valid target register address and “write” indicator bit and slot 2 contains valid target register data. A write operation is only valid if the register address and data are both valid and sent within the same frame. When accessing the Primary Codec, the Codec ID bits are cleared and the tag bits 14 and 13 resume their role indicating the validity of Command Address and Data in slots 1 and 2. The use of the tag bits in Input Frames (carried by the SDATA_IN signal) is the same for Primary and Secondary Codecs. The Codec Identity is determined by the input pins ID1#, ID0# (pins 46 and 45) and can be read as the value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h of the target codec. Slots in the AC Link Output Frame are always mapped to carry data to the left DAC channel in slot 3 and data to the right DAC channel in slot 4. Similarly, slots in AC Link Input Frames are always mapped such that PCM data from the left ADC channel is carried by slot 3 and PCM data from the right ADC channel by slot 4. Output Frames are those carried by the SDATA_OUT signal from the controller to the codec while Input Frames are those carried by the SDATA_IN signal from the codec to the controller. Slot 0: Tag bits in Output Frames (controller to codec) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Valid Frame Slot 1 Valid Slot 2 Valid Slot 3 Valid Slot 4 Valid X X X X X X X X X ID1 ID0 Extended Audio ID register (28h): Support for Multiple Codecs Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 28h Extended Audio ID ID1 ID0 X X X X X X X X X X X X X VRA X001h 30 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 [97 DIGITAL CONTROLLER [97 PRIMARY MASTER: ID = 00 SYNC Line_Out_L SYNC BIT_CLK BIT_CLK Slots 3 & 4 SDATA_OUT RESET# Line_Out_R SDATA_OUT DVDD/NC RESET# SDATA_IN0 SDATA_IN SDATA_IN1 XTAL_IN SDATA_IN2 XTAL_OUT ID1# ID0# DVDD/NC 46 45 SDATA_IN3 [97 SECONDARY 1 DOCKING: ID = 01 Line_Out_L SYNC BIT_CLK Slots 3 & 4 Line_Out_R SDATA_OUT DVDD/NC RESET# SDATA_IN ID1# ID0# 46 45 $& ¶97 SECONDARY 2 ID = 10 Line_Out_L SYNC BIT_CLK Slots 3 & 4 Line_Out_R SDATA_OUT RESET# SDATA_IN ID1# 46 ID0# 45 DVDD/NC $& ¶97 SECONDARY 3 ID = 11 Line_Out_L SYNC BIT_CLK Slots 3 & 4 Line_Out_R SDATA_OUT RESET# SDATA_IN ID1# ID0# 46 45 Figure 22. Multiple Codecs Using Extended AC Link Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 31 OBSOLETE LM4548A SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Test Modes AC '97 Rev 2 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is sampled high by the trailing edge (zero-to-one transition) of RESET#. In ATE test mode the codec AC Link outputs SDATA_IN and BIT_CLK are configured to a high impedance state to allow tester control of the AC Link interface for controller testing. ATE test mode timing parameters are given in the Electrical Characteristics table. The Vendor test mode is entered if SYNC is sampled high by the zero-to-one transition of RESET#. Neither of these entry conditions can occur in normal AC Link operation but care must be taken to avoid mistaken activation of the test modes when using non standard controllers. 32 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A OBSOLETE LM4548A www.ti.com SNOS988D – NOVEMBER 2002 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 32 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4548A 33 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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