ispLSI 1016EA ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Functionally Compatible with ispLSI 1016E • NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems (VCCIO Pin) — Open-Drain Output Option B7 D Q A2 Logic A3 Array B6 B5 D Q D Q GLB B4 B3 A4 D Q EW Output Routing Pool A0 A1 Output Routing Pool Features A5 A6 Global Routing Pool (GRP) pM 5V AC H D 4 ES A IG 5 F N O S R N A7 B2 B1 B0 CLK E2CMOS® TECHNOLOGY • HIGH-PERFORMANCE — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power 0139C/1016EA Description The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port. The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options. • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping SE is • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity U The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (Figure 1). There are a total of 16 GLBs in the ispLSI 1016EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and a dedicated input. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016ea_02.1 1 April 2007 Specifications ispLSI 1016EA Functional Block Diagram Figure 1. ispLSI 1016EA Functional Block Diagram VCCIO Generic Logic Blocks (GLBs) GOE 0 I/O 31 I/O 30 I/O 29 I/O 28 I/O 12 I/O 13 I/O 14 I/O 15 B5 A2 A3 Global Routing Pool (GRP) A4 B4 B3 B2 pM 5V AC H D 4 ES A IG 5 F N O S R Input Bus I/O 8 I/O 9 I/O 10 I/O 11 Output Routing Pool (ORP) I/O 4 I/O 5 I/O 6 I/O 7 A5 lnput Bus B6 A1 Output Routing Pool (ORP) A0 N EW B7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 B1 A6 B0 A7 TDI Clock Distribution Network TMS TCK Y0 Y1/RESET* Megablock TDO *Note: Y1 and RESET are multiplexed on the same pin U SE is The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 2 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pin to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V-compatible voltages. Eight GLBs, 16 I/O cells, a dedicated input (if available) and one ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1016EA device contains two Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 0139/1016EA Clocks in the ispLSI 1016EA device are selected using the Clock Distribution Network. Two dedicated clock pins (Y0 and Y1) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016EA device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 1016EA are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. 2 Specifications ispLSI 1016EA Boundary Scan Figure 2. Boundary Scan Waveforms and Timing Specifications TMS Tbtsu Tbtch N EW TDI Tbth Tbtcl Tbtcp pM 5V AC H D 4 ES A IG 5 F N O S R TCK Tbtvo TDO Tbtco Valid Data Tbtcpsu Data to be captured Tbtoz Valid Data Tbtcph Data Captured Tbtuov Data to be driven out Tbtuco Valid Data Parameter is Symbol Tbtuoz Valid Data Min Max Units TCK [BSCAN test] clock pulse width 100 – ns tbtch TCK [BSCAN test] pulse width high 50 – ns tbtcl TCK [BSCAN test] pulse width low 50 – ns tbtsu TCK [BSCAN test] setup time 20 – ns TCK [BSCAN test] hold time 25 – ns TCK [BSCAN test] rise and fall time 50 – mV/ns tbtco TAP controller falling edge of clock to valid output – 25 ns tbtoz TAP controller falling edge of clock to data output disable – 25 ns tbtvo TAP controller falling edge of clock to data output enable – 25 ns tbtcpsu BSCAN test Capture register setup time 40 – ns tbtcph BSCAN test Capture register hold time 25 – ns tbtuco BSCAN test Update reg, falling edge of clock to valid output – 50 ns tbtuoz BSCAN test Update reg, falling edge of clock to output disable – 50 ns tbtuov BSCAN test Update reg, falling edge of clock to output enable – 50 ns trf U tbth SE tbtcp 3 Specifications ispLSI 1016EA Absolute Maximum Ratings 1 Supply Voltage VCC ................................ -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C N EW Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). pM 5V AC H D 4 ES A IG 5 F N O S R DC Recommended Operating Conditions PARAMETER SYMBOL VCC Supply Voltage MIN. MAX. UNITS 4.75 5.25 V 5V 4.75 5.25 V 3.3V 3.0 3.6 V 0.8 V Vcc+1 V Commercial TA = 0°C to + 70°C VCCIO Supply Voltage: Output Drivers VIL VIH Input Low Voltage 0 Input High Voltage 2.0 Table 2-0005/1016EA Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial) 8 pf VCC = 5.0V, VPIN = 2.0V C2 Y0 Clock Capacitance 10 pf VCC = 5.0V, VPIN = 2.0V SE is C1 Table 2-0006/1016EA Erase/Reprogram Specifications U PARAMETER Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 10000 — Cycles Table 2-0008/1016EA 4 Specifications ispLSI 1016EA Switching Test Conditions Input Pulse Levels Figure 3. Test Load GND to 3.0V Input Rise and Fall Time 10% to 90% 1.5ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 See Figure 3 Table 2-0003/1016EA 3-state levels are measured 0.5V from steady-state active level. Device Output CL 470Ω 390Ω 35pF B Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF C ∞ 390Ω 5pF 470Ω 390Ω 5pF Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V N EW R2 *CL includes Test Fixture and Probe Capacitance. 0213a pM 5V AC H D 4 ES A IG 5 F N O S R R1 A CL* R2 Output Load Conditions (see Figure 3) TEST CONDITION Test Point Table 2-0004/1016E DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL Output Low Voltage VOH Output High Voltage IIL Input or I/O Low Leakage Current IIH Input or I/O High Leakage Current IIL-PU IOS1 I/O Active Pull-Up Current TYP.3 — — 0.4 V IOH = -2 mA, VCCIO = 3.0V 2.4 — — V IOH = -4 mA, VCCIO = 4.75V IOL = 8 mA MAX. UNITS — — V — — -10 μA (VCCIO - 0.2)V ≤ VIN ≤ VCCIO — — 10 μA VCCIO ≤ VIN ≤ 5.25V — — 10 μA 0V ≤ VIN ≤ VIL — — -200 μA Output Short Circuit Current VCCIO = 5.0V or 3.3V, VOUT = 0.5V — — -240 mA Operating Power Supply Current VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz — 91 — mA SE is 2.4 0V ≤ VIN ≤ VIL (Max.) U ICC2, 4, 5 MIN. CONDITION PARAMETER Table 2-0007/1016EA 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum ICC. 5 Specifications ispLSI 1016EA External Timing Parameters Over Recommended Operating Conditions 4 DESCRIPTION A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass A 2 A 3 — 4 1 — 4.5 Data Propagation Delay, Worst Case Path — Clock Frequency with Internal Feedback 3 200 Clock Frequency with External Feedback ( tsu2 + tco1) 143 1 ( -100 -125 MIN. MAX. MIN. MAX. MIN. MAX. 1 twh + twl ) — 5 Clock Frequency, Max. Toggle — 6 GLB Reg. Setup Time before Clock,4 PT Bypass A 7 GLB Reg. Clock to Output Delay, ORP Bypass — — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 9 GLB Reg. Setup Time before Clock 3.5 — 10 GLB Reg. Clock to Output Delay — — 11 GLB Reg. Hold Time after Clock 0.0 A 12 Ext. Reset Pin to Output Delay — 250 3.0 UNITS ns — 10.0 10.0 — 12.5 ns — 100 — MHz 100 — 77 — MHz 167 — 125 — MHz — 7.5 6.0 — — 125 — — — 4.5 — 6.0 — ns 3.5 — 4.5 — 6.0 ns — 0.0 — 0.0 — ns — 5.5 — 7.0 — ns 4.0 — 5.5 — 7.0 ns — 0.0 — 0.0 — ns 5.5 — 10.0 — 13.5 ns — 13 Ext. Reset Pulse Duration 3.5 — 5.0 — 6.5 — ns B 14 Input to Output Enable — 7.0 — 12.0 — 15.0 ns C 15 Input to Output Disable — 7.0 — 12.0 — 15.0 ns B 16 Global OE Output Enable — 4.5 — 7.0 — 9.0 ns C 17 Global OE Output Disable — 4.5 — 7.0 — 9.0 ns — 18 External Synchronous Clock Pulse Duration, High 2.0 — 3.0 — 4.0 — ns — 19 External Synchronous Clock Pulse Duration, Low 2.0 — 3.0 — 4.0 — ns — 20 I/O Reg. Setup Time before Ext. Sync Clock (Y1) 3.0 — 3.0 — 3.5 — ns — 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y1) 0.0 — 0.0 — 0.0 — ns SE is Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. U 1. 2. 3. 4. #2 N EW tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 -200 TEST COND. pM 5V AC H D 4 ES A IG 5 F N O S R PARAMETER 6 Table 2-0030A/1016EA v.2.6 Specifications ispLSI 1016EA Internal Timing Parameters1 PARAM. # 2 -200 DESCRIPTION -125 -100 MIN. MAX. MIN. MAX. MIN. MAX. UNITS Inputs 22 I/O Register Bypass 23 I/O Latch Delay – 0.3 0.4 ns – 4.0 – 4.0 – 4.0 ns – 3.0 – 3.4 – ns 25 I/O Register Hold Time after Clock 0.0 – 0.0 – 0.0 – ns 26 I/O Register Clock to Out Delay – 4.0 – 4.6 – 5.0 ns 27 I/O Register Reset to Out Delay – 28 Dedicated Input Delay – 29 GRP Delay, 1 GLB Load – 1.3 – 1.7 – 2.1 ns 30 GRP Delay, 4 GLB Loads – 1.5 – 1.9 – 2.3 ns 31 GRP Delay, 8 GLB Loads – 1.7 – 2.1 – 2.5 ns 32 GRP Delay, 16 GLB Loads – 2.1 – 2.5 – 2.9 ns 33 4 ProductTerm Bypass Path Delay (Combinatorial) – 1.7 – 3.4 – 4.9 ns 34 4 Product Term Bypass Path Delay (Registered) – 1.8 – 3.1 – 4.9 ns 35 1 ProductTerm/XOR Path Delay – 1.9 – 3.6 – 4.3 ns 36 20 Product Term/XOR Path Delay – 1.9 – 3.6 – 4.3 ns 37 XOR Adjacent Path Delay 3 – 1.9 – 3.6 – 4.3 ns 38 GLB Register Bypass Delay – 0.6 – 1.2 – 2.1 ns 39 GLB Register Setup Time before Clock 0.2 – 0.3 – 1.4 – ns 40 GLB Register Hold Time after Clock 1.0 – 3.5 – 4.0 – ns 41 GLB Register Clock to Output Delay – 1.4 – 1.4 – 1.7 ns 42 GLB Register Reset to Output Delay – 3.8 – 4.9 – 5.0 ns 43 GLB Product Term Reset to Register Delay – 2.5 – 3.8 – 4.5 ns 44 GLB Product Term Output Enable to I/O Cell Delay – 2.1 – 5.7 – 7.2 ns 1.5 2.5 2.8 3.9 3.5 4.7 ns – 0.0 – 0.3 – 0.3 ns 47 ORP Delay – 0.8 – 1.3 – 1.4 ns 48 ORP Bypass Delay – 0.1 – 0.2 – 0.4 ns 4.0 – 4.6 – 5.0 ns 1.1 – 1.9 – 2.2 ns pM 5V AC H D 4 ES A IG 5 F N O S R is SE 45 GLB Product Term Clock Delay 46 GLB Feedback Delay U ORP torp torpbp – 3.0 GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck tgfb 0.3 24 I/O Register Setup Time before Clock GRP tgrp1 tgrp4 tgrp8 tgrp16 – N EW tiobp tiolat tiosu tioh tioco tior tdin 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036A/1016EA v.2.6 Specifications ispLSI 1016EA Internal Timing Parameters1 PARAM. # -200 DESCRIPTION -125 -100 MIN. MAX. MIN. MAX. MIN. MAX. UNITS Outputs 49 Output Buffer Delay — 0.9 — 1.7 — 2.0 50 Output Buffer Delay, Slew Limited Adder — 5.0 — 5.0 — 5.0 ns 51 I/O Cell OE to Output Enabled — 3.1 — 4.0 — 5.1 ns 52 I/O Cell OE to Output Disabled — 3.1 — 4.0 — 5.1 ns 53 Global OE — 1.4 — 3.0 — 3.9 ns Clocks tgr 1.1 1.1 1.9 1.9 ns 0.9 0.9 0.9 1.5 1.5 ns 1.8 0.8 1.8 0.8 1.8 ns 0.0 0.0 0.0 0.0 0.0 0.0 ns 0.8 2.8 0.8 2.8 0.8 2.8 ns — 0.0 — 2.1 — 5.1 ns 0.9 55 Clock Delay, Y1 to Global GLB Clock Line 0.9 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 57 Clock Delay, Y1 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset 59 Global Reset to GLB and I/O Registers U SE is 1. Internal Timing Parameters are not tested and are for reference only. 8 ns 0.9 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) pM 5V AC H D 4 ES A IG 5 F N O S R tgy0 tgy1 tgcp tioy1 tiocp N EW tob tsl toen todis tgoe Table 2-0037A/1016EA v.2.6 Specifications ispLSI 1016EA ispLSI 1016EA Timing Model I/O Cell GRP GLB #46 Ded. In I/O Pin (Input) #59 ORP Feedback #33 #28 Comb 4 PT Bypass GLB Reg Bypass ORP Bypass #22 #30 #34 #38 #48 Input D Register Q RST #23 - 27 GRP Loading Delay 20 PT XOR Delays GLB Reg Delay ORP Delay #29, 31 - 32 #35 - 37 I/O Reg Bypass GRP4 I/O Cell Reg 4 PT Bypass D Q #49, 50 #51, 52 #47 Clock Distribution Y1 Control RE PTs OE #43 - 45 CK pM 5V AC H D 4 ES A IG 5 F N O S R #55 - 58 #39 - 42 N EW RST #59 Reset #54 Y0 #53 GOE 0 Derivations of tsu, th and tco from the Product Term Clock 1 = = = 0.9 = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #36) + (#39) - (#22 + #30 + #45) (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.2) th = = = 1.6 = Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #45) + (#40) - (#22 + #30 + #36) (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9) tco = = = 7.2 = Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #45) + (#41) + (#47 + #49) (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9) is tsu SE Derivations of tsu, th and tco from the Clock GLB 1 tsu = = = 1.1 = th = = = 1.4 = Clock (max) + Reg (hold) - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #41 + #56) + (#40) - (#22 + #30 + #36) (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9) tco = = = 7.2 = Clock (max) + Reg (clock-to-out) + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #41 + #56) + (#41) + (#47 + #49) (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9) U Logic + Reg (setup) - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #36) + (#39) - (#54 + #41 + #56) (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8) 1. Calculations are based upon timing specifications for the ispLSI 1016EA-200. Table 2-0042a/1016EA v.2.6 9 0491/1016EA I/O Pin (Output) Specifications ispLSI 1016EA Maximum GRP Delay vs GLB Loads GRP Delay (ns) 4 3 ispLSI 1016EA-100 ispLSI 1016EA-125 1 1 4 8 16 GLB Load Power Consumption pM 5V AC H D 4 ES A IG 5 F N O S R GRP/GLB/1016EA N EW ispLSI 1016EA-200 2 used. Figure 4 shows the relationship between power and operating speed. Power consumption in the ispLSI 1016EA device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 150 ispLSI 1016EA 140 120 110 is ICC (mA) 130 U SE 100 90 80 0 50 100 150 200 250 fmax (MHz) Notes: Configuration of four 16-bit counters Typical current at 5V, 25°C ICC can be estimated for the ispLSI 1016EA using the following equation: ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004) Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/1016EA 10 Specifications ispLSI 1016EA Pin Description TQFP PIN NUMBERS PLCC PIN NUMBERS NAME 18, 22, 28, 32, 40, 44, 6, 10 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 15, 19, 25, 29, 37, 41, 3, 7, GOE 0/IN 31 2 40 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. TDI 14 8 Input - Functions as an input pin to load programming data into the device and also used as one of the two control pins for the ispJTAG state machine. TMS 36 30 Input - Controls the operation of the ISP state machine. TDO 24 18 Output - Functions as an output pin to read serial shift register data. TCK 33 Y0 11 Y1/RESET1 35 Input/Output Pins - These are the general purpose I/O pins used by the logic array. N EW 17, 21, 27, 31, 39, 43, 5, 9, 9, 13, 19, 23, 31, 35, 41, 1, I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 pM 5V AC H D 4 ES A IG 5 F N O S R 16, 20, 26, 30, 38, 42, 4, 8, DESCRIPTION 27 Input - Functions as a clock pin for the Serial Shift Register. 5 Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. 29 This pin performs two functions: Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. GND 1, VCC 12, 34 VCCIO 13 23 17, 39 Ground (GND) 6, VCC 7 28 Supply voltage for output drivers, 5V or 3.3V. U SE is 1. Pins have dual function capability which is software selectable. 11 Table 2-0002C/1016EA Specifications ispLSI 1016EA Pin Configurations I/O 20 I/O 19 I/O 21 I/O 22 I/O 23 GND GOE 0/IN 31 I/O 24 I/O 26 I/O 25 I/O 27 ispLSI 1016EA 44-Pin PLCC Pinout Diagram 6 5 4 3 2 1 44 43 42 41 40 7 39 I/O 18 I/O 29 8 38 I/O 17 I/O 30 9 37 I/O 16 I/O 31 10 11 36 TMS Y1/RESET1 VCC N EW I/O 28 12 ispLSI 1016EA 35 34 VCCIO 13 Top View 33 TCK TDI 14 32 I/O 15 I/O 0 15 31 I/O 14 pM 5V AC H D 4 ES A IG 5 F N O S R Y0 VCC I/O 1 I/O 2 16 17 30 29 I/O 13 I/O 12 I/O 11 I/O 10 I/O 9 I/O 8 TDO GND I/O 7 I/O 6 I/O 4 I/O 5 I/O 3 18 19 20 21 22 23 24 25 26 27 28 1. Pins have dual function capability which is software selectable. 0123A-isp1016EA is SE I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 GOE 0/IN 31 I/O 24 44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC 1 2 3 4 5 ispLSI 1016EA 6 Top View 33 I/O 18 32 31 I/O 17 I/O 16 30 TMS 29 28 Y1/RESET1 VCC VCCIO 7 27 TCK TDI 8 26 I/O 15 I/O 0 I/O 1 9 10 I/O 14 I/O 13 I/O 2 11 25 24 23 I/O 12 I/O 9 I/O 10 I/O 11 I/O 8 GND TDO I/O 7 I/O 6 I/O 4 I/O 5 12 13 14 15 16 17 18 19 20 21 22 I/O 3 U I/O 26 I/O 25 I/O 27 ispLSI 1016EA 44-Pin TQFP Pinout Diagram 1. Pins have dual function capability which is software selectable. 44 TQFP/1016EA 12 Specifications ispLSI 1016EA Part Number Description ispLSI 1016EA —XXX X XXX X Device Family Grade Blank = Commercial Device Number Package J44 = PLCC T44 = TQFP Speed 200 = 200 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax N EW Power L = Low 0212/1016EA pM 5V AC H D 4 ES A IG 5 F N O S R ispLSI 1016EA Ordering Information COMMERCIAL FAMILY fmax (MHz) 200 200 125 ispLSI 125 100 100 Revision History — April 2007 02.1 PACKAGE 4.5 ispLSI 1016EA-200LJ44 44-Pin PLCC 4.5 ispLSI 1016EA-200LT44 44-Pin TQFP 7.5 ispLSI 1016EA-125LJ44 44-Pin PLCC 7.5 ispLSI 1016EA-125LT44 44-Pin TQFP 10 ispLSI 1016EA-100LJ44 44-Pin PLCC 10 ispLSI 1016EA-100LT44 44-Pin TQFP Table 2-0041A/1016EA Change Summary Previous Lattice releases. is Version — ORDERING NUMBER Internal Timing Parameters table - Corrected value for tGSU in the -100 speed grade. U SE Date tpd (ns) 13