ISL59424, ISL59445 ® Data Sheet September 30, 2011 FN7456.3 1GHz Triple Multiplexing Amplifiers Features The ISL59424, ISL59445 are 1GHz bandwidth multiplexing amplifiers designed primarily for video input switching. These MUX-amps exhibit a fixed gain of 1 and also feature a high speed three-state to enable the output of multiple devices to be wired together. All logic inputs have pull-downs to ground and may be left floating. The EN pin, when pulled high, sets the ISL59424, ISL59445 in to low current mode-consuming just 15mW. An added feature in the ISL59424 is a latch enable function (LE) that allows independent logic control using a common logic bus. When LE is high the last logic state is preserved. • Triple 2:1 and 4:1 Multiplexers for RGB • Internally Set Gain-of-1 • High Speed Three-state Outputs (HIZ) • Power-down Mode (EN) • Latch Enable (ISL59424) • ±5V Operation • ±1200 V/µsec Slew Rate • 1GHz Bandwidth • Latched Select Pin (ISL59424) • Pb-Free (RoHS Compliant) TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59424 Applications S0 ENABLE HIZ LE OUTPUT 0 0 0 0 INO (A, B, C) • HDTV/DTV Analog Inputs 1 0 0 0 IN1 (A, B, C) • Video Projectors X 1 X X Power Down • Computer Monitors X 0 1 X High Z • Set-top Boxes X 0 0 1 Last S0 State Preserved • Security Video • Broadcast Video Equipment Ordering Information TABLE 2. CHANNEL SELECT LOGIC TABLE ISL59445 PART NUMBER (Notes 1, 2, 3) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # S1 S0 ENABLE HIZ OUTPUT 0 0 0 0 IN0 (A, B, C) ISL59424IRZ 59424 IRZ 24 Ld QFN MDP0046 0 1 0 0 IN1 (A, B, C) ISL59424IRZ-T13 59424 IRZ 24 Ld QFN MDP0046 1 0 0 0 IN2 (A, B, C) ISL59424IRZ-T7 59424 IRZ 24 Ld QFN MDP0046 1 1 0 0 IN3 (A, B, C) ISL59445IRZ 59445 IRZ 32 Ld QFN L32.5x6A X X 1 X Power Down ISL59445IRZ-T13 59445 IRZ 32 Ld QFN L32.5x6A X X 0 1 High Z ISL59445IRZ-T7 59445 IRZ 32 Ld QFN L32.5x6A ISL59445IRZ-EVAL Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL59424 and ISL59445. For more information on MSL please see techbrief TB363. 4. 32 LD QFN Exposed Pad Size 2.48 x 3.40mm. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL59424, ISL59445 Pinouts 26 HIZ 22 OUTA IN1C 5 15 V- 21 VA=1 THERMAL PAD GNDB 6 IN2A 7 13 S0 LE 12 NIC 8 A=1 18 S0 LATCHED ON HIGH LE IN3C 16 NIC 15 IN3B 14 17 S1 IN2C 10 IN2B 9 THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO V- 20 OUTB 19 OUTC NIC 13 A=1 NIC 11 IN1C 9 NIC 8 IN1B 7 NIC 10 THERMAL PAD 27 IN0C NIC 4 14 OUTC GNDC 6 23 V+ A=1 IN3A 12 A=1 IN1A 5 28 NIC IN1B 3 17 V+ 16 OUTB GNDB 4 24 NIC GNDC 11 A=1 29 IN0B NIC 2 18 OUTA IN0C 3 25 ENABLE IN1A 1 19 ENABLE NIC 2 31 IN0A 32 GNDA 20 HIZ 21 NIC 22 NIC 23 IN0A 24 GNDA IN0B 1 30 NIC ISL59445 (32-LD QFN) TOP VIEW ISL59424 (24-LD QFN) TOP VIEW THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO V- NIC = NO INTERNAL CONNECTION NIC = NO INTERNAL CONNECTION Functional Diagram ISL59424 Functional Diagram ISL59445 EN0 S0 EN0 DECODE EN1 DL Q C S0 IN0 (A, B, C) EN1 OUT DL Q IN1 (A, B, C) C S1 DECODE IN1 (A, B, C) EN2 AMPLIFIER BIAS EN3 LE HIZ IN0 (A, B, C) OUT IN2 (A, B, C) IN3 (A, B, C) AMPLIFIER BIAS HIZ ENABLE A LOGIC HIGH ON LE WILL LATCH THE LAST S0 STATE. THIS LOGIC STATE IS PRESERVED WHEN CYCLING HIZ OR ENABLE FUNCTIONS. 2 ENABLE FN7456.3 September 30, 2011 ISL59424, ISL59445 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-On Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital & Analog Input Current (Note 5) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance (Typical, Notes 6, 7) θJA (°C/W) θJC (°C/W) 24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 46 10 32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 46 10 Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, VIN = 1VP-P & RL = 500Ω to GND unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT No load, VIN = 0V, Enable Low, IS+ 35 39 43 mA No load, VIN = 0V, Enable Low, IS- -40 -36 -32 mA GENERAL IS Enabled Enabled Supply Current (ISL59424) No load, VIN = 0V, Enable Low, IS+ 47 53 60 mA No load, VIN = 0V, Enable Low, IS- -57 -50 -44 mA Enable High, IS+ 2 3 4 mA Enable High, IS- -50 0 - µA Input Bias Current VIN = 0 -3.4 -2.2 -1.4 µA Bias current into output, HIZ mode ISL59424 - VOUT = +5V 8 15 22 µA ISL59445 - VOUT = 0V -35 0 35 µA - V Enabled Supply Current (ISL59445) +IS Disabled Ib ITRI Disabled Supply Current VOUT Positive and Negative Output Swing VIN = ±3.5V ±3.2 ±3.4 IOUT Output Current RL = 10Ω to GND ±80 ±130 - mA VOS Offset Voltage -13 3 13 mV ROUT HIZ Output Resistance HIZ = Logic High - 1.0 - MΩ ROUT Enabled Output Resistance HIZ = Logic Low - 0.2 - Ω Input Resistance VIN = ±3.5V - 10 - MΩ Voltage Gain VIN = ±1.5V 0.98 0.99 1.0 V/V 2 - - V RIN ACL or AV LOGIC VIH Input High Voltage (Logic Inputs) VIL Input Low Voltage (Logic Inputs) - - 0.8 V IIH Input High Current (Logic Inputs) VH = 5V 235 270 320 µA IIL Input Low Current (Logic Inputs) VL = 0V - 1 3 µA Power Supply Rejection Ratio (ISL59424) DC, PSRR V+ and V- combined 60 73 - dB Power Supply Rejection Ratio (ISL59445) DC, PSRR V+ and V- combined 50 57 - dB AC GENERAL PSRR 3 FN7456.3 September 30, 2011 ISL59424, ISL59445 Electrical Specifications PARAMETER ISO V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, VIN = 1VP-P & RL = 500Ω to GND unless otherwise specified. DESCRIPTION Channel Isolation (ISL59424) CONDITIONS f = 10MHz, CL = 0.5pF, VIN = -6dBm Channel Isolation (ISL59445) Xtalk Channel Cross Talk (ISL59424) f = 10MHz, CL = 0.5pF, VIN = -6dBm Channel Cross Talk (ISL59445) dG Differential Gain Error NTC-7, RL = 150, CL = 0.5pF MIN TYP MAX UNIT - 80 - dB - 75 - dB - 75 - dB - 70 - - - 0.02 - % dP Differential Phase Error NTC-7, RL = 150, CL = 0.5pF - 0.02 - ° BW -3dB Bandwidth CL = 0.5pF - 1000 - MHz FBW 0.1dB Bandwidth CL = 0.5pF - 130 - MHz 0.1dB Bandwidth CL = 1.5pF - 200 - MHz Slew Rate 25% to 75%, RL = 150Ω, Input Enabled, CL= 1.5pF, VIN = ±1V - ±1200 - V/µs Channel-to-Channel Switching Glitch VIN = 0V, CL = 0.5pF - 40 - mVP-P Enable Switching Glitch VIN = 0V, CL = 0.5pF - 300 - mVP-P HIZ Switching Glitch VIN = 0V, CL = 0.5pF - 200 - mVP-P Channel-to-Channel Switching Glitch VIN = 0V, CL = 0.5pF - 20 - mVP-P Enable Switching Glitch VIN = 0V, CL = 0.5pF - 200 - mVP-P HIZ Switching Glitch VIN = 0V, CL = 0.5pF - 200 - mVP-P tSW-L-H Channel Switching Time Low-to-High 1.2V logic threshold to 10% movement of analog output - 15 - ns tSW-H-L Channel Switching Time High-to-Low 1.2V logic threshold to 10% movement of analog output - 15 - ns tr Rise Time 10% to 90% - 600 - ps tf Fall Time 10% to 10% - 800 - ps tpd Propagation Delay 10% to 10% - 600 - ps tS 0.1% Settling Time Step = 1V - 6 - ns tLH Latch Enable HoldTime LE = 0V - 10 - ns SWITCHING CHARACTERISTICS SR VGLITCH ISL58424 VGLITCH ISL59445 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. 10 SOURCE POWER = -12dBm 8 3 CL = 3.8pF 4 CL = 2.7pF CL = 1.5pF 0 -2 CL = 0.5pF -4 -6 CL INCLUDES 0.5pF BOARD CAPACITANCE -8 -10 1 10 100 SOURCE POWER = -12dBm 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 6 2 5 CL = 8.7pF CL = 5.2pF 1k 1.2k RL = 1kΩ 2 RL = 500Ω 1 0 -1 -2 RL = 150Ω -3 RL = 100Ω -4 -5 1 10 100 1k 1.2k FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 1. GAIN vs FREQUENCY vs CL FIGURE 2. GAIN vs FREQUENCY vs RL 4 FN7456.3 September 30, 2011 ISL59424, ISL59445 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. 0.2 100 SOURCE 0.1 POWER = -12dBm SOURCE POWER = -12dBm CL = 2.0pF 0 -0.1 -0.2 CL = 0.5pF -0.3 CL = 1.5pF -0.4 -0.5 -0.6 OUTPUT RESISTANCE (Ω) NORMALIZED GAIN (dB) (Continued) ISL59424 10 ISL59445 1 -0.7 -0.8 1 10 100 0.1 0.1 1k 1.2k 1 FIGURE 3. 0.1dB GAIN vs FREQUENCY RL = 500Ω CL = 1.5pF 0.6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1k 0.8 RL = 500Ω CL = 1.5pF 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 TIME (5ns/DIV) TIME (5ns/DIV) FIGURE 5. ISL59424 TRANSIENT RESPONSE FIGURE 6. ISL59445 TRANSIENT RESPONSE 0 0 -10 -10 INPUT X TO OUTPUT Y CROSSTALK -20 -30 -30 -40 -40 OFF-ISOLATION INPUT X TO OUTPUT X -50 INPUT X TO OUTPUT Y CROSSTALK -20 (dB) (dB) 100 FIGURE 4. ROUT vs FREQUENCY 0.8 -60 OFF-ISOLATION INPUT X TO OUTPUT X -50 -60 -70 -70 -80 -80 -90 -90 -100 0.1 10 FREQUENCY (MHz) FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) FIGURE 7. ISL59424 CROSSTALK AND OFF-ISOLATION 5 1k -100 0.1 1 10 100 1k FREQUENCY (MHz) FIGURE 8. ISL59445 CROSSTALK AND OFF-ISOLATION FN7456.3 September 30, 2011 ISL59424, ISL59445 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. 20 20 10 10 PSRR (V+) PSRR (V+) 0 -10 -10 -20 -20 PSRR (dB) PSRR (dB) 0 -30 PSRR (V-) -40 -50 -60 PSRR (V-) -30 -40 -50 -60 -70 -70 -80 0.3 -80 0.3 1 10 100 1k 10 100 1k FREQUENCY (MHz) FIGURE 9. ISL59424 PSRR CHANNELS A, B, C FIGURE 10. ISL59445 PSRR CHANNELS A, B, C S0, S1 50Ω TERM. VIN = 0V 0 0.5V/DIV 0 VOUT A, B, C 0 VOUT A, B, C 10ns/DIV 10ns/DIV FIGURE 11. CHANNEL-TO-CHANNEL SWITCHING GLITCH VIN = 0V ENABLE 50Ω TERM. FIGURE 12. CHANNEL-TO-CHANNEL TRANSIENT RESPONSE VIN = 1V ENABLE VIN = 0V VIN = 1V 50Ω TERM. 1V/DIV 1V/DIV VIN = 1V S0, S1 50Ω TERM. 1V/DIV 1V/DIV 20mV/DIV 1 FREQUENCY (MHz) 0 0 1V/DIV 0 100mV/DIV (Continued) VOUT A, B, C 0 20ns/DIV FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V 6 0 VOUT A, B, C 20ns/DIV FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V FN7456.3 September 30, 2011 ISL59424, ISL59445 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. HIZ 0 1V/DIV 200mv/DIV 0 VIN = 1V 50Ω TERM. 1V/DIV 1V/DIV HIZ VIN = 0V 50Ω TERM. (Continued) 0 VOUT A, B, C VOUT A, B, C 0 10ns/DIV 10ns/DIV FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V VOLTAGE NOISE (nV√Hz) 60 50 40 30 20 10 0 100 1k 10k 100k FREQUENCY (Hz) FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C) 7 FN7456.3 September 30, 2011 ISL59424, ISL59445 Pin Descriptions ISL59445 (32-LD QFN) ISL59424 (24-LD QFN) PIN NAME EQUIVALENT CIRCUIT 1 5 IN1A Circuit 1 2, 4, 8, 13, 15, 24, 28, 30 2, 8, 10, 11, 21, 22 NIC - 3 7 IN1B Circuit 1 Channel 1 input for output amplifier "B" 5 9 IN1C Circuit 1 Channel 1 input for output amplifier "C" 6 4 GNDB Circuit 4 Ground pin for output amplifier “B” IN2A Circuit 1 Channel 2 input for output amplifier "A" 7 DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. 9 IN2B Circuit 1 Channel 2 input for output amplifier "B" 10 IN2C Circuit 1 Channel 2 input for output amplifier "C" GNDC Circuit 4 Ground pin for output amplifier “C” IN3A Circuit 1 Channel 3 input for output amplifier "A" 11 6 12 14 IN3B Circuit 1 Channel 3 input for output amplifier "B" 16 IN3C Circuit 1 Channel 3 input for output amplifier "C" 17 S1 Circuit 2 Channel selection pin MSB (binary logic code) 13 S0 Circuit 2 Channel selection pin. LSB (binary logic code) 19 14 OUTC Circuit 3 Output of amplifier “C” 20 16 OUTB Circuit 3 Output of amplifier “B” 21 15 V- Circuit 4 Negative power supply 22 18 OUTA Circuit 3 Output of amplifier “A” 23 17 V+ Circuit 4 Positive power supply 25 19 ENABLE Circuit 2 Device enable (active low). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic High on this pin puts device into power-down mode. In power-down mode only logic circuitry is active. All logic states are preserved post power-down. This state is not recommended for logic control where more than one MUX-amp share the same video output line. 12 LE Circuit 2 Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic state. HIZ and ENABLE functions are not latched with the LE pin. 26 20 HIZ Circuit 2 Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. 27 3 IN0C Circuit 1 Channel 0 for output amplifier "C" 29 1 IN0B Circuit 1 Channel 0 for output amplifier "B" 31 23 IN0A Circuit 1 Channel 0 for output amplifier "A" 32 24 GNDA Circuit 4 Ground pin for output amplifier “A” 18 V+ IN LOGIC PIN VCIRCUIT 1 21k + 1.2V 33k CIRCUIT 2 V+ V+ GND OUT V- VCIRCUIT 3 THERMAL HEAT SINK PAD V+ GNDA GND GNDC CAPACITIVELY COUPLED ESD CLAMP ~1MΩ VSUBSTRATE V. CIRCUIT 4 8 FN7456.3 September 30, 2011 ISL59424, ISL59445 AC Test Circuits VIN VIN 50Ω OR 75Ω TEST EQUIPMENT ISL59424, ISL59445 RS ISL59424, ISL59445 CL 1.5pF 50Ω OR 75Ω RL 500Ω FIGURE 18A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD 50Ω OR 75Ω 475Ω OR 462.5Ω 50Ω OR 75Ω 50Ω OR 75Ω FIGURE 18B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR 75Ω INPUT TERMINATED EQUIPMENT TEST EQUIPMENT ISL59424, ISL59445 RS VIN CL 1.5pF 50Ω OR 75Ω CL 1.5pF 50Ω OR 75Ω FIGURE 18C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED. FIGURE 18. TEST CIRCUITS Figure 18A illustrates the optimum output load for testing AC performance. Figure 18B illustrates the optimum output load when connecting to 50Ω input terminated equipment. Application Information General The ISL59424, ISL59445 are triple 2:1 and 4:1 muxes that are ideal for the matrix element of high performance switchers and routers. The ISL59424, ISL59445 are optimized to drive a 1.5pF in parallel with a 500Ω load. The capacitance can be split between the PCB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 50Ω or 75Ω terminations. Ground Connections For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane. Control Signals S0, S1, ENABLE, LE, HIZ - These pins are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select which one of the inputs connect to the output. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE, LE, HIZ pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. For control signal rise and fall times less than 10ns the use of termination resistors close to the part should be considered to minimize transients coupled to the output. 9 Power-Up Considerations The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the “Pin Descriptions” on page 8. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 19) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. FN7456.3 September 30, 2011 ISL59424, ISL59445 V+ SUPPLY SCHOTTKY PROTECTION LOGIC V+ LOGIC CONTROL S0 POWER GND GND SIGNAL EXTERNAL CIRCUITS V+ V- IN0 V+ V+ OUT V+ V- DE-COUPLING CAPS IN1 VV- V- V- SUPPLY FIGURE 19. SCHOTTKY PROTECTION CIRCUIT HIZ State An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 15ns (Figure 16) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4MΩ with approximately 1.5pF in parallel with a 10µA bias current from the output. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state. ENABLE and Power Down States The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power Down state is established within approximately 100ns (Figure 14), if a logic high (>2V) is placed on the ENABLE pin. In the Power Down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Do not use this state as a logic control for applications driving more than one mux on a common output. LE State The ISL59424 is equipped with a Latch Enable pin. A logic high (>2V) on the LE pin latches the last logic state. This logic state is preserved when cycling HIZ or ENABLE functions. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. Application Example Figure 19 illustrates the use of the ISL59445, two ISL84517 SPST switches and one NC7ST00P5X NAND gate to mux 3 different component video signals and one RGB video signal. The SPDT switches provide the sync signal for the 10 RGB video and disconnects the sync signal for the component signal. PC Board Layout The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. • Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible - Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. FN7456.3 September 30, 2011 ISL59424, ISL59445 • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. Maximum AC performance is achieved if the thermal pad is attached to a dedicated de-coupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1” x 1” pad area is sufficient for the ISL59445 that is dissipating 0.5W in +50°C ambient. Pad area requirements should be evaluated on a case by case basis. The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND. Connecting this pin to GND could result in large back biased currents flowing between GND and V-. The ISL59445 uses the package with pad dimensions of D2 = 2.48mm and E2 = 3.4mm. 11 FN7456.3 September 30, 2011 5V 0.1µF OPTIONAL SCHOTTKY PROTECTION Y1 Y2 31 1 Y3 7 R 12 INOA IN1A V+ ISL59445IL 23 0.1µF -5V 1nF 1nF 21 VOUTA 22 IN2A IN3A OUTB 20 12 Pb1 29 Pb2 3 OUTC 19 INOB IN1B 9 IN2B 14 IN3B Pb3 G Pr1 27 Pr2 5 Pr3 10 16 B R3 75Ω R2 75Ω R5 75Ω R4 75Ω R7 75Ω R9 75Ω R6 75Ω H SYNC 1 5V 0.1µF 0.1µF -5V ISL84517IH-T 5 V+ COM V- 3 SOT-23 IN 4 V SYNC ISL84517IH-T 5 V+ 1 COM V- 3 SOT-23 IN 4 NC 1nF 1nF 0.1µF 0.1µF 1nF 1nF 11 NIC NIC 4 8 NIC 13 NIC 15 NIC 24 NIC 28 NIC 30 HIZ 26 ENABLE 25 S0 18 S1 17 IN1C IN2C IN3C QFN 5V GNDC 2 INOC R12 75Ω 6 NIC R11 75Ω R10 75Ω R8 75Ω 32 GNDB R16 500Ω -5V NC 2 5V 0.1µF NC7ST00P5X 5V 5 2 1nF INPUT 1 FN7456.3 September 30, 2011 4 OUT 3 GND INPUT 2 SC70 LOGIC INPUTS FIGURE 20. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL R18 500Ω R17 500Ω ISL59424, ISL59445 R1 75Ω GNDA ISL59424, ISL59445 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN38 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN24 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 13 FN7456.3 September 30, 2011 ISL59424, ISL59445 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L32.5x6A (One of 10 Packages in MDP0046) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D B N (N-1) (N-2) 1 2 3 SYMBOL PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 0.00 0.02 0.05 - D 5.00 BSC - D2 2.48 REF - E 6.00 BSC - E2 3.40 REF - L 0.45 0.50 0.55 - b 0.17 0.22 0.27 - c 0.20 REF - e 0.50 BSC - N 32 REF 4 ND 7 REF 6 NE 9 REF 5 0.10 M C A B b Rev 1 2/09 NOTES: (N-2) (N-1) N N LEADS TOP VIEW MIN L 1. Dimensioning and tolerancing per ASME Y14.5M-1994. PIN #1 I.D. 2. Tiebar view shown is a non-functional feature. 3 1 2 3 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the “E” side of the package (or Y-direction). (E2) 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. NE 5 (N/2) 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 7 (D2) BOTTOM VIEW 0.10 C e C (c) SEATING PLANE 0.08 C N LEADS & EXPOSED PAD C 2 A (L) SEE DETAIL "X" A1 SIDE VIEW N LEADS DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7456.3 September 30, 2011