[AK4687] AK4687 Asynchronous Stereo CODEC with Capless Stereo Selector GENERAL DESCRIPTION The AK4687 is a stereo audio CODEC with 2-channel input selector and a line driver. The interfaces of ADC/DAC can accept up to 24bit input data and support asynchronous operation. The input range of the pre-amplifier, that supports 3ch stereo inputs, is selectable by external resistors. Both the input stereo selector and output drivers support ground reference 2Vrms In/Output, making it possible to remove AC-coupling capacitors and reducing external parts. The AK4687 has a dynamic range of 99dB for ADC, 105dB for DAC. It is well suitable for digital recording systems, digital TVs, Blu-ray recorders and Home theater systems. FEATURES Asynchronous ADC/DAC Operation 3:1 Capless Stereo Line Input Selector 24bit Stereo ADC - 64x Oversampling - Sampling Rate up to 48kHz - Linear Phase Digital Anti-Alias Filter - S/(N+D): 83dB - Dynamic Range, S/N: 99dB - Digital HPF for Offset Cancellation 24bit Two Stereo DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - S/(N+D): 95dB - Dynamic Range, S/N: 105dB - De-emphasis Filter High Jitter Tolerance External Master Clock Input: 256fs, 384fs, 512fs 768fs (fs=32kHz ∼ 48kHz) 128fs, 192fs, 256fs 384fs (fs=64kHz ∼ 96kHz) 128fs, 192fs (fs=128kHz ~ 192kHz) 2 Audio Serial I/F (PORT1, PORT2) - Master/Slave mode (PORT1) - I/F format PORT2: MSB, LSB justified (16/24 bit), I2S PORT1: MSB, LSB justified (16/24 bit), I2S Hardware / I2C-bus Control Operating Voltage: - Digital I/O and Charge Pump: 3.0V ∼ 3.6V - ADC Analog: 3.0V ∼ 3.6V - DAC Analog: 3.0V ∼ 3.6V Package: 48pinLQFP MS1307-E-00 2011/05 -1- [AK4687] 2Vrms +/-50mVDC input PORT1 PWAD bit PDN1 pin LO LI PDN1 LIN1 LIN2 LIN3 2ch ADC RIN1 RIN2 RIN3 HPF Serial I/F MCLK1 BICK1 LRCK1 SDTO MSN RI RO CVEE CP CN Charge Pump Control PWAD/PWDA bit PDN1/PDN2 pin I/F PWDA bit PDN2 pin I2C SDA/AIN1 SCL/AIN0 PORT2 2Vrms LOUT 2ch DAC De-em Serial I/F MCLK2 BICK2 LRCK2 SDTI ROUT PDN2 CAD0/CKS AVDD1 VSS1 AVDD2 VSS2 DVDD VSS3 VSS4 VSS5 VREF1 VREF2 AK4687 Block Diagram MS1307-E-00 2011/05 -2- [AK4687] ■ Ordering Guide AK4687EQ AKD4687 -20 ∼ +85°C 48pin LQFP (0.5mm pitch) Evaluation Board for the AK4687 LI LO RO RI VREF1 AVDD1 VSS1 VSS4 VSS5 VSS2 AVDD2 VREF2 36 35 34 33 32 31 30 29 28 27 26 25 ■ Pin Layout RIN3 37 24 LOUT LIN3 38 23 ROUT NC 39 22 NC RIN2 40 21 CVEE LIN2 41 20 CN NC 42 19 CP RIN1 43 18 VSS3 17 DVDD AK4687EQ Top View 9 10 11 12 LRCK2 SDTI CAD0/CKS TEST1 BICK2 13 8 48 MCLK2 SCL/AIN0 7 TEST2 PDN2 14 6 47 PDN1 SDA/AIN1 5 NC MCLK1 15 4 46 BICK1 I2C 3 NC LRCK1 16 2 45 SDTO NC 1 44 MSN LIN1 MS1307-E-00 2011/05 -3- [AK4687] PIN/FUNCTION No. Pin Name 1 MSN 2 3 4 5 6 SDTO LRCK1 BICK1 MCLK1 I/O I O I/O I/O I PDN1 I PDN2 I MCLK2 BICK2 LRCK2 SDTI CAD0 I I I I I CKS I 13 14 15 16 17 18 19 20 21 22 23 24 TEST1 TEST2 NC NC DVDD VSS3 CP CN CVEE NC ROUT LOUT I I I I O O O 25 VREF2 O 26 27 28 29 30 31 AVDD2 VSS2 VSS5 VSS4 VSS1 AVDD1 - 32 VREF1 O 33 34 35 36 37 38 39 40 41 42 43 44 45 RI RO LO LI RIN3 LIN3 NC RIN2 LIN2 NC RIN1 LIN1 NC O O O O I I I I I I - 7 8 9 10 11 12 Function PORT1 Master Mode Select Pin. “L”(connected to the ground): Slave mode. “H”(connected to DVDD) : Master mode. Audio Serial Data Output Pin (for PORT1) Channel Clock Pin (for PORT1) Audio Serial Data Clock Pin (for PORT1) ADC Master Clock Input Pin (for PORT1) Power-Down Mode for ADC When “L”, the ADC is powered-down. Power-Down Mode for DAC When “L”, the DAC is powered-down. DAC Master Clock Input Pin (for PORT2) Audio Serial Data Clock Pin (for PORT2) Input Channel Clock Pin (for PORT2) Audio Serial Data Input Pin (for PORT2) CAD Address Pin (I2C pin = “H”) ADC MCLK Speed Select Pin (I2C pin = “L”) “H”: MCLK=768fs , “L”: MCLK=256fs This pin must be connected to the ground This pin must be connected to the ground This pin must be connected to the ground This pin must be connected to the ground Digital Power Supply Pin, 3.0V∼3.6V Digital Ground Pin, 0V Positive Charge Pump Capacitor Terminal Pin (for Analog Input/Output) Negative Charge Pump Capacitor Terminal Pin (for Analog Input/Output) Charge Pump Circuit Negative Voltage Output Pin (for Analog Input/Output) This pin must be connected to the ground Rch Analog Output Pin Lch Analog Output Pin Reference Output Pin Connect to VSS2 with a 1µF low ESR capacitor over all temperatures. DAC Analog Power Supply Pin, 3.3V∼3.6V DAC Analog Ground Pin, 0V DAC Analog Ground Pin, 0V ADC Analog Ground Pin, 0V ADC Analog Ground Pin, 0V ADC Analog Power Supply Pin, 3.0V∼3.6V Reference Output Pin Connect to VSS1 with a 1µF low ESR capacitor over all temperatures. Rch Feedback Resistor Input Pin Rch Feedback Resistor Output Pin Lch Feedback Resistor Output Pin Lch Feedback Resistor Input Pin Rch Input 3 Pin Lch Input 3 Pin This pin must be connected to the ground Rch Input 2 Pin Lch Input 2 Pin This pin must be connected to the ground Rch Input 1 Pin Lch Input 1 Pin This pin must be connected to the ground MS1307-E-00 2011/05 -4- [AK4687] PIN/FUNCTION (Continued) No. Pin Name I/O Function I2C Pin 46 I2C I “H”= I2C control, “L”= H/W control SDA I/O Control Data Pin (I2C pin = “H”) 47 AIN1 I Analog Input Select Pin (I2C pin = “L”) SCL I Control Data Clock Pin (I2C pin = “H”) 48 AIN0 I Analog Input Select Pin (I2C pin = “L”) Note: All digital input pins must not be left floating. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4 =VSS5=0V; Note 1) Parameter Symbol min max Power Supply DVDD -0.3 4.0 AVDD1 -0.3 4.0 AVDD2 -0.3 4.0 Input Current (any pins except for supplies) IIN ±10 Digital Input Voltage VIND -0.3 DVDD+0.3 (MCLK1-2, PDN1-2, LRCK1-2, SDTI, BICK1-2, SDA, SCL, MSN, CAD0 pins) Analog Input Voltage VINA -0.3 AVDD1+0.3 (LIN1-3, RIN1-3 pins) Ambient Operating Temperature Ta -20 85 Storage Temperature Tstg -65 150 Note 1. VSS1, VSS2, VSS3, VSS4 and VSS5 must be connected to the same analog ground plane. Units V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=VSS5= 0V; Note 1) Parameter Symbol min typ max Units Power Supply (Note 2) DVDD 3.0 3.3 3.6 V AVDD1 3.0 3.3 3.6 V AVDD2 3.0 3.3 3.6 V Note 2. The AVDD1, AVDD2 and CVDD must be the same voltage. The voltage difference between DVDD and other voltages (AVDD1, AVDD2 and CVDD) must be less than 0.3V. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1307-E-00 2011/05 -5- [AK4687] ANALOG CHARACTERISTICS (Ta=25°C; AVDD1=AVDD2 = DVDD= 3.3V; VSS1=VSS2=VSS3 =VSS4 =VSS5 =0V; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency = 20Hz∼ 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified) Parameter min typ max Units Pre-Amp Characteristics: Feedback Resistance Rf 12 39 92 kΩ Input Resistance Ri 18 47 92 kΩ Output Level LO / RO pins (ADC=0dBFs) (Note 3) 1.82 1.91 2.00 Vrms Load Resistance RL (Note 4) 18 kΩ Load Capacitance CL (Note 4) 20 pF Analog Input (LIN1-3, RIN1-3pin) to ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-1dBFS) fs=48kHz 83 dB DR (-60dBFS) fs=48kHz, A-weighted 99 dB S/N (input off) fs=48kHz, A-weighted 99 dB Interchannel Isolation (Note 5) 100 dB Interchannel Gain Mismatch 0 dB Gain Drift 50 ppm/°C Power Supply Rejection (Note 6) 50 dB DAC to Analog Output (LOUT, ROUT pin) Characteristics Resolution 24 Bits S/(N+D) (0dBFS) fs=48kHz 95 dB fs=96kHz 93 dB fs=192kHz 93 dB DR (-60dBFS) fs=48kHz, A-weighted 105 dB fs=96kHz, A-weighted 105 dB fs=192kHz, A-weighted 105 dB S/N (“0” data) fs=48kHz, A-weighted 105 dB fs=96kHz, A-weighted 105 dB fs=192kHz, A-weighted 105 dB Interchannel Isolation 100 dB Interchannel Gain Mismatch 0 dB DC Offset (at output pin) –5 0 +5 mV Gain Drift 50 ppm/°C Output Voltage LOUT/ROUT= 2 x AVDD2/3.3 1.85 2 2.15 Vrms Load Resistance 5 kΩ Load Capacitance (C1) 30 pF Power Supply Rejection (Note 6) 62 dB Note 3. Input range for ADC full scale when the external input resistance is 47kΩ, feedback resistance is 39kΩ and input signal is 2.3Vrms. Note 4. RL or CL of Figure 2. Load resistance and capacitance when the output signal of the LO/RO pin is used for an external device. Note 5. This value is the channel isolation for all other channels between LIN1-3 and RIN1-3. Note 6. PSR is applied to AVDD1, AVDD2 and DVDD with 1kHz, 50mVpp. MS1307-E-00 2011/05 -6- [AK4687] LOUT/ROUT 470 AK4687 C1 Analog Out 2.2nF Figure 1. Lineout Circuit Example RL CL Rf LI 0V LO R i LIN1 R i LIN2 R i LIN3 - ADC + 0V AK4687 Figure 2. External Circuit of Pre-Amp MS1307-E-00 2011/05 -7- [AK4687] Power Supplies Parameter min typ max Units Power Supply Current Normal Operation (PDN1 pin = PDN2 pin = “H”) AVVD1 3 mA AVDD2 11 mA DVDD 13 mA DVDD+AVDD1+AVDD2 27 40 mA Power-Down Mode (PDN1 pin = PDN2 pin = “L”; Note 7) DVDD+AVDD1+AVDD2 1 20 μA Note 7. PDN1-2 and TEST1-2 pins are held at VSS3, and all digital inputs including clock pins (MCLK1-2, BICK1-2, LRCK1-2, SDTI, SDA, SCL, MSN and CAD0 pins) are held at DVDD or VSS3. However, the LRCK and BICK pins should be open since these pins become output state when the MSN pin is fixed to DVDD. FILTER CHARACTERISTICS (Ta=25°C; AVDD1=AVDD2= DVDD= 3.3V; fs=48kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 8) PB 0 18.8 kHz ±0.1dB 21.1 kHz -0.2dB 21.7 kHz -3.0dB Stopband SB 28.5 kHz Stopband Attenuation SA 73 dB Group Delay (Note 10) GD 17 1/fs Group Delay Distortion 0 µs ΔGD ADC Digital Filter (HPF): Frequency Response (Note 8) -3dB FR 1.0 Hz -0.1dB 7.1 Hz DAC Digital Filter: PB 0 21.7 kHz Passband ±0.05dB (Note 9) 24.0 kHz -6.0dB Stopband (Note 9) SB 26.3 kHz Passband Ripple PR dB ± 0.05 Stopband Attenuation SA 64 dB Group Delay (Note 10) GD 24 1/fs De-emphasis Filter (DEM = ON) De-emphasis Error fs = 32kHz –1.5/0 dB (DC Reference) fs = 44.1kHz –0.2/+0.2 dB fs = 48kHz 0/+0.6 dB DAC Digital Filter + Analog Filter: (DEM = OFF) Frequency Response 20.0kHz fs=44.1kHz FR dB ± 0.2 40.0kHz fs=96kHz FR dB ± 0.3 80.0kHz fs=192kHz FR dB ± 1.0 Note 8. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz. Note 9. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535×fs(@±0.05dB), SB=0.546×fs. Note 10. The calculating delay time occurred at digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register of PORT1. For DAC, this time is from setting the 20/24bit data of both channels on input register of PORT2 to the output of analog signal. MS1307-E-00 2011/05 -8- [AK4687] DC CHARACTERISTICS (Ta= 25°C; AVDD1=AVDD2= DVDD= 3.3V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400μA) VOH DVDD-0.4 Low-Level Output Voltage VOL (Iout= -400μA(except SDA pin), 3mA(SDA pin)) Iin Input Leakage Current - typ - max 30%DVDD 0.4 Units V V V V - ±10 μA SWITCHING CHARACTERISTICS (Ta=25°C; AVDD1=AVDD2=CVDD = DVDD= 3.3V; CL= 20pF (except for SDA pin), Cb=400pF(SDA pin)) Parameter Symbol min typ max Units Master Clock Timing Frequency fECLK 8.192 36.864 MHz Duty dECLK 40 50 60 % Master Clock 256fsn, 128fsd: fCLK 8.192 12.288 MHz Pulse Width Low tCLKL 0.37 1/fCLK Pulse Width High tCLKH 0.37 1/fCLK 384fsn, 192fsd: fCLK 12.288 18.432 MHz Pulse Width Low tCLKL 0.37 1/fCLK Pulse Width High tCLKH 0.37 1/fCLK 512fsn, 256fsd, 128fsq: fCLK 16.384 24.576 MHz Pulse Width Low tCLKL 0.37 1/fCLK Pulse Width High tCLKH 0.37 1/fCLK 768fsn, 384fsd, 192fsq: fCLK 24.576 36.864 MHz Pulse Width Low tCLKL 0.37 1/fCLK Pulse Width High tCLKH 0.37 1/fCLK LRCK1Timing (Slave Mode) fsn 32 48 kHz Duty Cycle Duty 45 55 % LRCK2Timing (Slave Mode) Normal Speed Mode fsn 32 48 kHz Double Speed Mode fsd 32 96 kHz Quad Speed Mode fsq 128 192 kHz Duty Cycle Duty 45 55 % LRCK1 Timing (Master Mode) Normal Speed Mode fsn 32 48 kHz Duty Cycle Duty 50 % Power-down & Reset Timing PDN Pulse Width (Note 11) tPD 150 ns PDN “↑” to SDTO valid (Note 12) tPDV 2640 1/fs Note 11. Refer to the “■ System Reset” paragraph for the reset by PDN1 and PDN2 pins. Note 12. After a rising edge of PDN1, the internal counter starts by divided clock of MCLK and ADC power down is released by a falling edge of CVEE after 64/fs on LRCK, then SDTIO is output 528/fs later. MS1307-E-00 2011/05 -9- [AK4687] Parameter Symbol min Audio Interface Timing (Slave Mode) PORT2(DAC) BICK2 Period tBCK 81 BICK2 Pulse Width Low tBCKL 20 Pulse Width High tBCKH 20 LRCK2 Edge to BICK2 “↑” (Note 13) tLRB 20 BICK2 “↑” to LRCK2 Edge (Note 13) tBLR 20 SDTI Hold Time tSDH 10 SDTI Setup Time tSDS 10 PORT1 (ADC) BICK1 Period tBCK 324 BICK1 Pulse Width Low tBCKL 128 Pulse Width High tBCKH 128 LRCK1 Edge to BICK1 “↑” (Note 13) tLRB 80 BICK1 “↑” to LRCK1 Edge (Note 13) tBLR 80 LRCK1 to SDTO (MSB) tLRS BICK1 “↓” to SDTO tBSD Audio Interface Timing (Master Mode) BICK1 Frequency fBCK BICK1 Duty dBCK BICK1 “↓” to LRCK1 Edge tMBLR -20 BICK1 “↓” to SDTO tBSD Control Interface Timing (I2C Bus): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first clock pulse) Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 14) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP Capacitive load on bus Cb 0 Note 13. BICK rising edge must not occur at the same time as LRCK edge. Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 15. I2C-bus is a trademark of NXP B.V. MS1307-E-00 typ max Units ns ns ns ns ns ns ns 80 80 ns ns ns ns ns ns ns 20 20 Hz % ns ns 400 - kHz μs μs 0.3 0.3 50 400 μs μs μs μs μs μs μs μs ns pF 64fs 50 2011/05 - 10 - [AK4687] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing (Normal mode) VIH LRCK VIL tBLR tLRB tLRS VIH BICK VIL tBSD 50% TVDD SDTO tSDS tSDH VIH SDTI VIL Audio Interface Timing LRCK= LRCK1, LRCK2 BICK= BICK1, BICK2 MS1307-E-00 2011/05 - 11 - [AK4687] LRCK 50% DVDD tMBLR 50% DVDD BICK tBSD 50% DVDD SDTO Audio Interface timing (Master Mode) tPD VIH PDN VIL tPDV SDTO 50% DVDD Power Down & Reset Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop I2C Bus mode Timing MS1307-E-00 2011/05 - 12 - [AK4687] OPERATION OVERVIEW ■ System Clock The AK4687 has two audio serial interfaces (PORT1 and PORT2) which can be operated asynchronously. The PORT2 is the audio data interface for DAC, and the PORT1 is for ADC. At each PORT, the external clocks, which are required to operate the AK4687 in slave mode, are MCLK1 (MCLK2), LRCK1 (LRCK2) and BICK1 (BICK2). The MCLK1 (MCKK2) must be synchronized with LRCK1 (LRCK2) but the phase is not critical. The AK4687 has independent power-down function for ADC and DAC controlled by the PDN1 and PDN2 pins (or PWAD and PWDA bits). In I2C control mode, the AK4687 is in normal operation when PDN1pin=PDN2 pin= “H” and PWAD bit = PWDA bit = “1” (Table 1, Table 3). In H/W control mode (Table 2, Table 4), the AK4687 is in normal operation when PDN1 pin = PDN2 pin = “H”. The AK4687 is automatically powered-down when MCLK1 clock is stopped in master mode (MSN pin = “H”), or when MCLK1 (MCLK2), LRCK1 (LRCK2) and BICK1 (BICK2) are pulled-down in slave mode (MSN pin = “L”). In this case, the ADC output is “0” data and DAC output is pulled down to VSS. The power-down state is released and the AK4687 starts operation when MCLK1 is input in master mode (MSN pin = “H”), or when MCLK1 (MCLK2), LRCK1 (LRCK2) and BICK1 (BICK2) are input in slave mode (MSN pin = “L”). When the reset is released (PDN1/2 pin = “L” → “H”), such as after power up the device, the ADC/DAC of AK4687 is in power down state until MCLK1/2, LRCK1/2 and BICK1/2 is input. PDN1 pin PWAD bit L H H H × 0 1 1 Master mode: MCLK1 Slave mode: MCLK1,LRCK1 and BICK1 × × Non-active active ADC stauts ADC OUT Power down Power down Power down Power up 0 0 0 ADC output (×: Don’t Care) Table 1. System CLOCK for ADC (I2C Control Mode, PORT1) Master mode: MCLK1 Slave mode: MCLK1,LRCK1 and BICK1 × Non-active active PDN1 pin L H H ADC stauts ADC OUT 0 0 ADC output (×: Don’t Care) Table 2. System CLOCK for ADC (H/W Control Mode, PORT1) PDN2 pin PWDA bit L H H H × 0 1 1 MCLK2,LRCK2 and BICK2 × × Non-active active Power down Power down Power up DAC stauts DAC OUT VSS VSS VSS DAC output (×: Don’t Care) Table 3. System CLOCK for DAC (I2C Control Mode, PORT2) PDN2 pin L H H MCLK2,LRCK2 and BICK2 × Non-active active Power down Power down Power down Power up DAC stauts DAC OUT Power down Power down Power up VSS VSS DAC output (×: Don’t Care) Table 4. System CLOCK for DAC (H/W Control Mode, PORT2) MS1307-E-00 2011/05 - 13 - [AK4687] ■ Master/Slave Mode The MSN pin controls master/slave mode of the PORT1. The PORT2 supports slave mode only. In master mode, LRCK1 and BICK1 pins are output pins. In slave mode, LRCK1 (LRCK2) and BICK1 (BICK2) pins are input pins (Table 5). PORT1 (ADC) BICK1, LRCK1 Input (slave mode) Output “L”(master mode) MSN pin L H PORT2 (DAC) BICK2, LRCK2 Input (slave mode) Input (slave mode) Table 5. Master/Salve Mode ■ PORT1 (ADC) Clock Control In master mode (MSN pin = “H”), the required clock is MCLK1. The CKS1-0 bits and the CKS pin select the clock frequency (Table 6, Table 7). The ADC is in power-down state until MCLK1, BICK1 and LRCK1 are supplied. CKS1 bit CKS0 bit Clock Speed 0 0 256fs 0 1 384fs 1 0 512fs 1 1 768fs (default) 2 Table 6. PORT1(ADC) Master Clock Control (Master Mode, I C Control Mode) CKS pin Clock Speed L 256fs H 768fs Table 7. PORT1(ADC) Master Clock Control (Master Mode, H/W Control Mode) In slave mode (MSN pin = “L”), required clocks are MCLK1, BICK1 and LRCK1. The master clock (MCLK1) must be synchronized with LRCK1 but the phase is not critical. After exiting reset following power-up (PDN1 pin = “L” → “H”), the ADC of AK4687 is in power down state until MCLK1, LRCK1 and BICK1 are input. The ADC only supports Normal Speed Mode (fs = 32k ~ 48kHz). LRCK1 MCLK1 (MHz) Fs 256fs 384fs 512fs 32.0kHz 8.1920 12.2880 16.3840 44.1kHz 11.2896 16.9344 22.5792 48.0kHz 12.2880 18.4320 24.5760 768fs 24.5760 33.8688 36.8640 BICK1 (MHz) 64fs 2.0480 2.8224 3.0720 Table 8. PORT1(ADC) System Clock Example MS1307-E-00 2011/05 - 14 - [AK4687] ■ PORT2 (DAC) Clock Control External clocks (MCLK2, BICK2 and LRCK2) must always be present whenever the DAC is in normal operation (PDN pin = “H” or PWDA2 bit= “1”). The master clock (MCLK2) must be synchronized with LRCK2 but the phase is not critical. MCLK2 clock is used for interpolation filter and delta sigma modulator. During operation, DAC is automatically reset and the analog output goes to 0V (typ) if MCLK2, LRCK2 and BICK2 are stopped. This reset is released, and the DAC starts operation when MCLK2, LRCK2 and BICK2 are input again. The DAC is in power-down mode until MCLK2, BICK2 and LRCK2 are supplied. There are two modes for controlling the sampling speed of DAC. One is the Manual Setting Mode (ACKS bit = “0”) using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = “1”). 1. Manual Setting Mode (ACKS bit = “0”) When the ACKS bit = “0”, DAC is in Manual Setting Mode and the sampling speed is selected by DFS1-0 bits (Table 9). DFS1 bit 0 0 1 1 DFS0 bit 0 1 0 1 DAC Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 128kHz~192kHz Not Available - (default) Table 9. PORT2(DAC) Sampling Speed (ACKS bit = “0”, Manual Setting Mode) LRCK2 Fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920 11.2896 12.2880 MCLK2 (MHz) 384fs 512fs 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 768fs 24.5760 33.8688 36.8640 BICK2 (MHz) 64fs 2.0480 2.8224 3.0720 Table 10. PORT2(DAC) system Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK2 Fs 88.2kHz 96.0kHz 128fs 11.2896 12.2880 MCLK2 (MHz) 192fs 256fs 16.9344 22.5792 18.4320 24.5760 384fs 33.8688 36.8640 BICK2 (MHz) 64fs 5.6448 6.1440 Table 11. PORT2(DAC)system Clock Example(Double Speed Mode @Manual Setting Mode) LRCK2 Fs 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK2 (MHz) 192fs 256fs 33.8688 36.8640 - 384fs - BICK2 (MHz) 64fs 11.2896 12.2880 Table 12. PORT2(DAC) system Clock Example (Quad Speed Mode @Manual Setting Mode) MS1307-E-00 2011/05 - 15 - [AK4687] 2. Auto Setting Mode (ACKS bit = “1”) When the ACKS bit = “1”, DAC is in Auto Setting Mode and the sampling speed is selected automatically by the ratio of MCLK2/LRCK2, as shown in Table 13 and Table 14. In this mode, the settings of DFS1-0 bits are ignored. MCLK2 512fs, 768fs 256fs, 384fs 128fs, 192fs DAC Sampling Speed (fs) LRCK2 Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 128kHz~192kHz Table 13. PORT2(DAC) Sampling Speed (ACKS bit = “1”, Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs - 22.5792 24.5760 192fs - 33.8688 36.8640 MCLK (MHz) 256fs 384fs 512fs 16.3840 22.5792 24.5760 8.192 12.288 11.2896 16.9344 12.288 18.432 22.5792 33.8688 24.5760 36.8640 Table 14. System Clock Example 768fs 24.5760 33.8688 36.8640 1152fs 36.8640 - Sampling Speed Normal Double - - Quad When MCLK= 256fs/384fs, the AK4687 supports sampling rate of 32kHz~96kHz (Table 15). But, when the sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs. MCLK DR, S/N 256fs/384fs 102dB 512fs/768fs 105dB Table 15. MCLK Frequency and DR, S/N (fs = 48kHz) ■ De-emphasis Filter The DAC of AK4687 includes a digital de-emphasis filter (tc=50/15μs) by IIR filter. Setting the DEM1 bit to “1” enables the de-emphasis filter. Refer to “FILTER CHARACTERISTICS” about the gain error when this filter is ON. The de-emphasis filter is OFF in double speed mode (MCLK2= 256fs/38fs ) and quad speed mode (MCLK2=128fs/192fs). The filter setting is executed in I2C control mode and DEM bit controls ON/OFF of the filter. (Table 17) DEM bit De-emphasis Filter 1 ON (default) 0 OFF Table 16. De-emphasis Control (Normal Speed Mode) MS1307-E-00 2011/05 - 16 - [AK4687] ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and frequency response scales with sampling rate (fs). ■ Audio Serial Interface Format Each PORT1/2 can select audio interface format independently. The DIF1 bit controls audio data format of the PORT1. The DIF1-0 bits control the audio data format of the PORT2. In all modes the serial data is MSB-first, 2’s complement format. The SDTO pin is clocked out on the falling edge of BICK1 and the SDTI pin is latched on the rising edge of BICK2. SDTI input formats can be used for 16-24bit data by zeroing the unused LSBs. 1. PORT1 (ADC) Setting The MSN pin and DIF1 bit select following four serial data formats (Table 17). Mode MSN pin DIF1 bit 0 L 0 1 L 1 2 H 0 3 H 1 LRCK1 L/R I/O SDTO BICK1 speed I/O ≥ 48fs or I 32fs I ≥ 48fs 24/16bit H/L I Left Justified 24bit, I2S L/H I 24bit H/L O 64fs Left Justified 2 24bit, I S L/H O 64fs Table 17. Audio Interface Format (ADC) O (default) (default) O 2. PORT2 (DAC) Setting The DIF21-20 bits select following four serial data formats (Table 18). Mode DIF21 bit DIF20 bit 0 1 2 3 0 0 1 1 0 1 0 1 LRCK2 L/R I/O 16bit, Right justified H/L I 24bit, Right justified H/L I 24bit, Left justified H/L I 24bit, I2S L/H I Table 18. Audio Interface Format (DAC) SDTI MS1307-E-00 BICK2 speed I/O I ≥ 32fs I ≥ 48fs I ≥ 48fs I ≥ 48fs (default) 2011/05 - 17 - [AK4687] LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 12 11 10 Don’t Care 0 15 14 23 22 8 7 1 12 11 10 Don’t Care 0 0 15 14 SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 3. PORT1= Mode0/2, PORT2=Mode0 Timing LRCK 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1 BICK (64fs) SDTO(o) 23 22 16 15 14 Don’t Care SDTI(i) 0 23 22 23:MSB, 0:LSB 23 22 8 7 1 16 15 14 Don’t Care 0 0 23 22 Lch Data 23 8 7 1 0 Rch Data Figure 4. PORT1= Mode0/2, PORT2=Mode1 Timing LRCK 0 1 2 21 22 23 24 28 29 30 31 0 1 2 22 23 24 28 29 30 31 0 1 BICK (64fs) SDTO(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data 23 Don’t Care 23 Rch Data Figure 5. PORT1= Mode0/2, PORT2=Mode2 Timing LRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK (64fs) SDTO(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data Don’t Care Rch Data Figure 6. PORT1= Mode1/3, PORT2=Mode3 Timing MS1307-E-00 2011/05 - 18 - [AK4687] ■ Input Selector The AK4687 has 3:1 stereo input selectors. AIN1-0 bits control each input channel in I2C control mode, and AIN1/0 pins control each selector in H/W control mode. (Table 19) AIN1 bit AIN0 bit Input Selector 0 0 LIN1 / RIN1 0 1 LIN2 / RIN2 1 0 LIN3 / RIN3 1 1 Reserved Table 19. ADC Input Selector (I2C Control Mode) (default) AIN1 pin AIN0 pin Input Selector L L LIN1 / RIN1 L H LIN2 / RIN2 H L LIN3 / RIN3 H H Reserved Table 20. ADC Input Selector (H/W Control Mode) ■ Pre-Amp and Input ATT The input attenuation circuit is constructed by connecting input resistors (Ri) to LIN1-3/RIN1-3 pins and feedback resistors (Rf) between LI/RI pin and LO/RO pin (Figure 7). The input voltage tolerance of the LO/RO pin is typically 1.91Vrms. Therefore, excessive inputs such as 2Vrms or 4Vrms to the LIN1-3/RIN1-3 pins via Ri resistors must be attenuated to 1.91Vrms by these Ri and Rf resistors. Table 21 shows resistance examples of Ri and Rf. Rf LO LI Ri LIN1 Ri LIN2 Ri LIN3 Pre-Amp Figure 7. Pre-Amp and Input ATT Input Range Ri (kΩ) 4Vrms 2.2Vrms 1Vrms 47 47 47 Rf (kΩ) 20 39 82 ATT Gain (dB) LO/RO pin ADC output (typ) -7.42 -1.62 +4.83 1.70Vrms 1.82Vrms 1.74Vrms -1.0dBFS -0.39dBFS -0.78dBFS Table 21. Input ATT example MS1307-E-00 2011/05 - 19 - [AK4687] ■ Charge Pump Circuit The internal charge pump circuit generates negative voltage (CVEE) from CVDD voltage for analog input and output. The power up time of charge pump circuit is 1.3ms@48kHz. When PWAD and PWDA bits = “1”, the ADC and DAC are powered-up after the charge pump circuit is powered-up. The power-up conditions of the charge pump circuit are: I2C Control Mode • PDN1 pin = “H”, PWAD bit = “1” and MCLK1, LRCK1 and BICK1 (MCLK1 only in master mode) are input. • PDN2 pin = “H”, PWDA bit = “1” and MCLK2, LRCK2 and BICK2 are input. H/W Control Mode • PDN1 pin = “H” and MCLK1, LRCK1 and BICK1 (MCK1 only in master mode) are input. • PDN2 pin = “H” and MCLK2, LRCK2 and BICK2 are input. PDN1 pin PWAD bit H x 1 x Master mode: MCLK1 Slave mode: MCLK1,LRCK1, BICK1 active x PDN2 pin PWDA bit MCLK2, BICK2, LRCK2 CP status x H x 1 x active ON ON (×: Don’t Care) Table 22. Charge Pump Power ON Conditions (I2C Control Mode) PDN1 pin H x Master mode: MCLK1 Slave mode: MCLK1, LRCK1, BICK1 Active x PDN2 pin x H MCLK2, BICK2, LRCK2 CP status x active ON ON (×: Don’t Care) Table 23. Charge Pump Power ON Conditions (H/W Control Mode) AK4687 DVDD Charge Pump CP CN Negative Power VSS3 (+) 1uF Ca VEE Cb 1uF (+) Figure 8. Charge Pump Circuit Note: Connect a 1µF low ESR capacitor between CP and CN pins, and VSS3-VEE pins respectively. MS1307-E-00 2011/05 - 20 - [AK4687] ■ Analog Input/Output (LIN1-3/RIN1-3, LOUT/ROUT pins) Power supply voltage for analog input/output is applied from a regulator for positive power and a charge-pump for negative power. The analog output is single-ended and centered on 0V (VSS2). Therefore, a capacitor for AC-coupling can be removed. The minimum load resistance is 5kΩ. When the DAC input signal level is 0dBFS, the output voltage is 2Vrms. ■ Soft Mute The DAC has a soft mute function. The soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the input data is attenuated by -∞ in 1024LRCK cycle. When the SMUTE bit returns to “0”, the mute is cancelled and the attenuation level gradually changes to 0dB in 1024 LRCK cycle. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and the attenuation level returns to 0dB in the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD LOUT/ROUT Notes: (1) In normal speed mode, the input data is attenuated to -∞ in 1024LRCK cycle. For example, this time is 2048LRCK cycles (2048/fs) in Double Speed Mode, and 4096LRCK cycle (4096/fs) in Quad Speed Mode. (2) The analog output corresponding to the digital input has group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and the attenuation level returns to 0dB in the same cycle. Figure 9. Soft Mute Function ■ System Reset When power-up the AK4687, the PDN1 and PDN2 pins should be “L” and changed to “H” after all power supplies (DVDD, AVDD1, and AVDD2) are supplied. After this reset is released (PDN1 and PDN2 pins = “L” → “H”), all blocks are in power-down mode. This ensures that all internal registers reset to their initial values. ADC internal circuit, control registers for ADC (Addr: 01h-02h) and PWAD bit are reset by PDN1 pin = “L”. DAC internal circuit, control registers for DAC (Addr: 03h) and PWDA bit are reset by PDN2 pin = “L”. When both PDN1 and PDN2 pins are “L”, all blocks, resisters and charge pump are powered-down. In H/W control mode, register settings are ignored and the power-down controls by PDN1 and PDN2 pins are available. MS1307-E-00 2011/05 - 21 - [AK4687] ■ Power ON/OFF Sequence The ADC and DAC blocks of the AK4687 are placed in power-down mode by bringing the PDN1 pin and PDN2 pin to “L” respectively and both digital filters are reset at the same time. The PDN1 pin = PDN2 pin =“L” also reset the control registers to their default values. In power-down mode, the DAC outputs 0V and the SDTO pin goes to “L”. This reset must always be executed after power-up. In master mode, the ADC starts operation on the rising edge of MLCK1 after power-down mode is released by a status change of the PDN1 pin from “L” to “H”. In slave mode, when power down mode is released by a status change of the PDN1 pin from “L” to “H”, the ADC starts operation on the rising edge of LRCK1 after MLCK1, LRCK1 and BICK1 are input. The DAC starts operation on the rising of the LRCK2, after power-down mode is released by a status change of the PDN2 pin from “L” to “H”, and MCLK2, LRCK2 and BICK2 are input. The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 2640 cycles of LRCK1 clock. In case of the DAC, an analog initialization cycle starts after exiting the power-down mode. The analog outputs are 0V during the initialization. Figure 10 shows power-down and power-up sequence. The ADC and DAC can be powered-down individually by PWAD and PWDA bits. Register values are not initialized by these bits. When PWAD bit = “0”, the ADC output goes to “L”. When PWDA bit = “0”, the DAC output goes to 0V. As some click noise occurs, the analog output should be muted externally if the click noise influences system application. Power (1) PDN1 pin = PDN2 pin (2) CVEE pin 0V CVEE VREF1/2 pin 0V 80% AVDD2 0V (7) (8) ADC Internal State timeA (3) Init Cycle (9) Normal Operation Power-down timeB (4) DAC Internal State Normal Operation (5) GD Power-down GD ADC In (Analog) (6) ADC Out (Digital) “0”data DAC In (Digital) “0”data “0”data “0”data GD (5) GD DAC Out (Internal Status) Clock In Don’t care Don’t care MCLK1,LRCK1,BICK1 MCLK2,LRCK2,BICK2 Figure 10. Power-up/down sequence example MS1307-E-00 2011/05 - 22 - [AK4687] Notes: (1) The PDN1 and PDN2 pins should be changed from “L” to “H” after power up. “L” time of 150ns or more is needed to reset the AK4687. The PDN pins must be held to “L” until all power supply pins are fed. After all powers are risen up, the PDN1 and PDN2 pins should be set to “H”. (2) Charge Pump Circuit Power-up: When MCLK1/2, BICK1/2 and LRCK1/2 are input after the PDN1/2 pin = “L” → “H”, the voltage on the CVEE pin rises to CVEE voltage approximately in 1.3msec@48kHz. Note: If the PWAD and PWDA bits are set to “1”, or PDN1 and PDN2 pins are set “H” → “L” when the charge-pump is power-on, ADC and DAC are initialized after the charge-pump circuit is powered-on. (3) The analog block of ADC is initialized after exiting the power-down state. timeA=528/fs (4) The analog block of DAC is initialized after exiting the power-down state. In case of connecting a 1µF to the VREF2 pin, timeB is shown below. timeB= 6/fs x 8 x 2: Normal Speed Mode timeB=12/fs x 8 2: Double Speed Modd timeB= 24/fs x 8 x 2 Quatruple Speed Mode Inputting D/A data becomes available after the timeB period. (5) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (GD). (6) ADC outputs “0” data in power-down state. (7) Charge Pump Circuit Power-down (PDN1 pin = “H”→“L” or No MCLK1, BICK1 and LRCK1 inputs) and (PDN2 pin = “H”→“L” or No MCLK2, BICK2 and LRCK2 inputs) The CVEE pin becomes 0V according to a flying capacitor and internal resistor. The internal resister is 50kΩ (typ). Therefore, when the CVEE pin has a flying capacitor of 1µF, the time constant is 50msec (typ). (8) It takes 2048/fs for VREF1 stabilization after charge pump is powered-up. (9) It takes approximately 5msec (typ) until VREF1/2 rises up after power-down mode of ADC/DAC is released. MS1307-E-00 2011/05 - 23 - [AK4687] ■ Serial Control Interface The AK4687 supports fast-mode I2C-bus system (max: 400kHz). 1. Data Transfer In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single slave address which includes the device address. IC devices on the BUS compare this slave address with their own addresses and the IC device which has an identical address with the slave-address generates an acknowledgement. The IC device with the identical address executes either a read or a write operation. After the command execution, input a stop condition. 1-1. Data Change Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is “L”. Change the SDA line condition while SCL line is “H” only when the start condition or stop condition is input. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 11. Data Transfer 1-2. Start Condition and Stop Condition A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions are initiated by a start condition. A stop condition is generated by the transition of “L” to “H” on SDA line while SCL line is “H”. All instructions end by a stop condition. SCL SDA START CONDITION STOP CONDITION Figure 12. START and STOP Conditions MS1307-E-00 2011/05 - 24 - [AK4687] 1-3. Acknowledge An external device that is sending data to the AK4687 releases the SDA line (“H”) after receiving one-byte of data. An external device that receives data from the AK4687 then sets the SDA line to “L” at the next clock. This operation is called “acknowledgement”, and it enables verification that the data transfer has been properly executed. The AK4687 generates an acknowledgement upon receipt of a start condition and Slave address. For a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by generation of an acknowledgement, the AK4687 releases the SDA line after outputting data at the designated address, and it monitors the SDA line condition. When the master side generates an acknowledgement without sending a stop condition, the AK4687 outputs data at the next address location. When no acknowledgement is generated, the AK4687 ends data output (not acknowledged). Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 13. Acknowledge on the I2C-bus 1-4. FIRST BYTE The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of the upper 6-bits is “001001”. The next 1 bit is the address bit that selects the desired IC (CAD0 bit). Set CAD0 bit according to the CAD0 pin setting (CAD0 pin = “L”: CAD0 bit = “0”, CAD0 pin = “H”: CAD0 bit = “1”). When the Slave-address is inputted, an external device that has the identical device address generates an acknowledgement and executes commands. The 8th bit of the First Byte (LSB) is allocated as R/W bit. When the R/W bit is “1”, a read instruction is executed, and when it is “0”, a write instruction is executed. 0 0 1 0 0 1 CAD0 R/W Figure 14. The First Byte MS1307-E-00 2011/05 - 25 - [AK4687] 2. WRITE Operations Set R/W bit = “0” for the WRITE operation of the AK4687. After receipt of the start condition and the first byte, the AK4687 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4687. The format is MSB first, and those most significant 3-bits are “Don’t care”. * * * A4 A3 A2 A1 A0 (*: Don’t care) Figure 15. The Second Byte After receipt of the second byte, the AK4687 generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits. D7 D6 D5 D4 D3 D2 D1 D0 Figure 16. Byte Structure after the Second Byte The AK4687 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4687 generates an acknowledge, and awaits the next data again. The master can transmit more than one data word instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. S T A R T SDA Register Address(n) Slave Address S T Data(n+x) O P Data(n+1) Data(n) P S A C K A C K A C K A C K Figure 17. WRITE Operation MS1307-E-00 2011/05 - 26 - [AK4687] 3. READ Operations Set R/W bit = “1” for a READ operation of the AK4687. The master can read next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal 3bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4687 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 3-1. CURRENT ADDRESS READ The AK4687 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4687 generates an acknowledge, transmits 1byte data, which address is set by the internal address counter, and increments the internal address counter by 1. If the master does not generate an acknowledge but generate stop condition, the AK4687 discontinues transmission S T A R T SDA Slave Address Data(n) Data(n+1) S Data(n+x) T O P Data(n+2) P S A C K A C K A C K A C K Figure 18. CURRENT ADDRESS READ 3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues start condition, slave address(R/W bit=“0”) and then the register address to read. After the register address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4687 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge but generate the stop condition, the AK4687 discontinues transmission. S T A R T SDA S T A R T Word Address(n) Slave Address S Slave Address Data(n) S Data(n+x) T O P Data(n+1) P S A C K A C K A C K A C K A C K Figure 19. RANDOM READ MS1307-E-00 2011/05 - 27 - [AK4687] ■ Register Map Addr 00H 01H 02H 03H Register Name Powerdown/Control AD Input AD Clock DAC Clock D7 0 0 0 0 D6 0 0 0 ACKS D5 0 0 0 DFS1 D4 0 0 DIF1 DFS0 D3 0 0 0 DEM D2 0 0 CKS1 DIF21 D1 PWDA AIN1 CKS0 DIF20 D0 PWAD AIN0 0 SMUTE Note: For addresses from 04H to 1FH, data must not be written. All registers are initialized to their default values by setting the PDN1 and PDN2 pins to “L”. ADC is powered down by setting the PDN1 pin to “L”. Registers for ADC (Addr: 01h-02h) and PWAD bit are initialized. DAC is powered down by setting the PDN2 pin to “L”. Registers for DAC (Addr: 03h) and PWDA bit are initialized. ADC is powered down by setting the PWAD bit to “0”. However, registers for ADC (Addr: 01h-02h) are not initialized. DAC is powered down by setting the PWDA bit to “0”. However, registers for DAC (Addr: 03h) is not initialized. The bits defined as 0 must contain a “0” value. MS1307-E-00 2011/05 - 28 - [AK4687] ■ Register Definitions Addr 00H Register Name Power down/Control R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 PWDA R/W 0 D0 PWAD R/W 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 AIN1 R/W 0 D0 AIN0 R/W 0 PWAD: ADC Power-down Control 0: Power-down (default) 1: Normal operation PWDA: DAC Power-down Control 0: Power-down (default) 1: Normal operation Addr 01H Register Name AD Input R/W Default D7 0 RD 0 AIN1-0: ADC input selector control (Table 19) 00: LIN1/RIN1 (default) 01: LIN2/RIN2 10: LIN3/RIN3 11: Reserved MS1307-E-00 2011/05 - 29 - [AK4687] Addr 02H Register Name AD Clock R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 DIF1 R/W 0 D3 0 RD 0 D2 CKS1 R/W 1 D1 CKS0 R/W 1 D0 0 RD 0 D3 DEM R/W 0 D2 DIF21 R/W 1 D1 DIF20 R/W 0 D0 SMUTE R/W 0 CKS1-0: PORT1 (ADC) Clock Control in Master Mode See Table 6. DIF1: PORT1 Audio Format Select See Table 17. Addr 03H Register Name DAC Clock R/W Default D7 0 RD 0 D6 ACKS R/W 1 D5 DFS1 R/W 0 D4 DFS0 R/W 0 SMUTE: Soft Mute control for DAC 0: Normal Operation (default) 1: LOUT/ROUT outputs soft-muted DIF21-20: PORT2 Audio Format Select See Table 18. DEM: DAC De-emphasis Response Control See Table 16. DFS1-0: PORT2 (DAC) Sampling Speed Control See Table 9. DFS1-0 bits setting is ignored in Auto Setting Mode (ACKS bit = “1”). ACKS: PORT2 (DAC) Auto Setting Mode Control 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode (default) The MCLK frequency is detected automatically when ACKS bit= “1”. In this case, DFS1-0 bits settings are ignored. When ACKS bit = “0”, DFS1-0 bits select the sampling speed mode, and the MCLK frequency is automatically detected in each mode. MS1307-E-00 2011/05 - 30 - [AK4687] SYSTEM DESIGN Figure 20 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Micro Controller Audio DSP2 47k 47k 1 MSN LI 36 2 SDTO LO 35 3 LRCK1 RO 34 4 BICK1 RI 33 AK4687EQ 6 PDN1 39k 1u (∗) AVDD1 31 7 PDN2 VSS1 30 8 MCLK2 VSS4 29 9 BICK VSS5 28 10 LRCK VSS2 27 0.1u + 10u 0.1u 10u + 3.3V 1u (∗) 3.3V 24 LOUT 23 ROUT 22 NC 21 CVEE 20 CN 19 CP 18 VSS3 17 DVDD VREF2 25 16 NC 12 CAD0 15 NC AVDD2 26 14 TEST2 11 SDTI 13 TEST1 39k VREF1 32 5 MCLK1 Reset and Power down RIN3 37 NC 39 LIN3 38 47k 47k LIN2 41 RIN2 40 47k NC 42 RIN1 43 NC 45 I2C 46 SCL 48 Audio DSP1 3.3V SDA 47 3.3V LIN1 44 47k Analog in 0.1u 10u + 1u (∗) 1u (∗) Analog Out 3.3V Figure 20. Typical Connection Diagram (I2C Control mode, CAD0 pin = “L”, Master mode) Notes: (1) Use low ESR (Equivalent Series Resistance) capacitors for the capacitors with (*). When using polarized capacitors, the positive polarity pin should be connected to the CP or VREF1/2 pin, and the negative polarity pin should be connected to the CVEE pin. (2) VSS1, VSS2, VSS3, VSS4 and VSS5 must be connected to the same analog ground plane. (3) Digital input pins should not be allowed to float. MS1307-E-00 2011/05 - 31 - [AK4687] Mode Setting Audio DSP1 3.3V 47k LI 36 2 SDTO LO 35 3 LRCK1 RO 34 4 BICK1 RI 33 39k 39k 1u (∗) VREF1 32 AK4687EQ 6 PDN1 AVDD1 31 7 PDN2 VSS1 30 8 MCLK2 VSS4 29 9 BICK VSS5 28 10 LRCK VSS2 27 0.1u + 10u 0.1u 10u + 3.3V 1u (∗) 3.3V 24 LOUT 23 ROUT 22 NC 21 CVEE 20 CN 19 CP 18 VSS3 17 DVDD VREF2 25 16 NC 12 CKS 15 NC AVDD2 26 14 TEST2 11 SDTI 13 TEST1 Audio DSP2 47k 1 MSN 5 MCLK1 Reset and Power down RIN3 37 NC 39 LIN3 38 47k 47k LIN2 41 RIN2 40 47k NC 42 RIN1 43 NC 45 LIN1 44 I2C 46 AIN1 47 AIN0 48 47k Analog in 0.1u 1u (∗) 10u + 1u (∗) Analog Out 3.3V Figure 21. Typical Connection Diagram (H/W Control mode, MCLK=768fs, Master mode) Notes: (1) Use low ESR (Equivalent Series Resistance) capacitors for the capacitors with (*). When using polarized capacitors, the positive polarity pin should be connected to the CP or VREF1/2 pin, and the negative polarity pin should be connected to the CVEE pin. (2) VSS1, VSS2, VSS3, VSS4 and VSS5 must be connected to the same analog ground plane. (3) Digital input pins should not be allowed to float. MS1307-E-00 2011/05 - 32 - [AK4687] 1. Grounding and Power Supply Decoupling The AK4687 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2 and DVDD are usually supplied from the system’s analog supply. If AVDD1, AVDD2 and DVDD are supplied separately, the power up sequence is not critical. VSS1, VSS2, VSS3, VSS4 and VSS5 of the AK4687 must be connected to the same analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4687 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The differential voltage between AVDD1 and VSS1 sets the analog input range, and the differential voltage between AVDD2 and VSS2 sets the analog output range. VREF1/VREF2 are signal common of this chip. A 1µF ceramic capacitor attached between the VREF1 and VREF2 pins eliminates the effects of high frequency noise. No load current may be drawn from the VREF1/VREF2 pins. All signals, especially clocks, should be kept away from the VREF1/VREF2 pins in order to avoid unwanted coupling into the AK4687. 3. Analog Inputs The analog input is single-ended and supplied to the Pre-amp via external resistors. Select the feedback resistance to make the pre-amp output match to the input range (typ. 1.91Vrms) of the ADC (LO and RO pins). The ADC output data format is 2’s complement. The internal digital HPF removes the DC offset. The AK4687 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4687 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 4. Analog Outputs The analog outputs are single-ended and centered around the VSS2 (0V typ.) voltage. The output signal range is typically 2.0Vrms (typ @AVDD2=3.3V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Using a 1st-order LPF (Figure 22) can reduce noise beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is 0V (VSS) for 000000H (@24bit). The DC offset is within ±5mV. AK4687 470 Analog Out L/R OUT 2.0Vrms (typ) 2.2nF (fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz) Figure 22. External Circuit Example1 5. Attention to the PCB Wiring LIN1-3 and RIN1-3 pins are the summing nodes of the Pre-Amp. Attention should be given to avoid coupling with other signals on those nodes. This can be accomplished by making the wire length of the input resistors as short as possible. The same theory also applies to the LI/RI pins and feedback resistors; keep the wire length to a minimum. Unused input pins among LIN1-3 and RIN1-3 pins must be left open. MS1307-E-00 2011/05 - 33 - [AK4687] PACKAGE 48pin LQFP (Unit: mm) 1.70Max 9.0 ± 0.2 0.13 ± 0.13 7.0 36 1.40 ± 0.05 24 48 13 7.0 37 12 1 0.5 9.0 ± 0.2 25 0.09 ∼ 0.20 0.22 ± 0.08 0.10 M 0° ∼ 10° 0.10 0.3 ∼ 0.75 ■ Material & Lead Finish Package molding compound: Epoxy, Halogen (Br and Cl) free Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS1307-E-00 2011/05 - 34 - [AK4687] MARKING AK4687EQ XXXXXXX 1 1) Pin #1 indication 2) Marking Code: AK4687EQ 3) Date Code: XXXXXXX (7 digits) REVISION HISTORY Date (YY/MM/DD) 11/05/30 Revision 00 Reason First Edition Page MS1307-E-00 Contents 2011/05 - 35 - [AK4687] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1307-E-00 2011/05 - 36 -