Intersil D2MC-76083-LR Powered speaker system Datasheet

DATASHEET
Intelligent Digital Amplifier and Sound Processor
D2-7xx83
Features
The D2-7xx83 family of the DAE-6™ Digital Audio Engine™
devices are complete System-on Chip (SoC) audio processor
and Class-D amplifier controllers. Integrated DSP processing
and configurable audio processing algorithms provide an
extremely flexible platform for feature rich and cost-effective
quality audio solutions which benefit from the addition of
Class-D amplifiers and DSP audio processing, meeting
demands of consumer electronics applications.
• Advanced DAE-6™ Digital Audio Engine™ IC
- Pin Compatible and Function/Feature Compatible with
the D2Audio™ DAE-3™ Device
The 12 integrated digital PWM controllers can be used in a
variety of multi-channel audio system configurations,
supporting powered as well as line outputs. Fully protected
amplifier control provides efficient and clean Class-D power
output support.
The DAE-6™ device family supports full audio decoding for
formats including Dolby® Digital, Dolby® Pro Logic IIx,
AAC LC™, DTS® Digital Surround, DTS® ES, and DTS Neo:6®.
The DAE-6 is pin-compatible and function/feature compatible
with the DAE-3™ devices, enabling additional decoding
capability to existing designs, or providing cost optimization to
lower-featured systems not requiring the additional audio
processing and decode capability.
Applications
• Audio Video Receiver (AVR)
• DTV Soundbar
• Home Theater in A Box (HTiB)
• Multi-Channel Multi-Media (MM) Systems
• Multi-Room Distributed Audio (MRDA)
• Powered Speaker Systems
• Automotive Trunk/Amplified Solutions
April 28, 2016
FN7838.3
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• Total System on Chip (SoC)
- All Digital Class-D Amplifier Controller
- Full 5.1/7.1/9.1-Channel Amplifier Platform Support
• Enhanced Audio Processing Decoders
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- AAC LC™
- DTS® Digital Surround
- DTS® ES
- DTS Neo:6®
• D2Audio™ SoundSuite™ Enhancement and Virtualization
• Mark Levinson MightyCat™ Audio Enhancement
• Expanded On-Chip Memory Capacity
• Integrated DSP Processing
- 12 Channels of Digital Signal Processing (DSP) including
Equalizers, Filters, Mixers and Other Common Audio
Processing Blocks
- Fully Configurable and Routable Audio Signal Paths
• Flexible Audio Input and Output Configurations
• Embedded 8-Channel Sample Rate Converter
- Sample Rates from 32kHz up to 192kHz
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load
(BTL) Topologies, Using Discrete or Integrated Power
Stages from 10W to Over 500W
- Complete Fault Protection with Automatic Recovery
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2016. All Rights Reserved
Intersil (and design), DAE-6 and D2Audio are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
D2-7xx83
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
AUDIO PROCESSING
FEATURE SET SUPPORT
(Note 1)
TEMP.
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
D2-71083-LR
D2-71083-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-74083-LR
D2-74083-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-71583-LR
D2-71583-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-74583-LR
D2-74583-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2-71683-LR
(No longer available, recommended
replacement: D2-71583-LR)
D2-71683-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2MC-72083-LR
(No longer available or supported)
D2MC-72083-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
D2MC-76083-LR
(No longer available or supported)
D2MC-76083-LR
Refer to Table 1
-10 to +85
128 Ld LQFP
Q128.14x14
NOTES:
1. The D2-7xx83 devices support multiple audio processing algorithms and decoders, and support is device-dependent. Refer to Table 1 for the
supported features for each device part number.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. .For Moisture Sensitivity Level (MSL), please see product information page for D2-71083, D2-74083, D2-71583, D2-74583, D2-71683, D2MC-72083,
D2MC-76083. For more information on MSL, please see tech brief TB363.
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FN7838.3
April 28, 2016
D2-7xx83
DAE-6 Device Feature Set Offering
The D2-7xx83 family has specific part numbers to specify the features and algorithms supported in the device. These part numbers
their supported features are shown in Table 1.
TABLE 1. DAE-6 DEVICE PART NUMBERS AND FEATURES
PART NUMBER
FEATURES
ALGORITHM SUPPORT
DSP CLOCK AND MEMORY
(Note 4)
D2-71083-LR
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
D2Audio™ SoundSuite™ Audio Processing
147MHz DSP Clock
24k X and Y Memory Capacities
32k P Memory Capacity
D2-74083-LR
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
D2Audio™ SoundSuite™ Audio Processing
160MHz DSP Clock
40K X and Y Memory Capacities
56k P Memory Capacity
D2-71583-LR
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
D2Audio™ SoundSuite™
Dolby® Digital/AC3 Decoder
Dolby® Pro Logic IIx Surround
DTS® Digital Surround Decoder
147MHz DSP Clock
24k X and Y Memory Capacities
32k P Memory Capacity
D2-74583-LR
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
D2Audio™ SoundSuite™
Dolby® Digital/AC3 Decoder
Dolby® Pro Logic IIx Surround
DTS® Digital Surround Decoder
160MHz DSP Clock
40k X and Y Memory Capacities
56k P Memory Capacity
D2-71683-LR
(No longer
available,
recommended
replacement:
D2-71583-LR)
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
D2Audio™ SoundSuite™
Dolby® Digital/AC3 Decode Processing
Dolby® Pro Logic IIx Surround Processing
DTS® Digital Surround Decode Processing
AAC LC™ Decode Processing
147MHz DSP Clock
24k X and Y Memory Capacities
32k P Memory Capacity
D2MC-72083-LR
(No longer
available or
supported)
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
Mark Levinson MightyCat™ Audio
Processing
147MHz DSP Clock
24k X and Y Memory Capacities
32k P Memory Capacity
D2MC-76083-LR
(No longer
available or
supported)
8-Channels Audio of I2S Digital Inputs
2 S/PDIF Digital Inputs
8 Audio Processing Channels with PWM Outputs
Embedded 8-Channel Sample Rate Converter
Mark Levinson MightyCat™ Audio
Processing
160MHz DSP Clock
40k X and Y Memory Capacities
56k P Memory Capacity
NOTE:
4. 147MHz DSP clock speed represents an actual DSP clock of 147.456MHz, and 160MHz DSP clock speed represents an actual DSP clock
of 159.744MHz, when using a crystal frequency of 24.576MHz.
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3
FN7838.3
April 28, 2016
D2-7xx83
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DAE-6 Device Feature Set Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Audio Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Two-Wire (I2C) Interface Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI™ Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Features and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Processing Signal Flow Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Converters (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks And PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booting and Boot Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Audio Processing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Firmware Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tone Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Excursion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upward Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High/Low-Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loudness Contour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Processing Enhancements and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SoundSuite™ Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mark Levinson MightyCat™ Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Disclaimer for Dolby Technology License Required Notice:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Disclaimer for DTS (SRS) Technology License Required Notice: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low Plastic Quad Flatpack Packages (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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FN7838.3
April 28, 2016
D2-7xx83
Absolute Maximum Ratings
Thermal Information
(Note 7)
Supply Voltage
RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
128 Ld LQFP Package (Notes 5, 6) . . . . . .
40
6.5
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications
TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration.
SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
(Note 11)
TYP
MAX
(Note 11)
UNIT
VIH
Digital Input High Logic Level (Note 8)
RVDD = 3.3V
(Scales with
RVDD)
2.0
-
-
V
VIL
Digital Input Low Logic Level (Note 8)
RVDD = 3.3V
(Scales with
RVDD)
-
-
0.8
V
VOH
High Level Output Drive Voltage
(IOUT at - Pin Drive Strength Current, see “Pin Descriptions” on
page 11)
RVDD - 0.4
-
-
V
VOL
Low Level Output Drive Voltage
(IOUT at + Pin Drive Strength Current, see “Pin Descriptions” on
page 11)
-
-
0.4
V
VIHX
High Level Input Drive Voltage XTALI Pin
0.7
-
PLLVDD
V
VILX
Low Level Input Drive Voltage XTALI Pin
-
-
0.3
V
IIN
Input Leakage Current (Note 9)
-
-
±10
µA
CIN
Input Capacitance
-
9
-
pF
V
VOHO
High Level Output Drive Voltage OSCOUT Pin
PLLVDD - 0.3
-
-
VOLO
Low Level Output Drive Voltage OSCOUT Pin
-
-
0.3
V
COUT
Output Capacitance
-
9
-
pF
tRST
nRESET Pulse Width
-
10
-
ns
3.0
3.3
3.6
V
-
15
-
mA
mA
(Voltage)
RVDD/ Typical Digital and PWM I/O Pad Ring Supply
PWMVDD
(Current, Active)
(Current, Power-down)
CVDD
Typical Core Supply
(Voltage)
(Current, Active)
(Current, Power-down)
PLLVDD
Typical PLL Analog Supply
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5
-
<1
-
1.7
1.8
1.9
V
-
450
-
mA
-
15
-
mA
1.7
1.8
1.9
V
(Current, Active)
-
25
-
mA
(Current, Power-down)
-
10
-
mA
(Voltage)
FN7838.3
April 28, 2016
D2-7xx83
Electrical Specifications
TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration. (Continued)
MIN
(Note 11)
TYP
MAX
(Note 11)
3.0
3.3
3.6
V
-
12
-
mA
Crystal Frequency (Fundamental Mode Crystal)
20
24.576
24.822
(24.576 + 1%)
MHz
Duty Cycle
40
-
60
%
-
5
20
ms
SYMBOL
ADCVDD
TEST
CONDITIONS
PARAMETER
Typical ADC Analog Supply
(Voltage)
(Current, Active, Power-Down)
UNIT
CRYSTAL OSCILLATOR
Xo
Dt
tSTART
Start-Up Time (Start-Up Time is Oscillator Enabled
(with Valid Supply) to Stable Oscillation)
PLL
FVCO
FIN
VCO Frequency
80.00
294.912
297.86
MHz
Input Reference Frequency
20
-
24.822
(24.576 + 1%)
MHz
Feedback Dividers (Integer)
4
12
15
PLL Lock Time from any Input Change
-
2
-
ms
1.8V POWER-ON RESET
VEN
Reset Enabled Voltage Level
-
1.1
1.4
V
tREJ
POR Pulse Width Rejection
-
150
500
(Note 12)
µs
tDIS
POR Minimum Output Pulse Width
-
5
-
µs
1.4
1.5
1.6
V
-
100
-
ns
20
-
-
ns
2.5
2.7
2.9
V
-
100
-
ns
20
-
-
ns
1.3
1.4
1.5
V
-
-
±20
µA
-
14
-
kΩ
VREF - 0.6
-
VREF + 0.6
V
1.8V BROWNOUT DETECTION
Detect Level
tBOD1
tO1
Pulse Width Rejection
Minimum Output Pulse Width
3.3V BROWNOUT DETECTION
Detect Level
tBOD3
tO3
Pulse Width Rejection
Minimum Output Pulse Width
ADC PERFORMANCE SPECIFICATIONS
VREF
ADCREF DC Level
IREF
ADCREF Load Current
IREF = 0
RREF
ADCREF Source Impedance
VAIN
Analog Input Level
Dynamic Range
-
94
-
dB
THD+N
-
-80
-
dB
Gain Mismatch
-
0.1
-
dB
Crosstalk
-
-80
-
dB
Power Supply Rejection
-
-70
-
dB
NOTES:
8. All input pins except XTALI.
9. Input leakage applies to all pins except XTALO.
10. Power-down is with device in reset and clocks stopped.
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
12. Limits established by characterization and are not production tested.
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FN7838.3
April 28, 2016
D2-7xx83
Serial Audio Interface Port Timing
(Figure 1) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
MIN
(Note 11)
DESCRIPTION
TYP
MAX
(Note 11)
UNIT
12.5
MHz
tcSCLK
SCKRx Frequency - SCKR0, SCKR1
twSCLK
SCKRx Pulse Width (High and Low) - SCKR0, SCKR1
40
ns
tsLRCLK
LRCKRx Set-Up to SCLK Rising - LRCKR0, LRCKR1
20
ns
thLRCLK
LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1
20
ns
tsSDI
SDINx Set-Up to SCLK Rising - SDIN0, SDIN1
20
ns
thSDI
SDINx Hold from SCLK Rising - SDIN0, SDIN1
20
ns
tdSDO
SDOUTx Delay from SCLK Falling
20
tcSCLK
ns
twSCLK
SCKRx
thLRCLK
twSCLK
LRCLKRx
tsLRCLK
tsSDI
SDINx
tdSDO
thSDI
SDOUTx
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
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FN7838.3
April 28, 2016
D2-7xx83
Two-Wire (I2C) Interface Port Timing
(Figure 2) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
MIN
(Note 11)
DESCRIPTION
TYPICAL
MAX
(Note 11)
UNIT
100
kHz
fSCL
SCL Frequency
tbuf
Bus Free Time Between Transmissions
4.7
µs
twlowSCLx
SCL Clock Low
4.7
µs
twhighSCLx
SCL Clock High
4.0
µs
tsSTA
Set-Up Time For a (Repeated) Start
4.7
µs
thSTA
Start Condition Hold Time
4.0
µs
thSDAx
SDA Hold From SCL Falling (Note 13)
tsSDAx
SDA Set-Up Time to SCL Rising
tdSDAx
SDA Output Delay Time From SCL Falling (Note 14)
1
µs
250
ns
3.5
µs
tr
Rise Time of Both SDA and SCL (Note 14)
1
µs
tf
Fall Time of Both SDA and SCL (Note 14)
300
ns
tsSTO
Set-Up Time For a Stop Condition
4.7
µs
NOTE:
13. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
14. Limits established by characterization and not production tested.
twhighSCLx
tR
twlowSCLx
tF
SCLx
tsSTA
thSDAx
tsSDAx
tsSTO
tBUF
SDAx (INPUT)
thSTAx
SDAx (OUTPUT)
tdSDAx
FIGURE 2. I2C INTERFACE TIMING
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FN7838.3
April 28, 2016
D2-7xx83
SPI™ Interface Port Timing
(Figure 3) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V.
All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 11)
MAX
(Note 11)
UNIT
-
8
ns
10
-
ns
SPI MASTER MODE TIMING
tV
MOSI Valid From Clock Edge
tS
MISO Set-Up to Clock Edge
tH
MISO Hold From Clock Edge
1 system clock + 2ns
tWI
nSS Minimum Width
3 system clocks + 2ns
SPI SLAVE MODE TIMING
tV
MISO Valid From Clock Edge
3 system clocks + 2ns
tS
MOSI Set-Up to Clock Edge
tH
MOSI Hold From Clock Edge
1 system clock + 2ns
tWI
nSS Minimum Width
3 system clocks + 2ns
10
-
ns
SCK (CPHA = 1, CPOL = 0
SCK (CPHA = 0, CPOL = 0
tV
tV
MOSI
tS
tH
MISO (CPHA = 0
tWI
nSS
FIGURE 3. SPI TIMING
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FN7838.3
April 28, 2016
D2-7xx83
Pin Configuration
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10
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PWMVDD
PWM0
PWM1
PWM2
PWM3
PWMGND
PWMVDD
PWM4
PWM5
PWM6
PWM7
PWMGND
PWMVDD
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWMGND
PWMVDD
PWM14
PWM15
PWM16
PWM17
PWMGND
CVDD
CGND
RGND
RVDD
GPIO1
PROTECT2
PSCURR
PWMSYNC
PROTECT3
PROTECT4
PROTECT5
PROTECT6
PROTECT7
PUMPLO
PSSYNC
PSTEMP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GPIO4
GPIO5
GPIO6
SDA1
SCL1
PROTECT9
SPDIFRX1
SPDIFRX0
SPDIFTX
TEST
IRQA
IRQB
IRQC
IRQD
TIO2
CVDD
CVDD
CGND
CGND
RGND
RVDD
PUMPHI
SC20
SRD2
SC21
SCK2
STD2
SC22
MCLK
SCK3
STD3
SC32
SC30
SC31
SRD3
STD0
SCK0
CVDD
CVDD
CGND
CGND
RGND
RVDD
SRD0
SC00
SC01
SC02
SCK
TIO1
MISO
MOSI
GPIO7
GPIO3
GPIO2
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
SCL0
SDA0
GPIO0
PROTECT0
PROTECT1
TIO0
nRESET
nRSTOUT
SRD1
SCK1
STD1
SC10
SC11
SC12
CVDD
CGND
RGND
RVDD
nSS
nTRST
ADCGND
AIN0
ADCREF
AIN1
ADCVDD
PLLAVDD
XTALO
XTALI
PLLTESTA
PLLTESTB
PLLAGND
OSCOUT
D2-71083, D2-74083, D2-71583, D2-74583, D2-71683, D2MC-72083, D2MC-76083
(128 LD LQFP)
TOP VIEW
FN7838.3
April 28, 2016
D2-7xx83
Pin Descriptions
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
SC20
I/O
3.3
8
Serial Audio Interface 2, I2S0 SCLK
2
SRD2
I/O
3.3
4
Serial Audio Interface 2, I2S0 SDIN
3
SC21
I/O
3.3
8
Serial Audio Interface 2, I2S0 LRCK
4
SCK2
I/O
3.3
8
Serial Audio Interface 2, I2S1 SCLK
5
STD2
I/O
3.3
8
Serial Audio Interface 2, I2S1 SDIN
6
SC22
I/O
3.3
4
Serial Audio Interface 2, I2S1 LRCK
7
MCLK
O
3.3
16
I2S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset
and is enabled by firmware assignment.
8
SCK3
I/O
3.3
8
Serial Audio Interface 3, I2S3 SCLK
9
STD3
I/O
3.3
8
Serial Audio Interface 3, I2S3 SDIN
10
SC32
I/O
3.3
8
Serial Audio Interface 3, I2S3 LRCK
11
SC30
I/O
3.3
8
Serial Audio Interface 3, I2S2 SCLK
12
SC31
I/O
3.3
8
Serial Audio Interface 3, I2S2 LRCK
13
SRD3
I/O
3.3
4
Serial Audio Interface 3, I2S2 SDIN
14
STD0
I/O
3.3
8
Serial Audio Interface 0, I2S SDAT0
15
SCK0
I/O
3.3
8
Serial Audio Interface 0, I2S LRCK0
16
CVDD
P
3.3
Core power, 1.8V
17
CVDD
P
3.3
Core power, 1.8V
18
CGND
P
3.3
Core ground
19
CGND
P
3.3
Core ground
20
RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
21
RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
22
SRD0
I/O
3.3
4
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
23
SC00
I/O
3.3
8
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
24
SC01
I/O
3.3
8
Serial Audio Interface 0, I2S SDAT1
25
SC02
I/O
3.3
8
Serial Audio Interface 0, I2S LRCK1
26
SCK
I/O
3.3
4
SPI clock I/O with hysteresis input.
27
TIO1
I/O
3.3
16
Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
28
MISO
I/O
3.3
4
SPI master input, slave output data signal.
29
MOSI
I/O
3.3
4
SPI master output, slave input data signal.
30
GPIO7
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
31
GPIO3
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
32
GPIO2
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
33
GPIO4
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
PIN
PIN
NAME
(Note 15)
1
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11
DESCRIPTION
FN7838.3
April 28, 2016
D2-7xx83
Pin Descriptions (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
GPIO5
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
35
GPIO6
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
36
SDA1
I/O
3.3
8 - OD
Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers
for data transport.
37
SCL1
I/O
3.3
8 - OD
Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave
controllers for clock signaling.
38
PROTECT9
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
39
SPDIFRX1
I
3.3
-
S/PDIF Digital audio data input 1
40
SPDIFRX0
I
3.3
-
S/PDIF Digital audio data input 0
41
SPDIFTX
O
3.3
4
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent
upon firmware, driving stereo output up to 192kHz.)
42
TEST
I
3.3
-
Factory test use only. Must be tied low.
43
IRQA
I
3.3
-
Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
44
IRQB
I
3.3
-
Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
45
IRQC
I
3.3
-
Interrupt request port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
46
IRQD
I
3.3
-
Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
47
TIO2
I/O
3.3
16
48
CVDD
P
3.3
-
Core power, 1.8V
49
CVDD
P
3.3
-
Core power, 1.8V
50
CGND
P
3.3
-
Core ground
51
CGND
P
3.3
-
Core ground
52
RGND
P
3.3
-
Digital pad ring ground. Internally connected to PWMGND.
53
RVDD
P
3.3
-
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
54
PUMPHI
I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
55
PUMPLO
I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
56
PSSYNC
I/O
3.3
16
Synchronizing output signal to switching power supply. (Operates under specification of
firmware and resets to high impedance inactive state when not used.)
57
PSTEMP
I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
58
PSCURR
I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
59
PWMSYNC
I/O
3.3
16
PWM synchronization port. (Function and operation is defined by firmware.)
60
PROTECT3
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
PIN
PIN
NAME
(Note 15)
34
Submit Document Feedback
12
DESCRIPTION
Timer I/O port 2. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
FN7838.3
April 28, 2016
D2-7xx83
Pin Descriptions (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PROTECT4
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
62
PROTECT5
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
63
PROTECT6
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
64
PROTECT7
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
65
PROTECT2
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
66
GPIO1
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
67
RVDD
P
3.3
-
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
68
RGND
P
3.3
-
Digital pad ring ground. Internally connected to PWMGND.
69
CGND
P
3.3
-
Core ground
70
CVDD
P
3.3
-
Core power, 1.8V
71
PWMGND
P
3.3
-
PWM output pin ground. Internally connected to RGND.
72
PWM17
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
73
PWM16
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
74
PWM15
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
75
PWM14
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
76
PWMVDD
P
3.3
-
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
77
PWMGND
P
3.3
-
PWM output pin ground. Internally connected to RGND.
78
PWM13
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
79
PWM12
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
80
PWM11
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
81
PWM10
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
82
PWM9
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
83
PWM8
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
84
PWMVDD
P
3.3
-
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
85
PWMGND
P
3.3
-
PWM output pin ground. Internally connected to RGND.
86
PWM7
I/O
3.3
8 or 16
PIN
PIN
NAME
(Note 15)
61
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DESCRIPTION
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
FN7838.3
April 28, 2016
D2-7xx83
Pin Descriptions (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
PWM6
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
88
PWM5
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
89
PWM4
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
90
PWMVDD
P
3.3
-
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
91
PWMGND
P
3.3
-
PWM output pin ground. Internally connected to RGND.
92
PWM3
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
93
PWM2
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
94
PWM1
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
95
PWM0
I/O
3.3
8 or 16
PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined
by firmware.)
96
PWMVDD
P
3.3
-
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
97
OSCOUT
P
1.8
-
Analog oscillator output to slave D2-71x83 devices. OSCOUT drives a buffered version of the
crystal oscillator signal from the XTALI pin.
98
PLLAGND
P
1.8
-
PLL Analog ground
99
PLLTESTB
O
1.8
-
Factory test use only. Must be tied low.
100
PLLTESTA
O
1.8
-
Factory test use only. Must be tied low.
101
XTALI
P
1.8
-
Crystal oscillator analog input port. An external clock source would be driven into the this port.
In multi-D2-71x83 systems, the OSCOUT from the master D2-71x83 would drive the XTALI pin.
102
XTALO
P
1.8
-
Crystal oscillator analog output port. When using an external clock source, this pin must be
open. XTALO does not have a drive strength specification.
103
PLLAVDD
P
1.8
-
PLL Analog power, 1.8V
104
ADCVDD
P
3.3
-
Analog power for internal ADC, 3.3V
105
AIN1
I
3.3
-
Analog input 1 to internal ADC
106
ADCREF
O
3.3
-
Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.
107
AIN0
I
3.3
-
Analog input 0 to internal ADC
108
ADCGND
P
3.3
109
nTRST
I
3.3
-
Factory test only. Must be tied high at all times.
110
nSS
I/O
3.3
4
SPI slave select I/O.
111
RVDD
P
3.3
-
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
112
RGND
P
3.3
-
Digital pad ring ground. Internally connected to PWMGND.
113
CGND
P
3.3
-
Core ground
114
CVDD
P
3.3
-
Core power, 1.8V
115
SC12
I/O
3.3
8
Serial Audio Interface 1, LRCK
116
SC11
I/O
3.3
8
Serial Audio Interface 1, SDAT3
PIN
PIN
NAME
(Note 15)
87
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14
DESCRIPTION
Analog ground for internal ADC
FN7838.3
April 28, 2016
D2-7xx83
Pin Descriptions (Continued)
TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
SC10
I/O
3.3
8
Serial Audio Interface 1, data (Assignment by firmware control.)
118
STD1
I/O
3.3
8
Serial Audio Interface 1, SDAT2
119
SCK1
I/O
3.3
8
Serial Audio Interface 1, SCK
120
SRD1
I/O
3.3
4
Serial Audio Interface 1, data (Assignment by firmware control.)
121
nRSTOUT
O
3.3
16 - OD
Active low open drain reset output. Pin drives low from POR generator, 3.3V brown out detector
going active, or from 1.8V brown out detector going active. This output should be used to
initiate a system reset to the nRESET pin upon brownout event detection.
122
nRESET
I
3.3
-
Active low reset input with hysteresis. Activates system level reset when pulled low, initializing
all internal logic and program operations. System latches boot mode selection of the IRQ input
pins on the rising edge.
123
TIO0
I/O
3.3
16
Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
124
PROTECT1
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
125
PROTECT0
I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
126
GPIO0
I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
127
SDA0
I/O
3.3
8 - OD
Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers
for data transport.
128
SCL0
I/O
3.3
8 - OD
Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave
controllers for clock signaling.
PIN
PIN
NAME
(Note 15)
117
DESCRIPTION
NOTES:
15. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix.
16. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins
to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and
PWMGND pins are also internally connected and are to be tied together.
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FN7838.3
April 28, 2016
D2-7xx83
Functional Block Diagram
HD Audio Interface
PROT9
2:1
MUX
SPDIFTX
Amplifier Protection
24-Bit Fixed-Point Digital Signal Processor with 56-Bit MAC
(Typical Signal Processing Blocks Contained Within Firmware Download)
S/PDIF
Rx
PROT7
2:1
MUX
SPDIFRX1
PROT6
SPDIFRX0
PROT5
Stereo
ADC
AIN1
PROT4
AIN0
PROT3
4 Serial Audio Interface Ports
(4 Multifunction Data Type Receivers/Transceivers)
PROT2
PROT1
PROT0
SC32
SC31
SC30
STD3
SCK3
SC22
SC21
SC20
STD2
SAI3 Port
(I2S/TDM/DSD/ADC)
SCK2
SC12
SC11
SC10
STD1
SCK1
SRD1
SC02
SC01
SC00
STD0
SCK0
SRD0
MCLK
SAI2 Port
(I2S/DSD/HDA/TDM)
SRD3
SAI1 Port
(I2S/TDM)
SRD2
SAI0 Port
(I2S/TDM)
12 Channel Pulse Width Modulator
Engine (via 18 Pins of Output)
PWM0
Linear Interpolator
Input Selection
PWM1
Audio Processing
& Virtualization
Algorithms
Firmware-Dependent
(D2Audio SoundSuite™,
rd
3 -Party Enhancements, etc.)
S/PDIF
Rx
Auto Detection
PWM2
PWM3
PWM4
PWM Correction
PWM5
PWM6
DSD Decimator
Engine
PWM7
nRESET
PWM8
Noise Shaper
Compressed Audio Decoders
PWM9
nRSTOUT
PWM10
PUMPHI
PWM11
PUMPLO
Sample Rate
Converters
IC and Audio
System
Control
Interface
PSSYNC
PSTEMP
PSCURR
Post-Processing (Tone Control,
D2Audio DigitalEQ for Speaker
Compensation & Content EQ,
Compressor/Limiter, Individual
Channel Delays)
Mixers / Routers
PWM12
Quantizer
PWM13
PWM14
PWM15
PWMSYNC
IRQ[D:A]
GPIO[7:0]
A/V Sync
4
PWM16
Output Drive
PWM17
8
Test
Timer
Power Supply
SPI Port
MOSI
MISO
SCK
nSS
SDA1
SCL1
SDA0
SCL0
OSCOUT
XTALI
XTALO
TIO0
RGND
TIO1
4
TIO2
4
RVDD
6
CGND
PWMGND
6
CVDD
4
PWMVDD
OSCVDD
ADCGND
ADCVDD
ADCREF
PLLAGND
PLLAVD
nTRST
TEST
4
Dual Port 2-Wire
(I2C-Compatible)
PLL
FIGURE 4. D2-7xx83 IC FUNCTIONAL BLOCK DIAGRAM
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FN7838.3
April 28, 2016
D2-7xx83
Introduction
System Features and Support
The DAE-6 family of ICs provide the core functionality, amplifier
control, and complete audio signal processing for D2Audio’s
Class-D amplifier solutions. A variety of Reference Designs from
Intersil D2Audio Corporation include specific signal flows
designed for their applications, supporting today’s design
features. Support is also provided for future planned features,
with little or no additional hardware or logic to enable new
features. The signal flow, digital audio I/O, and amplifier
hardware control support is handled completely by the DAE-6
firmware.
The DAE-6 enables multiple solutions consisting of a Class-D
amplifier system built around internal audio processing
functional blocks. Features include:
The products are targeted at high-volume Home Theater in a Box
(HTiB), Multimedia, Soundbar, and similar solutions, where rich
features and cost-effective quality audio are required to meeting
demands of current consumer electronics markets.
The DAE-6 devices are completely pin-compatible with the DAE-3
devices, allowing full flexibility for function vs cost trade-off,
providing cost-effective solutions for applications of varying
end-user features and capabilities.
Target Performance
Typical systems built around the DAE-6 support performances
that includes or exceeds:
• >110 dB SNR/Dynamic Range System Support
• <0.06% THD+N at Full Scale at 1kHz
• 20Hz to 20kHz Audio Frequency Response
• Scalable Amplifier Power Control Capability
• Discrete Component and Integrated Power Stages using
Full-Bridge, Half-Bridge, and BTL Output Topologies
• Encrypted Code Loads and Unique Decryption for each IC Part
Number
• Support for all Standard Audio Data Delivery Formats and
Protocols Employed in the Target Markets
• The Delivery Formats Include: I2S, Left-Justified, Time-Division
Multiplexed (TDM), S/PDIF, DSD, HDA, 2-Channel Analog
Application Markets
The powerful DSP coupled with flexible peripherals and excellent
signal processing hardware results in a chip for solutions that
cover many markets. All are characterized by the need for
complex signal processing and high audio channel count. Typical
applications include a wide variety of cost sensitive but
feature-demanding performance such as in:
• Flexible Audio Input and Output Configurations
- 4 Independent Asynchronous I2S Digital Inputs
- Support of 8 Audio Channels of HDMI
- HD Audio (HDA)
- Direct Stream Digital™ (DSD) Input Support
- Integrated high-performance stereo ADC
- Dual Multiplexed S/PDIF™ Digital Audio Inputs
(Linear IEC-61958 PCM or Compressed IEC-61937 Audio)
- S/PDIF Digital Audio PCM Output
- Line-level Outputs (Left, Right, Subwoofer) using passive or
active output filter stages
• Flexible DSP Clock Speed and DSP Memory Capacity Options
- 147.456MHz DSP Clock Speed Devices, with 24k X and Y
Memory and 32k P Memory Capacity
- 159.744MHz DSP Clock Speed Devices, with 24k X and Y
Memory and 32k P Memory Capacity
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL)
Topologies, using Discrete or Integrated Power Stages from
10W to Over 500W
- Graceful Protection and Recovery
- Complete Fault Protection with Automatic Recovery
• Serial Control Interface via I2C, HDA, SPI, or SCI
• Decoding of Compressed Audio Formats, Including
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- AAC™ LC
- DTS® Digital Surround
- DTS® ES
- DTS Neo:6®
• Audio Enhancement Feature Support
- D2Audio™ SoundSuite™ Audio Processing Enhancement
- Mark Levinson MightyCat™ Audio Processing Enhancement
• Multimedia Speaker Solutions
• Multi-Driver (Bi-Amp, Tri-Amp) Speaker Arrays
• Home Theater Systems with Compressed Audio Decoder
• Soundbar System Solutions
• Set-Top Box Solutions
• Low-Cost Virtualized Stereo, 5.1, 7.1, and 9.1 AVR Systems
• MRDA distributed and networked audio systems with multiple
powered channels
• Aftermarket/OEM Automotive Amplifiers
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FN7838.3
April 28, 2016
D2-7xx83
Audio Processing Signal Flow Support
The D2-7xx83-series of ICs supports a wide variety of signal flows
and audio processing options that are fully programmable and
are completely defined by the system firmware and system
architecture.
The firmware provided for the D2-7xx83 devices is
application-specific and includes its own specific signal flow and
associated performance level. Much of the signal flow is also
hardware dependent and that hardware integrates with the full
system architecture that is defined within that system’s
programmed firmware. Each firmware design includes a specific
set of control tool support, including the D2Audio™ Audio
Canvas™ software and system design data.
Additional design-specific reference documentation is included
within each firmware application design, that includes
platform-specific signal flows, control registers, and descriptions
of advanced processing features.
The various system support capabilities include:
• Flexible system configuration with 8 audio input and audio
processing channels, with up to 12 audio output PWM
channels, supporting differential or single-end PWM outputs
with up to 18 PWM output pins.
• Audio processing for up to 4 simultaneous stereo
asynchronous digital audio inputs from a variety of sources
(HDA, I2S, HDMI, DSD, S/PDIF Digital)
• Multiple D2-7xx83 devices may be cascaded to support higher
channel count designs.
Functional Description
The D2-7xx83 Family of ICs, integrated into D2Audio’s offerings
of reference design platforms support present and future design
features with little or no additional hardware or logic to enable
new features.
Audio Input
Multiple versions of the D2-7xx83 family IC-based reference
designs support a wide range of market applications and each of
these market applications has a variety of potential audio
sources such as:
• Mono and Stereo Analog Inputs
• Serial Audio, I2S and Time Division Multiplexed (TDM) Single
Line “Network” Mode
• HD-Audio Interface (UAA-Class Driver Capable)
• Stereo and Multichannel DSD
• S/PDIF Digital (IEC60958-Compliant and IEC61937Compliant)
SERIAL AUDIO INPUT
Since most systems incorporate some mix of digital and analog
inputs, the DAE-6 offers a very flexible digital audio peripheral
interface. The DAE-6 features four independent Serial Audio
Interface (SAI) ports. All SAI ports support both master or slave
clocking and can support sample rates from 32kHz to 192kHz.
Each SAI port supports the digital audio industry I2S standard, which
supports carrying up to 24-bit Linear PCM audio words per subframe
IEC60958, or compressed digital audio (Dolby® Digital, AAC, DTS®,
MPEG, etc.) packing per the IEC61937 specification. The SAI port
also supports Left-Justified formatted Linear PCM or compressed
digital audio. Each SAI port supports time division multiplexing
(TDM) capability (a.k.a. “Network mode”) with up to 32 words per
frame.
SAI ports 2 and 3 (the 3rd and 4th ports) have multiplexed inputs
to provide a standard input signal flow for the ADC, DSD, and
HDA audio interfaces. All serial audio input data streams go
through an SAI interface, which simplifies the data flow
configuration.
SAI data formats are shown in Figure 5. For I2S format, the left
channel data is read when LRCK is low. For the Left-Justified
format, the left channel data is read when LRCK is high. Either
format requires data to be valid on the rising edge of SCLK and
sent MSB-first on SDIN with 32 bits of data per channel. Each set
of digital inputs runs asynchronously to the others and may
accept different sample rates and formats.
Left Channel
LRCLKx
Right Channel
SCLKx
Serial
Data
MSB
-1
-2
+3
-3
+2
+1
LSB
MSB
-1
-2
-3
+3
+2
+1
LSB
MSB
I2S Format
LRCLKx
Right Channel
Left Channel
SCLKx
Serial
Data
MSB
-1
-2
-3
-4
+3
+2
+1
LSB
MSB
-1
-2
-3
-4
+3
+2
+1
LSB
MSB
-1
Left-Justified
FIGURE 5. SAI PORT SUPPORTED DATA FORMATS FOR DELIVERY OF LINEAR PCM OR COMPRESSED AUDIO DATA
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FN7838.3
April 28, 2016
D2-7xx83
S/PDIF RECEIVER
ADC INPUT
The D2-7xx83 contains two input pins internally multiplexed into
one IEC60958 compliant S/PDIF Digital receiver. The receiver
input pins are 3.3V CMOS input level compatible, requiring
external circuitry to condition the serial input. The receiver
contains an input transition detector, digital PLL clock recovery,
and a decoder to separate audio, channel status, and user data.
Only the first 24-Channel status bits are supported. The receiver
constantly monitors the incoming data stream to detect the
IEC61937-1 packet headers, and if found, captures the Pc and
Pd data words into registers. The receiver meets the jitter
tolerance specified in IEC60958-4.
The D2-7xx83 contains a high-performance Analog-to-Digital
Converter (ADC) that connects to input analog sources with a
minimum of interface circuitry. At a bandwidth of 20kHz at
nominal voltage and temperature, the ADC input of the DAE-6
provides a typical THD+N (unweighted) value of -81dB and an
SNR/Dynamic Range of 94dB.
S/PDIF is a commonly used interface for receiving compressed
(IEC61937-compliant) and stereo PCM (IEC60958-compliant)
audio data. This interface also supports receipt of compressed
audio data that is not compliant with the IEC61937 specification,
but instead meets the IEC60958 specification.
0
The ADC master clock can be supplied from either the low jitter
PLL of the D2-7xx83, or from the HD Audio interface. When the
PLL provides the ADC master clock, the ADC operates
synchronous to the DSP processing, which minimizes noise
pickup. When operated from the HD Audio clock system, the ADC
decimator output is synchronous to the HDA frame rate,
eliminating the need for sample rate conversion to the HDA
frame rate. Figure 6 shows the ADC decimator frequency
response over full bandwidth and passband, and Figure 7 shows
the ADC performance with full scale input processed through the
SRC to a 48kHz sample rate.
0.020
24 BITS
SPEC
24 BITS
SPEC
0.015
0.010
LEVEL (dB)
LEVEL (dB)
50
100
0.005
0
-0.005
-0.010
-0.015
150
0
0.5
1.0
1.5
2.0
FREQUENCY (Hz)
2.5
3.0
-0.020
0
0.5
1.0
1.5
2.0
FREQUENCY (Hz)
x106
2.5
3.0
x104
FIGURE 6. ADC DECIMATOR FREQUENCY RESPONSE (256 TAPS DECIMATE BY 32)
0
fs = 6.144MHz
Ch0 INPUT = 1kHz AT 1VP-P
THD + N = -81dB SNR = 94dB
MAGNITUDE (dB)
-20
-40
-60
-80
-100
-120
-140
0
5k
10k
FREQUENCY (Hz)
15k
20k
FIGURE 7. ADC PERFORMANCE AT FULL SCALE INPUT
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FN7838.3
April 28, 2016
D2-7xx83
DSD
The HDMI specification (version 1.2 and later) used in TV systems
supports streaming DSD encoded audio over HDMI. To support
this, the system can receive and process up to 6 DSD audio
streams. The DSD interface supports both standard and
phase-modulated data formats. A high-quality 16x decimator
engine converts all of the DSD data streams into 24-bit PCM
words with an FS of 176.4kHz using a 128-tap FIR filter. The DSD
decimation filter has a cutoff frequency of 50kHz and is
optimized for passband flatness.
SAI ports 2 and 3 support DSD format inputs. When the DSD
interface is enabled, all the pins of SAI 2 and the SC21 pin of
SAI3 become the DSD input signals. The 6 channels of DSD
audio are merged into 3 I2S PCM streams at a 176.4kHz sample
rate. These I2S streams are routed into both receivers on SAI 2
and the first receiver of SAI 3. The data is then passed to the
Sample Rate Converter (SRC). The SRC will rate-lock to the DSD
input clock and attenuate any jitter in the DSD input stream.
The DSD input processing clusters the DSD data into channel
pairs. This allows a flexible channel count of 2, 4, or all 6 DSD
data streams to be handled. Using 4-channel DSD frees the SAI 3
port for other uses. Similarly, using only 2-Channel DSD frees the
second SAI 2 port and the SAI 3 port for other uses.
The D2-7xx83 family of ICs also offers digital audio format
conversion support for DSD stereo format input to S/PDIF or I2S
format output, as well as DSD multichannel format input to
multiple I2S format output. This high-quality digital audio format
conversion path also offers the ability to reduce clock jitter in the
audio system introduced by certain transmission paths such as
HDMI.
This technique also enables consumer products to output a
downsampled and/or downmixed (if necessary) digital audio
output for audio that may not otherwise be made available to the
consumer in the original higher-bandwidth format due to certain
consumer electronic/content protection licensing restrictions.
The graphs in Figure 8 show the DSD decimation filter frequency
response at 2 different frequency zoom levels.
0.020
0
24 BITS
SPEC
24 BITS
SPEC
0.015
0.010
LEVEL (dB)
LEVEL (dB)
-50
-100
0.005
0
-0.005
-0.010
-0.015
-150
0
2
4
6
8
FREQUENCY (Hz)
10
12
14
x105
-0.020
0
0.5
1.0
1.5
2.0
FREQUENCY (Hz)
2.5
3.0
x 104
FIGURE 8. DSD DECIMATOR FREQUENCY RESPONSE (128 TAPS DECIMATE BY 16)
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FN7838.3
April 28, 2016
D2-7xx83
Audio Output
PWM AUDIO AMPLIFIER OUTPUT
The D2-7xx83 family supports multiple PWM output topologies,
which enables system designs to use an output stage, which
meets the cost and performance requirements of the particular
application. Twelve PWM channels are mapped to 18 PWM
output pins by the programmed firmware. The PWM output pins
are 3.3V CMOS levels with either 8mA or 16mA drive capability.
Output topologies supported include:
• Half-bridge, N+N or N+P
• Full-bridge, N+N or N+P using 2-level modulation, 2 or
4-quadrant control
LINE LEVEL OUTPUT
In addition to amplified outputs, the D2-7xx83 family IC also
supports line-level outputs that generate a nominal 1VRMS
output using a simple passive filter.
PCM audio bitstream via a specified SAI port, or S/PDIF Digital
transmitter. In addition, depending on the firmware functionality,
it is possible for unused SAI (Serial Audio Interfaces) to also
support I2S output as well, in either slave or master mode. The
output audio sample rate is determined by the firmware and can
vary from 32kHz up to 192kHz.
HD Audio
HDA INTERFACE
The HD Audio interface also provides a control interface. This
control interface uses the HD Audio GPI, GPO, and GPIO 8-bit
ports to provide a message passing facility between the
D2-7xx83 and the PC.
The D2-7xx83 fully supports Windows® Hardware Quality Labs
(WHQL™)-certification as, it is a UAA-Compliant Secondary HD
Audio CODEC. The devices may be used either as the primary
HDA CODEC, or as the second HDA CODEC in the system.
Features supported are:
Headphone outputs or line-level outputs that require a 2VRMS (or
higher output level) are also supported, using an active filter to
accomplish the signal level needs.
• Message passing to other devices located on the motherboard
(e.g. HP jack detection and reporting.)
S/PDIF TRANSMITTER
• Amplifier code load during system boot.
The D2-7xx83 contains one IEC60958 compatible S/PDIF Digital
transmitter. The transmitter complies with the consumer
applications defined in IEC60958-3. The transmitter supports
24-bit audio data, 24-bit user data, and 30-bit channel status
data.
• Amplifier control protocol (D2Audio Canvas II support).
A bit-exact pass-through mode from the selected SPDIFRX[1:0]
input is also supported. This simplifies system designs that
require that the IEC61937-compliant original compressed audio
bitstream be made available at the back panel of the product, as
well as giving the user the capability to select a decoded (and
downmixed, if necessary) IEC60958-compliant stereo or mono
Linear PCM output for digital audio recording/playback
capabilities.
The D2-7xx83 family optional firmware offers digital audio
format conversion support for I2S Digital format input to S/PDIF
Digital format output, as well as S/PDIF Digital format input to
I2S Digital format output, for all digital audio Linear PCM
(non-compressed) audio sources. This functionality is not
available for compressed audio inputs, unless the compressed
audio data is first decoded by the internal DSP, and if necessary,
downmixed to 2 channels.
• Amplifier firmware download.
HD AUDIO PLAY
The D2-7xx83 provides for direct connection of a PC’s HD Audio
(HDA) Controller to the device. In this configuration, the
D2-7xx83 functions as an HDA CODEC with powered (amplified)
outputs.
Supported Features Include:
• 2, 4, 6, or 8 Amplified or PWM DAC Channels
• Audio Sample Rates 48kHz, 96kHz, 192kHz
• Data Widths of 16-bit, 20-bit, and 24-bit
• Independent Channel Gain Control
The HDA interface uses 5 of the 6 pins of the SAI 3 port. The HDA
interface captures the audio streams and converts them into one
to four I2S data streams, depending on the number of channels
used. These I2S stereo streams are routed through SAI 3 and SAI
4 and then on to the Sample Rate Converter. The SRC will rate
lock to the HDA stream and remove any jitter while converting
the data to the output sample rate.
This format conversion path offers the ability to reduce the clock
jitter on the output due to the fact that both inputs (when in this
mode) pass through the professional-grade Sample-Rate Converters
(SRC). This approach also enables consumer products to output a
downsampled digital audio output for audio that may not otherwise
be made available to the consumer in the original higher-bandwidth
format due to certain consumer electronic/content protection
licensing restrictions.
SERIAL AUDIO OUTPUT
D2-7xx83 family IC-based systems support outputting a bit-exact
pass-through of a compressed audio bitstream, or a decoded,
down-mixed (Lt/Rt or Lo/Ro) and downsampled 2 channel Linear
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21
FN7838.3
April 28, 2016
D2-7xx83
HD AUDIO FUNCTIONS AND FUNCTION TYPES
TABLE 2.
FUNCTION
FUNCTION TYPE
NODE ID
Function Group
01
Parent of all other nodes, also holds GPIO functions
Front L/R DAC
Stereo DAC
02
To Front L/R Mixer
Center/LFE DAC
Stereo DAC
03
To Center/LFE Mixer
Surround L/R DAC
Stereo DAC
04
To Surround L/R Mixer
Side Surround L/R DAC
Stereo DAC
05
To Side Surround Mixer
Front L/R Mixer
Sum/Mixer Node
06
To Front L/R Pin
Center/LFE Mixer
Sum/Mixer Node
07
To Center/LFE Pin
Surround L/R Mixer
Sum/Mixer Node
08
To Surround L/R Pin
Side Surround L/R Mixer
Sum/Mixer Node
09
To Side Surround L/R Pin
Front L/R Output Pin
Pin Complex
0A
To system per configuration default register
Center/LFE Output Pin
Pin Complex
0B
To system per configuration default register
Surround L/R Output Pin
Pin Complex
0C
To system per configuration default register
Side Surround L/R Output Pin
Pin Complex
0D
To system per configuration default register
Audio Function Group
CONNECTIONS
HD AUDIO VERBS SUPPORTED
TABLE 3.
WIDGET NID
VERB FUNCTION
GET CODE
SET CODE
Converter Format
A
2
Gain/Mute
B
3
Processing Coefficient
C
4
Coefficient Index
D
5
Get Parameter
F00
Connection Select
F01
Get Connection List
F02
Processing
F03
SDI Select
F04
704
Power State
F05
705
Channel/Stream ID
F06
706
Pin Widget
F07
707
Unsolicited Response
F08
708
Pin Sense
F09
709
Beep
F0A
70A
EAPD/BTL
F0C
70C
Digital Converter
F0D
70D - 70E
Volume Knob
F0F
70F
F10 - F1A
710 - 71A
Config Default
F1C
71C - 71F
Subsystem ID
F20
720 - 723
GPI
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22
01
02 - 05
06 - 09
0A - 0D
Y
Y
Y
Y
Y
Y
Y
Y
701
Y
Y
Y
Y
Y
Y
Y
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April 28, 2016
D2-7xx83
TABLE 3. (Continued)
WIDGET NID
VERB FUNCTION
Stripe
GET CODE
SET CODE
F24
724
Reset
01
7FF
02 - 05
06 - 09
0A - 0D
Y
HD AUDIO WIDGET REQUIRED PARAMETERS
TABLE 4. VERB ID - 0xF00; PARAMETERS 0x9 - 0xD
WIDGET CAP.
PCM SIZE RATE
FORMAT
PIN CAP.
INPUT AMP CAP.
PID 0x9
PID 0xA
PID 0xB
PID 0xC
PID 0xD
Y
Y
NODE ID
FUNCTION
01
Function
02
DAC
Y
Y
Y
03
DAC
Y
Y
Y
04
DAC
Y
Y
Y
05
DAC
Y
Y
Y
06
Mixer
Y
Y
07
Mixer
Y
Y
08
Mixer
Y
Y
09
Mixer
Y
Y
0A
Pin
Y
Y
0B
Pin
Y
Y
0C
Pin
Y
Y
0D
Pin
Y
Y
TABLE 5. VERB ID - 0xF00; PARAMETERS 0xE - 0x13
CONNECT LIST
LENGTH
POWER STATES
PROCESS CAP.
OUTPUT AMP
CAP.
VOLUME KNOB
PID 0xE
PID 0xF
PID 0x10
PID 0x12
PID 0x13
NODE ID
FUNCTION
01
Function
02
DAC
03
DAC
04
DAC
05
DAC
06
Mixer
Y
Y
07
Mixer
Y
Y
08
Mixer
Y
Y
09
Mixer
Y
Y
0A
Pin
Y
Y
0B
Pin
Y
Y
0C
Pin
Y
Y
0D
Pin
Y
Y
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23
Y
FN7838.3
April 28, 2016
D2-7xx83
HD AUDIO SYSTEM TOPOLOGY
Front L/R
DAC
NID 02
Center / LFE
DAC
NID 03
Front L/R
Mixer
(Gain Control)
Front L/R
Pin Complex
(Mute Control)
NID 06
Center / LFE
Mixer
(Gain Control)
NID 0A
Center / LFE
Pin Complex
(Mute Control)
NID 07
NID 0B
HDA Link
Interface
Surround L/R
DAC
NID 04
Side Surr L/R
DAC
NID 05
Surround L/R
Mixer
(Gain Control)
Surround L/R
Pin Complex
(Mute Control)
NID 08
Side Surr L/R
Mixer
(Gain Control)
NID 0C
Side Surr L/R
Pin Complex
(Mute Control)
NID 09
NID 0D
FIGURE 9. HD AUDIO SYSTEM TOPOLOGY
Sample Rate Converters (SRC)
D2-7xx83 family ICs support internal asynchronous sample rate
conversion to align input audio streams to a single rate
compatible with the DSP processing rate and PWM switch rate.
D2-7xx83 device family has 4 independent rate estimators,
allowing up to 4 asynchronous stereo inputs (8 channels) to be
sample rate converted and processed simultaneously. The
sample rate converter has a measured SNR that exceeds 140dB
and a THD+N that exceeds -125dB.
The PLL block contains the following components:
• Low noise crystal oscillator
• Low jitter PLL clock multiplier
• Power on reset generator
• Brown out detectors on the CVDD and RVDD supplies
• System reset generation logic
DSP
The majority of the D2-7xx83 audio processing functions as well
as system control occur within the DSP core. The core is a 24-bit
fixed-point Digital Signal Processor, tightly integrated with its
own DMA, interrupt control, memory, and control interfaces.
Software configurable processing blocks and signal routings are
implemented within the DSP, allowing a wide range of
functionality and system implementations through the
programmed definitions that are read into memory upon device
initialization. Signal flows through the device are buffered and
processed through hardware specific-function blocks (such as
the Sample Rate Converter) and allow considerable overall signal
processing capability through interface to the DSP.
Clocks And PLL
The clock generation contains a low jitter PLL critical for low
noise PWM output and a precise master clock source for the
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ADC, sample rate conversion, and the audio data paths. The
serial audio interfaces can function as either a master or a slave.
24
• Clock generators for the DSP, S/PDIF transmitter, ADC, and
MCLK output pin
The PLL block is completely managed by the system firmware.
The system clock is provided by the crystal oscillator block, using
either a fundamental mode crystal or a clock input to the XTALI
pin. If the clock input is used, it must be a 1.8V signal level. The
input signal on the XTALI pin is analog buffered and driven onto
the OSCOUT pin for use in driving the XTALI input of other
D2-7xx83 controllers.
The PLL uses the signal on the XTALI pin as the reference clock.
The reference clock frequency is multiplied by an integer
multiple of 4 to 15 to get the PLL output clock. The PLL output is
used to time the PWM outputs and to generate the DSP clock.
During system start-up, before the PLL has been configured and
locked, the PLL is bypassed and the system operates at XTALI
speed.
FN7838.3
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D2-7xx83
The power on reset circuit senses the rise of the PLLVDD supply.
When the supply reaches the sense threshold, the power on reset
pulse is generated. If the PLLVDD supply droops below the sense
threshold, the reset pulse will occur when the supply rises above
the threshold. The power on reset signal will drive the nRSTOUT
output pin low.
The two power supply brown out detectors monitor the CVDD and
PWMVDD power rails. If the power rail droops below the
threshold, the brown out detector will activate and drive the
nRSTOUT output pin low.
The system reset generation logic is activated by a low level on
the nRESET input pin or by the power on reset sensor pulse. Upon
de-assertion of nRESET a sequential counter ensures sufficient
time and clock cycle count for the internal synchronous logic to
reset.
Multiple D2-7xx83 ICs are capable of running on a common
timebase. Multiple D2-7xx83 ICs synchronize themselves onto a
single crystal oscillator so that all ICs run at identical
frequencies.
DSP CLOCK SPEED AND MEMORY CAPACITY SUPPORT
The D2-7xx83 devices are offered in part number-specific
devices that support multiple DSP clock speeds and memory
capacity. Depending on the device part number, the D2-7xx83
operates up to clock rates of 147.456MHz or 159.744MHz, and
offers memory capacity of 24k/24k/32k or 40k/40k, 56k of
X/Y/P memory space.
The higher speed and larger memory devices support designs
requiring higher processing capacity, while the lower speed
devices provide cost optimization to systems not requiring the
additional audio processing and decode capability.
Refer to “DAE-6 Device Feature Set Offering” on page 3 for the
device part numbers and definitions of clock speed and memory
capacity.
Hardware I/O Functions
The D2-7xx83 provides programmable I/O pins used for various
hardware functions of the system design. Pin functions are
defined by the product firmware, and may be different from one
design to another.
GENERAL-PURPOSE (GPIO) I/O PINS,
POWER SUPPLY SYNCHRONIZATION
The PSSYNC pin provides a power supply synchronization signal
for switching power supplies. Firmware configures PSSYNC to the
frequency and duty cycle needed by the system switching
regulator. The proper configuration eliminates audio output tones
generated if the switching power supply is not locked to the
amplifier switching.
POWER SUPPLY ANTI-PUMP
D2-7xx83 supports designs to correct for power supply pumping
that occurs in half-bridge output stage topologies. The PUMPHI
and PUMPLO pins provide a differential PWM signal pair that
drive an anti-pump correction stage. The dead time and duty
cycle are adjustable to eliminate the power supply DC offset.
Amplifier Protection
The D2-7xx83 supports individual PWM channel protection
through individual protection input pins. These PROTECT pins are
primarily intended for protecting the PWM powered output
stages. The protection inputs are activated by either a pulse or
level driven into the pin. Firmware configures the input
processing logic to properly interpret the input signal as rising
edge triggered, falling edge triggered, high level, or low level.
The protection input signal is generated by specialized sensing
circuits. There are several kinds of sensing circuits for detecting
current, temperature, or voltage. A powered PWM output stage or
a power supply pump driver typically uses an overcurrent sensor.
This sensor will detect power FET current, load current, or both.
These circuits are unique to the specific power stage design, and
may be embedded inside an integrated power stage.
Temperature and voltage sensing are accomplished in a variety
of ways and usually create a DC level representing a fault
condition.
D2-7xx83 designs incorporate a variety of protection strategies to
prevent damage from the high voltages, currents, and
temperatures present in class-D amplifier designs. This
protection is also effective against user-induced faults, such as
clipping, output overload, or output shorts, including both shorted
outputs or short-to-ground faults.
The D2-92xx IC works in conjunction with specific surrounding
parts to provide continuous system monitoring for destructive
events. These events include:
Eight dedicated General Purpose I/O (GPIO) pins are available for
system use. These are controlled only by the D2-7xx83 device
family firmware.
• Output Overcurrent
TIMERS
• Power Supply Brown Out
A timer block consisting of 3 separate general purpose timers
provides programmed control of event or count down timing
functions. The timer functions are controlled through the
firmware, where these timers can operate as timed pulse
generators, as pulse-width modulators, or as event counters to
capture an event or to measure the width or period of a
connected signal. These timers are connected to the 3 timer pins
(TIO[0:2]), which are also assignable as I/O by firmware.
• Shoot Through Overcurrent
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25
• Output Short Circuit
• Over-Temperature (Thermal Event)
Protection features and their details are firmware application
dependent.
Firmware functions running on the D2-7xx83 can be assigned to
observe the temperature at critical points in the hardware and
automatically respond to excessive temperature. Depending on
the specific implementation, this response can be as simple as
turning on an optional fan to reduce temperature, or managing
the audio signal to reduce power consumption.
FN7838.3
April 28, 2016
D2-7xx83
GRACEFUL OVERCURRENT AND SHORT CIRCUIT
Overcurrent sensing requires a current sensor in the power
device to be protected, usually a powered PWM output. The
typical sensor creates a pulse that is active when the current
exceeds a specified threshold.
The D2-7xx83 IC observes the overcurrent protection inputs and
provides graceful protection for the output stage. The hardware is
configured to provide immediate current reduction, cycle-by-cycle
output clipping, output signal control, and output stage
deactivation depending on the severity and duration of high
current events. The combination of hardware features and
firmware monitoring allows the system to differentiate between
an overcurrent situation or a more serious short circuit condition.
At the de-assertion of nRESET, the chip will capture the boot
mode selection and begin the boot process.
Booting and Boot Modes
CODE INITIALIZATION AND BOOT MODES
D2-7xx83 includes a fully-programmable DSP with internal boot
ROM. The boot ROM’s primary function is to download a
second-stage boot image from one of several possible peripheral
sources:
• I2C Interface EEPROM
THERMAL PROTECTION
The D2-7xx83 IC can connect to an optional low-cost thermal
sensing circuit and monitor temperatures in the system.
Firmware monitoring can record the system temperature and
provide system responses including enabling a fan and
managing the audio output signal.
Device Operation
RESET AND INITIALIZATION
The D2-7xx83 must be reset after power up to begin proper
operation, and in normal system hardware configurations, the
reset occurs automatically via the reset hardware circuitry. The
chip contains power rail sensors, brown out detectors, on the 3.3V
and 1.8V power supplies. These brown out sensors will assert and
hold an internal Power-on Reset, which will disable the device until
the power supplies are at a safe level for the DSP to start. These
same brownout sensors will detect a power supply voltage droop
while the system is active and provide a safe amplifier shutdown.
POWER SEQUENCING
The CVDD and RVDD (including PWMVDD) supplies should be
brought up together to avoid high current transients that could
fold back a power supply regulator. The ADCVDD and PLLVDD
may be brought up separately. Best practice would be for all
supplies to feed from regulators with a common power source.
Typically this can be achieved by using a single 5V power source
and regulating the 3.3V and 1.8V supplies from that 5V source.
RESET
D2-7xx83 has one reset input: the nRESET pin. The nRESET input
pin (active low, non-reset high) is effectively a power-on system
reset. All internal state logic, except internal test hardware, is
initialized by nRESET. While reset is active the system is held in
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the reset condition. The reset condition is defined as all internal
reset signals being active, the crystal oscillator is running, and
the PLL disabled.
26
• I2C Interface Slave
• SPI ROM
• SPI Interface Slave
• HDA Bus
The specific boot mode is selected based on the state of the
IRQD, IRQC, IRQB, and IRQA pins at the time of reset
de-assertion. The boot ROM code has been designed to handle
both encrypted and non-encrypted boot images from any of the
above storage locations. Boot modes are shown in Table 6 on
page 27.
The system requires external firmware to boot the internal DSP.
Internal ROM within the DAE-6 initiates the boot process to read
the boot records and firmware, to load into the internal DAE-6
memory.
There are multiple boot modes provided on the DAE-6 devices, as
shown in Table 6. The mode is selected by a hardware pull-up or
pull-down connection to each of the four boot mode (IRQ[D:A])
pins. (Modes not listed are reserved.) Boot sources include:
• I2C EEPROM
• SPI EEPROM or SPI Flash
• I2C Slave (to external Microcontroller)
• SPI Slave (to external Microcontroller)
• Asynchronous UART (RS-232 for PC Communication Mode as
well as D2-7xx83 Device to Device Communication Mode)
• HD Audio Bus
• Combo Mode with I2C EEPROM or SPI
FN7838.3
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D2-7xx83
TABLE 6. BOOT MODES
MODE
0
IRQ[D:A]
0000
M/S
S
XTALI RANGE
N/A
INTERFACE
SPEED
per Master
DESCRIPTION
USAGE
I2C port 1 slave boot at address 88
System
Combo Master - ROM On I2C port 0 or SPI
System
ROM On SPI (EE or FLASH)
(Copy of Mode 1 for pin compatibility)
System
SPI slave boot
System
1
0001
M
24.576 MHz
400kb/s
(See Note 17)
2
0010
M
24.576MHz
1.53MHz
3
0011
S
N/A
per Master
7
0111
S
24.576MHz
384kb/s
Fast Asynchronous SCI boot
Multi-IC
B
1011
S
24.576 MHz
9600 b/s
Asynchronous SCI interface boot (RS232
Compatible)
System
C
1100
M
24.576MHz
1.53MHz
(See Note 17)
HDA enabled, Combo Master - ROM on SPI (EE or
FLASH)
System
D
1101
M
24.576MHz
400kb/s
Copy of mode C for pin compatibility
System
E
1110
M
24.576MHz
per Master
HDA boot
System
F
1111
M
24.576 MHz
400Kb/s
2 wire ROM on GPIO port (SCL= GPIO1,SDA = GPIO0)
System/
Failsafe
NOTE:
17. For the “per Master” and “N/A” entries above, there is a maximum transfer rate that is a fraction of XTALI speed. This maximum transfer rate is
peripheral port specific.
APPLICATION FIRMWARE LOAD
MULTI-CONTROLLER IC COMMUNICATION
The application firmware is loaded either by the boot code or by a
multi-step process. Direct boot code loading occurs when the
selected boot mode successfully finds a boot image on the
expected peripheral interface and the image is successfully
loaded in memory. A multi-step boot is one in which the boot
code loads a program that manages the system boot.
The D2-7xx83 IC is capable of communicating and synchronizing
data and control information across multiple D2-7xx83 ICs. This
communication is to facilitate matrix mixing of all input channels
in a system and to allow precise phase alignment of the output
audio. Systems designs are capable of achieving outputs phase
aligned to within 1/2 sample at 192kHz. One D2-7xx83 IC acts
as the timing master, so all other D2-7xx83 ICs must then
operate as timing slaves. The setting of the each of the D2-7xx83
ICs is system-configuration specific and is detailed in the specific
RDP documentation.
Control Interfaces
I2C 2-WIRE INTERFACE
The D2-7xx83 family IC has two separate I2C 2-Wire compatible
ports. One is typically used for the external microcontroller
interface, and the other for D2-7xx83 family IC communication to
EEPROMs, or other compatible peripheral chips. Both I2C
interfaces are multi-master capable.
Registers are accessed through the I2C control interface. Since
the I2C bus has multiple slaves, the desired I2C target device
must be addressed. The specific I2C channel control address is
defined within the firmware that is loaded into the DAE-6 at boot
and initialization time. Typical addresses used in various
reference designs use the address of 0xB2, but the actual
address should be confirmed based on the firmware design
being used in the application.
SERIAL PERIPHERAL INTERFACE (SPI™)
The Serial Peripheral Interface (SPI) is an alternate serial
interface to the I2C interfaces. As a master, this interface
supports port extenders, EEPROMs, Flash, and various control
interfaces for more complex chips. As a slave, this provides an
alternate method for customers to communicate with the
system.
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27
AUDIO SYNCHRONIZATION
Multiple D2-7xx83 ICs can be connected together and synchronized
for controlling events to meet phase alignment requirements.
Control Protocols provide for an external device communication
with the D2-7xx83 firmware while the amplifier is running. The
D2-7xx83 firmware has a peripheral device driver that
establishes communication with the external controller device.
The D2-7xx83 is always a slave. Communication can occur
through the HDA, I2C, and SPI ports. However control is provided
through only the I2C, and HDA ports, and control through the SPI
port is not supported.
CONTROL REGISTER SUMMARY
The control register interface provides a mechanism for an
external controller to manipulate the amplifier signal flow, and
provides access to the internal registers.
Each system design has its own firmware-dependent register
Application Programming Interface (API) and its own unique
signal flow. The control register definitions, bit fields, and data
format for each register are specified in that firmware API.
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D2-7xx83
READING AND WRITING CONTROL REGISTERS
by the device address with the write bit set, and three register
address bytes. Next, the master must send a repeated Start,
following with the device address with the read/write bit set to
read, and then read the next three data bytes. The master must
Acknowledge (ACK) the first two read bytes and send a Not
Acknowledge (NACK) on the third byte received and a Stop
condition to complete the transaction. The device's control
interface acknowledges each byte by pulling SDA low on the bit
immediately following each write byte. The device read function,
as shown in Figure 11, executes the following 11 steps as the I2C
bus master:
Registers and memory spaces are defined within the DAE-6
firmware for specific internal operation and control. In typical
reference designs, the highest-order byte of the register address
(bits 23:16) determines the internal address space used for
control read or write access, and the remaining 16 bits (bits
15:0) describe the actual address within that space. Refer to the
descriptions of the actual reference design firmware being used
in the application for specific definitions.
All reads or writes to registers (shown in Figures 10 and 11)
begin with a Start Condition, followed by the Device Address byte,
three Register Address bytes, three Data bytes and a Stop
Condition.
1. I2C START command
2. Transmit device I2C address with W
3. Transmit mode byte
Register writes through the I2C interface are initiated by setting
the read/write bit that is within the device address byte. The
device write function as, shown in Figure 10, executes the
following 9 steps as the I2C bus master:
4. Transmit upper memory address byte
5. Transmit lower memory address byte
6. Repeat START command
1. I2C START command
7. Transmit device I2C address with R
2. Transmit device I2C address with W
8. Receive data upper byte
3. Transmit mode byte
9. Receive data middle byte
4. Transmit upper memory address byte
10. Receive data lower byte
5. Transmit lower memory address byte
11. I2C STOP command or NACK
6. Transmit data upper byte
7. Transmit data middle byte
8. Transmit data lower byte
9. I2C STOP command
All reads to registers require two steps. First, the master must
send a dummy write, which consists of sending a Start, followed
ACK
DEVICE-ADDR
ACK
ACK
REGISTER [23:16]
START
REGISTER [15:8]
REGISTER [7:0]
R/W
ACK
Write Sequence
REGISTER [7:0]
ACK
DATA [23:16]
ACK
DATA [15:8]
ACK
DATA [7:0]
STOP
FIGURE 10. I2C WRITE SEQUENCE OPERATION
Step 1
ACK
DEVICE-ADDR
REGISTER [23:16]
START
Read Sequence
ACK
ACK
REGISTER [15:8]
R/W
ACK
MASTER
ACK
ACK
DEVICE-ADDR
REPEAT
START
REGISTER [7:0]
DATA [23:16]
MASTER
ACK
DATA [15:8]
R/W
ACK
REPEAT
START
NACK
DATA [7:0]
STOP
Step 2
FIGURE 11. I2C READ SEQUENCE OPERATION
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28
FN7838.3
April 28, 2016
D2-7xx83
Audio Processing Functions
Input Source Selection
Each system design has its own firmware-dependent signal flow.
This signal flow may be generic, or specifically designed for a
particular amplifier application and consists of input elements
connected to various signal processing blocks, routing the audio
data to an output element. The input elements consist of chip
peripherals used for audio input (I2S input, S/PDIF Digital
receiver, and ADC). The output elements include the chip I2S
output, S/PDIF Digital transmitter, and PWM outputs.
A source selection register specifies the action of a signal
multiplexer, which will implement a simple switching function.
The selected input will be routed to the block output unaltered.
All non-selected inputs will be ignored. Selections typically
include I2S inputs, S/PDIF Digital inputs, HD Audio inputs, and
ADC inputs.
Typical audio processing blocks include gain stages, mixers, tone
controls, compressors, limiters, equalizers, routers, loudness
contour, crossover filters, delays, as well as audio enhancement
features provided within the specific application firmware.
The input and output elements are configured by the firmware
application and the scope of I/O selection is generally specific to
the hardware of the particular application.
The signal processing blocks contain one or more parameters
that define the signal transfer characteristic of the block and a
mechanism for choosing the source and destination data
locations. The signal flow is created by connecting together the
signal processing blocks in the proper order to achieve the
overall system audio processing function.
Firmware Functions
D2-7xx83 IC contains a DSP supporting powerful audio
processing algorithms. Some of the standard audio algorithms
that are typically supported in all firmware loads. Other
algorithms are specific system design and firmware load
dependent.
Master Volume
A master volume function alters the level on all channels
simultaneously by applying the same gain/attenuation function
to each. A single parameter controls all channels.
Channel Attenuation
A channel attenuation function alters the level of a single
channel. A single parameter is provided for each channel.
Equalization
An equalization processing block consists of a single input and
output, and is characterized by how many frequency bands are
supported. Typical equalizers have 3-bands or 5-bands, although
multiple combinations are directly supported. Each frequency
band has 3 parameters - the center frequency, the filter Q, and
the filter gain.
Tone Control
Tone control provide simple bass and treble processing to the
audio signal. Each tone processing block includes two first-order
(6dB/octave) shelving filters, one each for bass and treble. Filters
include programmable corner frequency and gain settings.
Additional features support multiple system capabilities such as:
Excursion Control
• Automatic power-on amplifier calibration
Excursion processing provides dynamic control of the subwoofer
response. Three audio processing control adjustments are
provided for frequency settings, and three adjustments are
provided for Q parameter settings.
• Parameter control and status reporting
• Integrated power supply control and clock synchronization
• Automatic power supply high-voltage rail anti-pump control
• Automatic negative rail generation and bring-up control (for
select half-bridge designs where a ± rail is not already
supplied)
• Automatic cycle-by-cycle temperature sensing and system
response
• Automatic cycle-by-cycle current sensing and system response
• Input audio signal sensing and pop-free power-on/off via
D2Audio’s patented “Green Mode” algorithm with adjustable
threshold
• Dynamic adjustment of efficiency vs. distortion vs. output
power level via D2Audio’s patented “DynaTiming” algorithm
• AM radio interference avoidance mode allows for dynamic
switching of PWM engines when system microcontroller is in
AM Radio model
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29
Mixer
Mixer configuration blocks have multiple input channels and as
many output channels as required by the system implementation.
The mixer has an input gain parameter for each input to every
mixing node. (e.g. An 8-input mixer with 12 outputs incorporates a
total of 96 independent gain adjustment parameters.) The
minimum gain parameter value is infinite attenuation, or mute.
Mixers
An input mixer provides a two-input, two-output mixing and
routing path. All inputs can be mixed at adjustable gain into any
combination of outputs. Programmable settings are continuously
adjustable from unity (0 dB) gain, through full cut-off.
Compressor/Limiter
The compressor/limiter processor is used to gracefully limit the
dynamic range of the audio signal. This is useful to prevent the
amplifier from clipping or to limit the amplifier output power.
Each compressor/limiter has configurable Compression Ratio,
Threshold, Attack and Release Time, as well as Makeup Gain.
FN7838.3
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D2-7xx83
Upward Compressor
Upward Compressors provide audio compression and limiting
functions but also provide an increase of signal level to inputs
below the threshold setting. Upward Compressors have
configurable Expansion Ratio, Threshold, Attack and Release
Time, as well as Makeup Gain. Controls are supported for Global
settings, Gate adjustment, and for Low Level Expansion.
Upward compressors support two inputs. One input receives the
audio that is processed by the compressor and passed to its
output. A separate side chain input is used as the reference input
for the processing algorithms.
Delay
A delay block simply adds delay to the audio signal. A single
delay parameter is used.
Crossover
Low-pass and high-pass filter blocks add frequency filtering to
the audio paths, providing appropriate signal processing for
speaker crossover functionality, including bi-amplified solutions,
and subwoofer low-pass filtering.
High/Low-Pass Filters
High-Pass and Low-Pass filter blocks are provided for each of the
5 output channels downstream of the Router and Stereo Mixer.
These provide a flexible Crossover function for all the output
channels, including provision for defining the subwoofer
channel’s frequency response.
Filters are implemented as cascaded elements, with elements
allocated for high-pass as well as for low-pass functionality, with
complete flexibility of assignment. Pre-defined filter types
including Butterworth, Bessel, and Linkwitz-Riley
implementations are also provided.
Routers
Routers provide individual audio path selection to any one of
available input channels. The router performs path assignment
only. It does not have a provision for gain or signal level
adjustment.
Audio Processing Enhancements and
Decoding
Depending on the device part number and design-specific
firmware definitions, the DAE-6 device supports a variety of
processing, decoding, virtualization, and pre/post processing
feature sets, as well as options for DSP clock speed and memory
capacity. Features and processing support are shown in
“DAE-6 Device Feature Set Offering” on page 3.
SoundSuite™ Processing
The D2Audio SoundSuite™ audio processing provides a full set of
enhancements to audio that greatly add to the quality and
listening experience of sound in wide scopes of consumer
devices. The D2Audio SoundSuite™ algorithms use
psycho-acoustic processing that create a rich-sounding
environment from small speakers, and synthesizes the sound
and quality equivalent to more complex systems. It is especially
suited to consumer products that include televisions, docking
stations, and mini hi-fi stereo products.
The DAE-6 includes enhanced SoundSuite Processing that
includes:
• D2Audio™ WideSound™
• D2Audio™ DeepBass™
• D2Audio™ AudioAlign™
• D2Audio™ ClearVoice™
The D2Audio™SoundSuite™ algorithms are completely included
within the D2-71083 and D2-74083 DAE-6 devices.
Mark Levinson MightyCat™ Processing
The Mark Levinson MightyCat™ Series of Processors provide an
exclusive set of Mastering Tools and Tuning Capabilities, and
have been developed and refined by Mark Levinson over the
course of his many years of recording experience. The Tools and
Capabilities allow for an extended Studio Quality Tuning that is
only available in the MightyCat™ Series of DAE-6 Processors.
The MightyCat™ algorithms are included within the D2MC-72083
and D2MC-76083 devices. Refer also to the “DAE-6 Device
Feature Set Offering” on page 3.
Loudness Contour
Loudness contour provides adjustment to allow for dynamically
and automatically enhancing the frequency response of the
audio program material relative to the master volume Level
setting. The Loudness Contour models the frequency response
correction as defined by the Fletcher/Munson audio response
curve. It provides for amplitude or volume changes to those
signals to which the ear does not respond equally at very low
listening levels.
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30
FN7838.3
April 28, 2016
D2-7xx83
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
April 28, 2016
FN7838.3
Updated the Ordering Information table on page 2.
Updated Table 1 on page 3 Algorithm Support column for D2-71583-LR, D2-74583-LR and D2-71683-LR.
Replaced the Products section with the About Intersil section.
Added Dolby and DTS disclaimers.
September 20, 2011
FN7838.2
Revise/add available device part numbers and related descriptions.
June 23, 2011
FN7838.1
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
Disclaimer for Dolby Technology License Required Notice:
Intersil may distribute Dolby™ technology separately from its D2Audio™ integrated circuits. Dolby™ technology would be embedded in
firmware to be loaded onto and executed by Dolby™ enabled D2AudioTM integrated circuits. Supply of this implementation of Dolby
technology does not convey a license nor imply a right under any patent or any other industrial or intellectual property right of Dolby
Laboratories to use this implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for
such use is required from Dolby Laboratories. In some cases the Dolby™ technology may include at least one Dolby™ Pro Logic™
decoder. The party receiving this implementation must be licensed for at least one of the three Dolby Laboratories Licensing
Corporation (“Dolby”) technologies contained in this implementation. If the party receiving this implementation is not a Licensee for all
three of the Dolby technologies contained in this implementation then the party may only use the unlicensed technology(ies) contained
on the implementation for internal testing and evaluation purposes.
Disclaimer for DTS (SRS) Technology License Required Notice:
NOTICE OF LICENSE REQUIREMENT: Supply of this implementation of DTS technology to DTS Product Licensees directly or through a
distributor does not incur a royalty payment or convey a license, exhaust DTS’ rights in the implementation, or imply a right under any
patent or any other industrial or intellectual property right of DTS to use, offer for sale, sell, or import such implementation in any
finished end-user or ready-to-use final product. A license from and royalty payment to DTS is required prior to and for such use.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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31
FN7838.3
April 28, 2016
D2-7xx83
Low Plastic Quad Flatpack Packages (LQFP)
Q128.14x14
4X
128 LEAD LOW PLASTIC QUAD FLATPACK PACKAGE .4 MM
PITCH
0.2 Y T-U Z
D
PIN 1
MILLIMETERS
97
Z
128
1
96
U
T
E
E1
SYMBOL
MIN
A
-
A1
0.05
A2
1.35
1.40
b
0.13
b1
0.13
33
D1
0.2 H T-U Z
4X
DETAIL F
H
NOTES
-
0.15
-
1.45
-
0.16
0.23
4
-
0.19
-
c
0.09
-
0.20
-
0.09
-
0.16
-
D
16 BSC
-
D1
14 BSC
3
E
16 BSC
-
E1
14 BSC
3
0.45
L1
64
MAX
1.60
c1
L
65
32
NOM
0.60
0.75
1.00 REF
-
R1
0.08
-
-
-
R2
0.08
-
0.20
-
S
0.20
-
-
-
0
0°
3.5°
7°
-
01
0°
-
-
-
02
11°
12°
13°
-
03
11°
12°
13°
-
N
128
e
0.40 BSC
Rev. 1 7/11
128X b
Y
124X
SEATING PLANE
0.07 M Y T-U
b1
c1
c
0.05
PLATING
02
b
R1
A2
R2
A1
03
S
NOTES:
1. Dimensions are in millimeters. Dimensions in ( ) for
Reference Only.
2. Dimensions and tolerances per AMSEY14.5M-1994.
3. Dimensions D1 and E1 are excluding mold protrusion.
Allowable protrusion is 0.25 per side. Dimensions D1
and E1 are exclusive of mold mismatch and determined by datum plane H.
4. Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall not cause the lead
width to exceed the maximum b dimension by more
than 0.08mm. Dambar cannot be located at the lower
radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
01
A
0.080 Y
e
0
L
(L1)
0.25 GAUGE
PLANE
DETAIL F
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32
FN7838.3
April 28, 2016