Elpida MC-458CB646 8m-word by 64-bit synchronous dynamic ram module unbuffered type Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CB646
8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
EO
The MC-458CB646EFB, MC-458CB646PFB and MC-458CB646XFB are 8,388,608 words by 64 bits synchronous
dynamic RAM module on which 4 pieces of 128M SDRAM: µPD45128163 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
/CAS latency
Clock frequency
Access time from CLK
(MAX.)
(MAX.)
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
L
Part number
MC-458CB646EFB-A80
MC-458CB646EFB-A10
MC-458CB646PFB-A10
77 MHz
7 ns
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
CL = 3
CL = 2
MC-458CB646XFB-A10
CL = 3
CL = 2
od
MC-458CB646XFB-A80
Pr
MC-458CB646PFB-A80
CL = 2
125 MHz
6 ns
100 MHz
6 ns
100 MHz
6 ns
77 MHz
7 ns
t
uc
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (sequential / interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0063N10 (1st edition)
(Previous No. M13049EJ8V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
This product became EOL in March, 2004.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-458CB646
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
Ordering Information
Part number
Clock frequency
Package
Mounted devices
(MAX.)
125 MHz
168-pin Dual In-line Memory Module
4 pieces of µPD45128163G5 (Rev. E)
MC-458CB646EFB-A10
100 MHz
(Socket Type)
(10.16 mm (400) TSOP (II))
MC-458CB646PFB-A80
125 MHz
Edge connector : Gold plated
4 pieces of µPD45128163G5 (Rev. P)
MC-458CB646PFB-A10
100 MHz
25.4 mm height
(10.16 mm (400) TSOP (II))
MC-458CB646XFB-A80
125 MHz
4 pieces of µPD45128163G5 (Rev. X)
MC-458CB646XFB-A10
100 MHz
(10.16 mm (400) TSOP (II))
MC-458CB646EFB-A80
L
EO
t
uc
od
Pr
2
Data Sheet E0063N10
MC-458CB646
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85
86
87
88
89
90
91
92
93
94
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
VSS
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
VSS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1 (A12)
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
L
1
2
3
4
5
6
7
8
9
10
/××× indicates active low signal.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0 (A13), BA1 (A12) : SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0
: Clock Enable Input
/CS0, /CS2
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
od
Pr
Vcc
CLK0
VSS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SDA
SCL
Vcc
VSS
WP
NC
Data Sheet E0063N10
t
uc
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
VSS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0 (A13)
A11
Vcc
EO
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
: Ground
: Write Protect
: No Connection
3
MC-458CB646
Block Diagram
/WE
/CS0
/CS2
DQMB 4
LDQM
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 38
DQ 37
DQ 39
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
UDQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQMB 6
DQMB 5
D1
/CS /WE
LDQM
UDQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQMB 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
LDQM
D2
D5
DQMB 3
UDQM
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
CLK : D1, D2
od
UDQM
C
A0 - A11
A0 - A11 : D1, D2, D4, D5
BA0
CLK2
CLK : D4, D5
C
/CS /WE
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQMB 1
CLK0
/CS /WE
D4
DQMB 2
Pr
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
L
EO
DQMB 0
/CS /WE
A13 : D1, D2, D4, D5
BA1
A12 : D1, D2, D4, D5
/RAS
/RAS : D1, D2, D4, D5
/CAS : D1, D2, D4, D5
CKE0
C
t
uc
/CAS
CLK1, CLK3
CKE : D1, D2, D4, D5
SERIAL PD
SDA
VCC
SCL
D1, D2, D4, D5
C
VSS
A0
D1, D2, D4, D5
A1
A2
47 kΩ
SA0 SA1 SA2
Remarks 1. The value of all resistors is 10 Ω except WP.
2. D1, D2, D4, D5 : µPD45128163 (2M words × 16 bits × 4 banks)
4
WP
Data Sheet E0063N10
MC-458CB646
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
4
W
EO
Voltage on power supply pin relative to GND
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
L
Recommended Operating Conditions
Parameter
TYP.
MAX.
Unit
VCC
3.0
3.3
3.6
V
High level input voltage
VIH
2.0
VCC + 0.3
V
VIL
−0.3
+0.8
V
TA
0
70
°C
Low level input voltage
Operating ambient temperature
Symbol
Condition
Pr
MIN.
Supply voltage
Capacitance (TA = 25 °C, f = 1 MHz)
Test condition
MIN.
MAX.
Unit
CI1
A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE
15
40
pF
CI2
CLK0, CLK2
20
40
CI3
CKE0
15
40
CI4
/CS0, /CS2
10
20
CI5
DQMB0 - DQMB7
3
13
CI/O
DQ0 - DQ63
4
13
Data Sheet E0063N10
TYP.
pF
t
uc
Data input/output capacitance
Symbol
od
Parameter
Input capacitance
5
MC-458CB646
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Operating current
Symbol
ICC1
Test condition
Burst length = 1
Grade MIN. MAX.
/CAS latency = 2
tRC ≥ tRC(MIN.), IO = 0 mA
/CAS latency = 3
Precharge standby current in
power down mode
Precharge standby current in
ICC2P
EO
power down mode
Active standby current in
ICC2N
400
-A80
400
-A10
400
CKE ≤ VIL(MAX.), tCK = 15 ns
4
1
mA
4
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
80
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
mA
ICC3P
32
CKE ≤ VIL(MAX.), tCK = 15 ns
20
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
mA
16
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
120
mA
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
ICC4
tCK ≥ tCK(MIN.), IO = 0 mA
80
/CAS latency = 2
(Burst mode)
L
CBR (Auto) refresh current
-A10
mA
Input signals are changed one time during 30 ns.
non power down mode
Operating current
400
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
non power down mode
Active standby current in
-A80
Unit Notes
ICC5
/CAS latency = 3
tRC ≥ tRC(MIN.)
/CAS latency = 2
ICC6
Input leakage current
II(L)
Output leakage current
IO(L)
High level output voltage
VOH
Low level output voltage
VOL
480
-A10
380
-A80
580
-A10
500
-A80
920
-A10
920
-A80
920
-A10
920
CKE ≤ 0.2 V
mA
2
mA
3
8
mA
–4
+4
µA
DOUT is disabled, VO = 0 to 3.6 V
–1.5
+1.5
µA
IO = –4.0 mA
2.4
VI = 0 to 3.6 V, All other pins not under test = 0 V
IO = +4.0 mA
od
Self refresh current
Pr
/CAS latency = 3
-A80
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
t
uc
6
Data Sheet E0063N10
MC-458CB646
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
CLK
tCL
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
Input
2.4 V
1.4 V
0.4 V
L
EO
tCK
tCH
tAC
tOH
Output
t
uc
od
Pr
Data Sheet E0063N10
7
MC-458CB646
Synchronous Characteristics
Parameter
Clock cycle time
Access time from CLK
Symbol
-A80
-A10
MIN.
MAX.
Unit
MIN.
MAX.
/CAS latency = 3
tCK3
8
(125 MHz)
10
(100 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
13
(77 MHz)
ns
/CAS latency = 3
tAC3
6
6
ns
1
/CAS latency = 2
tAC2
6
7
ns
1
tCH
3
3
ns
CLK low level width
tCL
3
3
ns
Data-out hold time
tOH
3
3
ns
Data-out low-impedance time
tLZ
0
0
ns
/CAS latency = 3
tHZ3
3
6
3
6
/CAS latency = 2
6
3
7
EO
CLK high level width
Data-out high-impedance time
1
ns
ns
tHZ2
3
Data-in setup time
tDS
2
2
ns
Data-in hold time
tDH
1
1
ns
Address setup time
tAS
2
2
ns
tAH
1
1
ns
CKE setup time
tCKS
2
2
ns
tCKH
1
1
ns
CKE setup time (Power down exit)
tCKSP
2
2
ns
Command (/CS0, /CS2, /RAS, /CAS, /WE,
tCMS
2
2
ns
tCMH
1
1
ns
L
Address hold time
CKE hold time
Note
DQMB0 - DQMB7) setup time
DQMB0 - DQMB7) hold time
Note 1. Output load
Pr
Command (/CS0, /CS2, /RAS, /CAS, /WE,
Z = 50 Ω
Output
od
50 pF
Remark These specifications are applied to the monolithic device.
t
uc
8
Data Sheet E0063N10
MC-458CB646
Asynchronous Characteristics
Parameter
Symbol
-A80
MIN.
-A10
MAX.
MIN.
120,000
50
Unit
MAX.
tRC
70
ACT to PRE command period
tRAS
48
PRE to ACT command period
tRP
20
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
20
ns
ACT(one) to ACT(another) command period
tRRD
16
20
ns
Data-in to PRE command period
tDPL
8
10
ns
Data-in to ACT(REF) command period /CAS latency = 3
tDAL3
1CLK+20
1CLK+20
ns
(Auto precharge)
tDAL2
1CLK+20
1CLK+20
ns
tRSC
2
2
CLK
tT
0.5
EO
REF to REF/ACT command period
/CAS latency = 2
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
tREF
70
30
1
64
Note
ns
120,000
ns
30
ns
64
ms
L
t
uc
od
Pr
Data Sheet E0063N10
9
MC-458CB646
Serial PD
(1/2)
Byte No.
0
Function Described
Defines the number of bytes written into
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
80H
1
0
0
0
0
0
0
0
128 bytes
serial PD memory
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
09H
0
0
0
0
1
0
0
1
9 columns
5
Number of banks
01H
0
0
0
0
0
0
0
1
1 bank
6
Data width
40H
0
1
0
0
0
0
0
0
64 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
9
CL = 3 Cycle time
-A80
80H
1
0
0
0
0
0
0
0
8 ns
-A10
A0H
1
0
1
0
0
0
0
0
10 ns
-A80
60H
0
1
1
0
0
0
0
0
6 ns
-A10
60H
0
1
1
0
0
0
0
0
6 ns
EO
1
10
CL = 3 Access time
DIMM configuration type
00H
0
0
0
0
0
0
0
0
None
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
10H
0
0
0
1
0
0
0
0
×16
14
Error checking SDRAM width
00H
0
0
0
0
0
0
0
0
None
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
L
11
Pr
SDRAM module attributes
00H
0
0
0
0
0
0
0
0
22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A80
A0H
-A10
D0H
24
CL = 2 Access time
-A80
60H
-A10
70H
25-26
14H
1
0
1
0
0
0
0
0
10 ns
1
1
0
1
0
0
0
0
13 ns
0
1
1
0
0
0
0
0
6 ns
0
1
1
1
0
0
0
0
7 ns
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
tRP(MIN.)
-A80
-A10
14H
0
0
0
1
28
tRRD(MIN.)
-A80
10H
0
0
0
1
-A10
14H
0
0
0
1
14H
0
0
0
1
29
tRCD(MIN.)
-A80
-A10
14H
0
0
0
1
30
tRAS(MIN.)
-A80
30H
0
0
1
1
-A10
32H
0
0
1
1
10H
0
0
0
1
Module bank density
Data Sheet E0063N10
20 ns
0
1
0
0
20 ns
0
0
0
0
16 ns
0
1
0
0
20 ns
0
1
0
0
20 ns
t
uc
27
31
10
00H
od
21
0
1
0
0
20 ns
0
0
0
0
48 ns
0
0
1
0
50 ns
0
0
0
0
64M bytes
MC-458CB646
(2/2)
Byte No.
32
Function Described
Command and address signal input
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
20H
0
0
1
0
0
0
0
0
2 ns
10H
0
0
0
1
0
0
0
0
1 ns
setup time
33
Command and address signal input
hold time
34
Data signal input setup time
20H
0
0
1
0
0
0
0
0
2 ns
35
Data signal input hold time
10H
0
0
0
1
0
0
0
0
1 ns
00H
0
0
0
0
0
0
0
0
12H
0
0
0
1
0
0
1
0
-A80
E7H
1
1
1
0
0
1
1
1
-A10
4DH
0
1
0
0
1
1
0
1
64H
0
1
1
0
0
1
0
0
36-61
SPD revision
63
Checksum for bytes 0 - 62
EO
62
64-71
72
Manufacture’s JEDEC ID code
Manufacturing location
73-90
Manufacture’s P/N
91-92
Revision code
93-94
Manufacturing date
95-98
Assembly serial number
L
99-125
1.2
Mfg specific
126
Intel specification frequency
127
Intel specification /CAS
-A80
A7H
1
0
1
0
0
1
1
1
latency support
-A10
A5H
1
0
1
0
0
1
0
1
Pr
Timing Chart
100 MHz
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
t
uc
od
Data Sheet E0063N10
11
MC-458CB646
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A(AREA B)
Y
N
Z
M1(AREA B)
Q
EO
R
M2(AREA A)
S
A
J
T
B
H
(OPTIONAL HOLES)
U
K
E
C
B
I
M
L
G
D
L
A1(AREA A)
ITEM
A
Pr
detail of A part
detail of B part
D2
W
od
V
P
X
D1
MILLIMETERS
133.35
A1
133.35±0.13
B
C
11.43
36.83
D
D1
6.35
2.00
D2
E
G
3.125
54.61
6.35
H
1.27 (T.P.)
I
J
8.89
24.495
K
42.18
L
17.78
25.4±0.13
5.62
19.78
2.80 MAX.
P
Q
R
S
T
1.00
R2.0
4.00±0.10
φ 3.00
1.27±0.10
U
V
4.0 MIN.
0.20±0.15
W
X
1.00±0.05
2.54±0.10
Y
3.00 MIN.
Z
3.00 MIN.
M168S-50A103
t
uc
M
M1
M2
N
12
Data Sheet E0063N10
MC-458CB646
[ MEMO ]
L
EO
t
uc
od
Pr
Data Sheet E0063N10
13
MC-458CB646
[ MEMO ]
L
EO
t
uc
od
Pr
14
Data Sheet E0063N10
MC-458CB646
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
EO
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
L
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
Pr
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
od
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
t
uc
Data Sheet E0063N10
15
MC-458CB646
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
L
EO
• The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
t
uc
od
Pr
M8E 00. 4