IDT IDT72T51546 2.5v multi-queue flow-control devices (32 queues) 36 bit wide configuration 1,179,648 bits and 2,359,296 bit Datasheet

ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
1,179,648 bits and 2,359,296 bits
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FEATURES:
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Choose from among the following memory density options:
IDT72T51546  Total Available Memory = 1,179,648 bits
IDT72T51556  Total Available Memory = 2,359,296 bits
Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
– IDT72T51556 : 2,048 x 36 x 32Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Shows PAE and PAF status of 8 Queues
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IDT72T51546
IDT72T51556
Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
FWFT mode of operation on read port
Packet mode operation
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
FSTR
WRADD
8
WEN
WCLK
Q0
READ CONTROL
WRITE CONTROL
WADEN
Q1
RADEN
ESTR
RDADD
8
REN
RCLK
EREN
ERCLK
Q2
Qout
Din
PAF
PAFn
8
WRITE FLAGS
FF
x36
DATA OUT
OV
READ FLAGS
x36
DATA IN
OE
Q31
PR
PAE
PAEn
8
PRn
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5998/3
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
DESCRIPTION:
The IDT72T51546/72T51556 multi-queue flow-control devices is a single
chip within which anywhere between 1 and 32 discrete FIFO queues can be
setup. All queues within the device have a common data input bus, (write port)
and a common data output bus, (read port). Data written into the write port is
directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective
queue via an internal multiplex operation, addressed by the user. Data writes
and reads can be performed at high speeds up to 200MHz, with access times
of 3.6ns. Data write and read operations are totally independent of each other,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet mode of operation is also provided when the device is configured
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within
a queue is available for reading. The Packet Ready provides the user with
a means by which to mark the start and end of packets of data being passed
through the queues. The multi-queue device then provides the user with an
internally generated packet ready status per queue.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the Queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at high
speed.
The multi-queue flow-control device has the capability of operating its IO in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected
via the IOSEL input. The core supply voltage (VCC) to the multi-queue is always
2.5V, however the output levels can be set independently via a separate supply,
VDDQ.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
of the functional blocks within the device.
2
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
D35 = TEOP
D34 = TSOP
Din
x9, x18, x36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
D0 - D35
WCLK WEN
TMS
INPUT
DEMUX
JTAG
Logic
WRADD
WADEN
TDI
TDO
TCK
8
Write Control
Logic
TRST
Write Pointers
Packet
Mode Logic
FSTR
PAFn
FSYNC
8
PAF
General Flag
Monitor
Upto 32
FIFO
Queues
FXO
FXI
FF
PAF
SI
SO
SCLK
SENI
SENO
FM
IW
OW
BM
Serial
Multi-Queue
Programming
Vref
PD
ESTR
ESYNC
EXI
EXO
8
Reset
Logic
Read Control
Logic
RDADD
RADEN
NULL-Q
REN
RCLK
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
2
OUTPUT
REGISTER
PRS
MRS
IOSEL
OV
PAE
Read Pointers
PKT
DFM
PRn/PAEn
PAE
General Flag
Monitor
MAST
ID0
ID1
ID2
DF
8
Active Q
Flags
2.3 Mbit
Dual Port
Memory
Active Q
Flags
PR
Q35 = REOP
Q34 = RSOP
EREN
ERCLK
IO Level Control
&
Power Down
OE
Q0 - Q35
Qout x9, x18, x36
Figure 1. Multi-Queue Flow-Control Device Block Diagram
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5998 drw02
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
A1 BALL PAD CORNER
A
D14
D13
D12
D10
D7
D4
D1
TCK
TDO
ID1
Q3
Q6
Q9
Q12
Q14
Q15
D15
D16
D11
D9
D6
D3
D0
TMS
TDI
ID0
Q2
Q5
Q8
Q11
Q13
Q19
D17
D18
D19
D8
D5
D2
TRST
IOSEL
ID2
Q0
Q1
Q4
Q7
Q10
Q17
Q18
D20
D21
D23
D24
D26
D27
D29
D30
D32
D33
GND
NULL-Q
PD
GND
SI
DFM
SENO
SENI
B
C
D
E
C
N
N
O
I
A
T
V
A
D
A RM
O
F
IN
D22
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
D25
VDDQ
VDDQ
VCC
VCC
GND
GND
D28
VDDQ
VCC
GND
GND
GND
D31
VCC
VCC
GND
GND
D34
VCC
GND
GND
D35
VCC
GND
VREF
VCC
DF
VDDQ
VDDQ
VDDQ
Q16
Q21
Q20
VCC
VCC
VDDQ
VDDQ
Q24
Q23
Q22
GND
GND
GND
VCC
VDDQ
Q27
Q26
Q25
GND
GND
GND
GND
VCC
VCC
Q30
Q29
Q28
GND
GND
GND
GND
GND
GND
VCC
Q33
Q32
Q31
GND
GND
GND
GND
GND
GND
GND
VCC
PKT
Q35
Q34
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
GND
MAST
FM
VDDQ
VCC
GND
GND
GND
GND
GND
GND
VCC
VDDQ
BM
IW
SO
VDDQ
VDDQ
VCC
VCC
GND
GND
VCC
VCC
VDDQ
VDDQ
OE
SCLK
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VDDQ
WADEN
PAF3
PAF6
PAF7
FF
OV
PAE
PAE7
WRADD6 WRADD5 FSYNC
FSTR
PAF2
PAF5
PAF4
PAF
PR
ERCLK
WRADD7
FXI
FXO
PAF0
PAF1
WEN
WCLK
PRS
MRS
1
2
3
4
5
6
7
8
9
E
F
G
H
J
K
L
M
N
WRADD1 WRADD0
P
WRADD4 WRADD3 WRADD2
VCC
OW
RDADD0 RDADD1
VDDQ
RDADD2 RDADD3 RDADD4
PAE6
PAE3
RDADD5 RDADD6 RDADD7
EREN
PAE5
PAE2
RADEN
ESTR
ESYNC
RCLK
REN
PAE4
PAE1
PAE0
EXO
EXI
10
11
12
13
14
15
16
VDDQ
R
T
5998 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
4
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 32 queues
and when a respective queue is selected on the read port, the almost empty flag
provides status for that queue.
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 32 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 32 Queues within the device.
These queues can be configured to utilize the total available memory, providing
the user with full flexibility and ability to configure the queues to be various depths,
independent of one another.
PROGRAMMABLE FLAG BUSSES
In addition to these dedicated flags, full & almost full on the write port and output
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 32 queues in the device.
In the IDT72T51546/72T51556 multi-queue flow-control devices the user
has the option of utilizing anywhere between 1 and 32 queues, therefore the
8 bit flag status busses are multiplexed between the 32 queues, a flag bus can
only provide status for 8 of the 32 queues at any moment, this is referred to as
a “Quadrant”, such that when the bus is providing status of queues 1 through
8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so
on up to quadrant 4. If less than 32 queues are setup in the device, there are
still 4 quadrants, such that in “Polled” mode of operation the flag bus will still cycle
through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant 3 will reflect the status of queues 17 through 22 on the least significant
6 bits, the most significant 2 bits of the flag bus are don’t care and the 4th quadrant
outputs will be don’t care also.
The flag busses are available in two user selectable modes of operation,
“Polled” or “Direct”. When operating in polled mode a flag bus provides status
of each quadrant sequentially, that is, on each rising edge of a clock the flag bus
is updated to show the status of each quadrant in order. The rising edge of the
write clock will update the almost full bus and a rising edge on the read clock will
update the almost empty bus. The mode of operation is always the same for both
the almost full and almost empty flag busses. When operating in direct mode, the
quadrant on the flag bus is selected by the user. So the user can actually address
the quadrant to be placed on the flag status busses, these flag busses operate
independently of one another. Addressing of the almost full flag bus is done via
the write port and addressing of the almost empty flag bus is done via the read
port.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256 x36 bits. When the user is configuring the number of queues and individual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72T51546 and
IDT72T51556 the Total Available Memory is 128 and 256 blocks respectively
(a block being 256 x36). Queues can be built from these blocks to make any
size queue desired and any number of queues desired.
BUS WIDTHS
The input port is common to all queues within the device, as is the output port.
The device provides the user with Bus Matching options such that the input port
and output port can be either x9, x18 or x36 bits wide provided that at least one
of the ports is x36 bits wide, the read and write port widths being set
independently of one another. Because the ports are common to all queues the
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
from the device read port is read from a queue selected via the read queue select
address inputs. Data can be simultaneously written into and read from the same
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as a
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
based on the rising edge of a write clock provided setup and hold times are met.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automatically fall through to the output register. All subsequent words from that
queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 32 queues and when a
PACKET READY
The multi-queue flow-control device also offers a “Packet Mode” operation.
Packet Mode is user selectable and requires the device to be configured with
both write and read ports as 36 bits wide. In packet mode, users can define the
length of packets or frame by using the two most significant bits of the 36-bit word.
Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to mark the
End of Packet (EOP) as shown in Table 5). When writing data into a given queue
, the first word being written is marked, by the user setting bit 34 as the “Start
of Packet” (SOP) and the last word written is marked as the “End of Packet” (EOP)
with all words written between the Start of Packet (SOP) marker (bit 34) and the
End of packet (EOP) packet marker (bit 35) constituting the entire packet. A
packet can be any length the user desires, up to the total available memory in
the multi-queue device. The device monitors the SOP (bit 34) and looks for the
word that contains the EOP (bit 35). The read port is supplied with an additional
5
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
status flag, “Packet Ready”. The Packet Ready (PR) flag in conjunction with
Output Valid (OV) indicates when at least one packet is available to read. When
in packet mode the almost empty flag status , provides packet ready flag status
for individual queues.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
memory blocks within a multi-queue device can be allocated to increase the
depth of a queue. For example, depth expansion of 8 devices provides the
possibility of 8 queues of 64K x36 deep, each queue being setup within a single
device utilizing all memory blocks available to produce a single queue. This is
the deepest queue that can setup within a device.
For queue expansion a maximum number of 256 (8 x 32) queues may be
setup, each queue being 2K x36 deep, if less queues are setup, then more
memory blocks will be available to increase queue depths if desired. When
connecting multi-queue devices in expansion mode all respective input pins
(data & control) and output pins (data & flags), should be “connected” together
between individual devices.
EXPANSION
Expansion of multi-queue devices is also possible, up to 8 devices can be
connected in a parallel fashion providing the possibility of both depth expansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queues available. Depth expansion is possible by virtue of the fact that more
6
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol &
Pin No.
BM
(L14)
Name
Bus Matching
D[35:0]
Data Input Bus
Din
(See Pin No.
table for details)
I/O TYPE
LVTTL
INPUT
Description
This pin is setup before Master Reset and must not toggle during any device operation. This pin is used
along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3
for details.
HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge
INPUT
of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet
markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs
may be used, any unused inputs should be tied LOW.
DF(1)
(L3)
Default Flag
LVTTL
INPUT
If the user requires default programming of the multi-queue device, this pin must be setup before Master
Reset and must not toggle during any device operation. The state of this input at master reset determines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
DFM(1)
(L2)
Default Mode
LVTTL
INPUT
The multi-queue device requires programming after master reset. The user can do this serially via the
serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
ERCLK
(R10)
RCLK Echo
HSTL-LVTTL Read Clock Echo output, this output generates a clock based on the read clock input, this is used for Source
OUTPUT
Synchronous clocking where the receiving devices utilizes the ERCLK to clock data output from the Queue.
EREN
(R11)
REN Echo
HSTL-LVTTL Read Enable Echo output, can be used in conjunction with the ERCLK output to load data output from the
OUTPUT
Queue into the receiving device.
ESTR
(R15)
PAEn Flag Bus
Strobe
ESYNC
(R16)
PAEn Bus Sync HSTL-LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus
OUTPUT
during Polled operation of the PAEn bus. During Polled operation each quadrant of queue status flags is
loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads
quadrant 1 on to PAEn, the second RCLK rising edge loads quadrant 2 and so on. The fifth RCLK rising
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed
on to the PAEn bus, the ESYNC output will be HIGH. For all other quadrants of that device, the ESYNC
output will be LOW.
EXI
(T16)
PAEn Bus
Expansion In
LVTTL
INPUT
The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn
bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The EXI
receives a token from the previous device in a chain. In single device mode the EXI input must be tied
LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI input
must be connected to the EXO output of the same device. In expansion mode the EXI of the first device
should be tied LOW, when direct mode is selected.
EXO
(T15)
PAEn Bus
Expansion Out
LVTTL
OUTPUT
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAEn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the PAEn bus with respect to RCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAEn bus. This continues through the chain
and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device
in the chain provides synchronization to the user of this looping event.
FF
(P8)
Full Flag
LVTTL
INPUT
If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
and the RDADD bus to select a quadrant of queues to be placed on to the PAEn bus outputs. A quadrant
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus
selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
HSTL-LVTTL This pin provides the full flag output for the active Queue, that is, the queue selected on the input port
OUTPUT
for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during
expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common
line. The device with a queue selected takes control of the FF bus, all other devices place their FF output
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
7
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
FM(1)
(K16)
Name
Flag Mode
I/O TYPE
Description
HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT
FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled
or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
FSTR
(R4)
PAFn Flag Bus
Strobe
LVTTL
INPUT
If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a quadrant of queues to be placed on to the PAFn bus outputs. A quadrant
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
FSYNC
(R3)
PAFn Bus Sync
LVTTL
OUTPUT
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags
is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
quadrant 1 on to PAFn, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising
edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed
on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC
output will be LOW.
FXI
(T2)
PAFn Bus
Expansion In
LVTTL
INPUT
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a token from the previous device in a chain. In single device mode the FXI input must be tied
LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO
(T3)
PAFn Bus
Expansion Out
LVTTL
OUTPUT
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain
and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device
in the chain provides synchronization to the user of this looping event.
ID[2:0](1)
ID2-C9
ID1-A10
ID0-B10
Device ID Pins
IOSEL
(C8)
IO Select
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.
IW(1)
(L15)
Input Width
LVTTL
INPUT
This pin is used in conjunction with OW and BM to setup the input and output bus widths to be a combination
of x9, x18 or x36, (providing that one port is x36).
MAST(1)
(K15)
Master Device
HSTL-LVTTL The state of this input at Master Reset determines whether a given device (within a chain of devices), is the
INPUT
Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
master device is the first to take control of all outputs after a master reset, all slave devices go to HighImpedance, preventing bus contention. If a multi-queue device is being used in single device mode, this
pin must be set HIGH.
MRS
(T9)
Master Reset
HSTL-LVTTL A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required
INPUT
after master reset.
NULL-Q
(J2)
Null Queue
Select
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
and RADEN address bus to address the Null-Q.
HSTL-LVTTL For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
INPUT
selection takes place the 3 MSb’s of this 8 bit address bus are used to address the specific device (the
5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is ‘111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
8
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
OE
(M14)
Name
I/O TYPE
Description
Output Enable
HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
INPUT
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides threestate of that respective device.
OV
(P9)
Output Valid
Flag
HSTL-LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control device
OUTPUT
data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV
flag represents the data in that respective queue. When a selected queue on the read port is read to
empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has
High-Impedance capability, required when multiple devices are used and the OV flags are tied together.
OW(1)
(L16)
Output Width
PAE
(P10)
Programmable
Almost-Empty
Flag
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
Programmable HSTL-LVTTL On the 32Q device the PAEn/PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
Almost-Empty
OUTPUT
Almost Empty mode or Packet mode. This output bus provides PAE/PRn status of 8 queues (1 quadrant),
Flag Bus/Packet
within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs
ReadyFlag Bus
provide programmable empty flag status or packet ready status, in either direct or polled mode. The mode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of
High-Impedance state, this is important during expansion of multi-queue devices. During direct operation
the PAEn/PRn bus is updated to show the PAE/PR status of a quadrant of queues within a selected device.
Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is
loaded with the PAE/PRn status of multi-queue flow-control quadrants sequentially based on the rising
edge of RCLK. PAE or PR operation is determined by the state of PKT during master reset.
PAF
(R8)
Programmable HSTL-LVTTL This pin provides the Almost-Full flag status for the Queue that has been selected on the input port for
Almost-Full Flag OUTPUT
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected
Queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is
synchronized to WCLK.
PAFn
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
Programmable HSTL-LVTTL On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status
Almost-Full Flag OUTPUT
of 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/
Bus
write operations these outputs provide programmable full flag status, in either direct or polled mode. The
mode of flag operation is determined during master reset via the state of the FM input. This flag bus is
capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct
operation the PAFn bus is updated to show the PAF status of a quadrant of queues within a selected
device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn
bus is loaded with the PAF status of multi-queue flow-control quadrants sequentially based on the rising
edge of WCLK.
PD
(K1)
Power Down
HSTL
INPUT
This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
PKT(1)
(J14)
Packet Mode
LVTTL
INPUT
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and
LVTTL
INPUT
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
HSTL-LVTTL This pin provides the Almost-Empty flag status for the Queue that has been selected on the output port
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
9
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
PKT(1)
(Continued)
(J14)
Name
I/O TYPE
Packet Mode
PR
(R9)
Packet Ready
Flag
HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected
OUTPUT
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets PR LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
PRS
(T8)
Partial Reset
HSTL-LVTTL A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
LVTTL
INPUT
Description
the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected.
Packet Ready utilizes user marked locations to identify start and end of packets being written into the
device. Packet Mode can only be selected if both the input port width and output port width are 36 bits.
Q[35:0]
Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
Qout
OUTPUT
of RCLK provided that REN is LOW, OE is LOW and the Queue is selected. Note, that in Packet Ready
(See Pin No.
mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more
table for details)
detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.
RADEN
(R14)
Read Address
Enable
HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
INPUT
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the
part has been completed and SENO has gone LOW.
RCLK
(T10)
Read Clock
HSTL-LVTTL When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAEn/PRn flag quadrant to be placed on the PAEn/PRn bus during direct flag operation. During polled
flag operation the PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized
to RCLK. The PAE, PR and OV outputs are all synchronized to RCLK. During device expansion the EXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
RDADD
Read Address
[7:0]
Bus
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
HSTL-LVTTL For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
INPUT
function of RDADD is to select a Queue to be read from. The least significant 5 bits of the bus, RDADD[4:0]
are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data
can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On the
next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue select,
data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the
first word fall through effect.
The second function of the RDADD bus is to select the quadrant of queues to be loaded on to the
PAEn/PRn bus during strobed flag mode. The least significant 2 bits, RDADD[1:0] are used to select the
quadrant of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5] are again
used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address
bits RDADD[4:2] are don’t care during quadrant selection. The quadrant address present on the RDADD
bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed
on to the Qout bus, read from the previously selected Queue on this RCLK edge). Please refer to Table 2
for details on RDADD bus.
10
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
REN
(T11)
Name
I/O TYPE
Description
Read Enable
HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.
INPUT
A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not
required to cycle the PAEn/PRn bus (in polled mode) or to select the PAEn quadrant , (in direct mode).
SCLK
(N3)
Serial Clock
HSTL-LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
SENI
(M2)
Serial Input
Enable
HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT
part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
SENO
(M1)
Serial Output
Enable
HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device
OUTPUT
has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
SI
(L1)
Serial In
HSTL-LVTTL During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO
(M3)
Serial Out
HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
OUTPUT
to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK(2)
(A8)
JTAG Clock
LVTTL
INPUT
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
TDI(2)
(B9)
JTAG Test Data
Input
LVTTL
INPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
(A9)
JTAG Test Data
Output
LVTTL
OUTPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
JTAG Mode
Select
LVTTL
INPUT
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2)
(C7)
JTAG Reset
LVTTL
INPUT
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
11
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
TRST(2)
(Continued)
Name
JTAG Reset
I/O TYPE
LVTTL
Description
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
WADEN
(P4)
Write Address
Enable
HSTL-LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
INPUT
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
WCLK
(T7)
Write Clock
HSTL-LVTTL When enabled by WEN, the rising edge of WCLK writes data into the selected Queue via the input
INPUT
bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of
WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also
select the flag quadrant to be placed on the PAFn bus during direct flag operation. During polled flag
operation the PAFn bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK.
The PAFn, PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and
FXI signals are based on WCLK. The WCLK must be continuous and free-running.
WEN
(T6)
Write Enable
HSTL-LVTTL The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A
INPUT
queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless
of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK
cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn
bus (in polled mode) or to select the PAFn quadrant , (in direct mode).
WRADD
Write Address
[7:0]
Bus
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
INPUT
first function of WRADD is to select a Queue to be written to. The least significant 5 bits of the bus,
WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant
3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present
on the WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that
data present on the Din bus can be written into the previously selected queue on this WCLK edge and
on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue
select, data can be written into the newly selected queue.
The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the PAFn
bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant
of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to
select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits
WRADD[4:2] are don’t care during quadrant selection. The quadrant address present on the WRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be
written into the previously selected queue on this WCLK edge). Please refer to Table 1 for details on the
WRADD bus.
VCC
(See pg. 13)
+2.5V Supply
Power
These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
(See pg. 13)
O/P Rail Voltage
Power
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
GND
(See pg. 13)
Ground Pin
Ground
These are Ground pins and must all be connected to the GND supply rail.
Vref
(K3)
Reference
Voltage
HSTL
INPUT
This is a Voltage Reference input and must be connected to a voltage level determined from the table
"Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 59-62 and Figures 36-38.
12
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN NUMBER TABLE
Symbol
Name
I/O TYPE
Pin Number
D[35:0]
Din
Data Input Bus
HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),
INPUT
D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5,
D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Q[35:0]
Qout
Data Output Bus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),
OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14,
Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,
Q(1,0)-C(11,10)
V CC
+2.5V Supply
Power
D(7-10), E(6,7,10,11), F(5,12), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(5,12), M(6,7,10,11), N(7-10)
VDDQ
O/P Rail Voltage
Power
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
GND
Ground Pin
Ground
E(8-9), F(6-11), G(6-11), H(5-12), J(1,5-12), K(2,6-11,14), L(6-11), M(8-9)
13
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
ABSOLUTE MAXIMUM RATINGS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +3.6(2)
Unit
V
TSTG
Storage Temperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
Symbol
CIN
(2,3)
COUT(1,2)
Parameter(1)
Conditions
VCC
GND
Parameter
Supply Voltage
Supply Voltage
10
pF
Output
Capacitance
VOUT = 0V
15
pF
Typ.
Max.
Unit
2.375
0
2.5
0
2.625
0
V
V
VIH
Input High Voltage
 LVTTL
 eHSTL
 HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
Input Low Voltage
 LVTTL
 eHSTL
 HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
 eHSTL
 HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
0
—
70
°C
-40
—
85
°C
Voltage Reference Input
VREF
(HSTL only)
TA
Operating Temperature Commercial
TA
Operating Temperature Industrial
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
14
Unit
VIN = 0V
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
Min.
(3)
Input
Capacitance
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Max.
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input Leakage Current
–10
10
µA
ILO
Output Leakage Current
–10
10
µA
VDDQ -0.4
VDDQ -0.4
VDDQ -0.4
—
—
—
—
—
—
0.4V
0.4V
0.4V
V
V
V
V
V
V
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
150
150
mA
mA
mA
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
Standby VCC Current in Power Down mode(VCC = 2.5V) I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
—
—
—
25
100
100
—
50
50
mA
mA
mA
mA
mA
mA
Active VDDQ Current (VDDQ = 2.5V LVTTL)
(VDDQ = 1.5V HSTL)
(VDDQ = 1.8V eHSTL)
—
—
—
10
10
10
mA
mA
mA
VOH
(3)
Output Logic “1” Voltage,
IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
Output Logic “0” Voltage,
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
ICC2(1)
Standby VCC Current (VCC = 2.5V)
ICC3(1)
IDDQ(1,2)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
15
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL
1.5V AC TEST CONDITIONS
AC TEST LOADS
VDDQ/2
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
0.25 to 1.25V
0.4ns
0.75
VDDQ/2
50Ω
Z0 = 50Ω
I/O
5998 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDED HSTL
1.8V AC TEST CONDITIONS
0.4 to 1.4V
0.4ns
0.9
VDDQ/2
∆tCD
(Typical, ns)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
6
5
4
3
2
1
NOTE:
1. VDDQ = 1.8V±.
20 30 50
2.5V LVTTL
2.5V AC TEST CONDITIONS
80 100
Capacitance (pF)
200
5998 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
GND to 2.5V
1ns
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE & tOLZ
Output
Normally
LOW
Output
Normally
HIGH
VCC/2
tOHZ
VCC/2
100mV
100mV
VOL
VOH
100mV
100mV
VCC/2
VCC/2
NOTE:
1. REN is HIGH.
5998 drw04b
16
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tPRSS
tPRSH
tOLZ (OE-Qn)(2)
tOHZ(2)
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
tAH
tWFF
tROV
tSTS
tSTH
tQS
tQH
tWAF
tRAE
tPAF
tPAE
Parameter
Clock Cycle Frequency (WCLK & RCLK)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Partial Reset Setup
Partial Reset Hold
Output Enable to Output in Low-Impedance
Output Enable to Output in High-Impedance
Output Enable to Data Output Valid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
SCLK to Serial Data Out
SCLK to Serial Enable Out
Serial Data Out Propagation Delay
Serial Enable Propagation Delay
Programming Complete to Write Queue Selection
Programming Complete to Read Queue Selection
Address Setup
Address Hold
Write Clock to Full Flag
Read Clock to Output Valid
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
Queue Setup
Queue Hold
WCLK to PAF flag
RCLK to PAE flag
Write Clock to Synchronous Almost-Full Flag Bus
Read Clock to Synchronous Almost-Empty Flag Bus
Com'l & Ind'l(1)
IDT72T51546L6
IDT72T51556L6
Min.
Max.
Unit
—
0.6
5
2.3
2.3
1.5
0.5
1.5
0.5
30
15
10
1.5
0.5
0.6
0.6
0.6
—
100
45
45
20
1.2
20
1.2
—
—
1.5
1.5
20
20
1.5
1.0
—
—
1.5
0.5
1.5
1.0
0.6
0.6
0.6
0.6
—
0.6
6
2.7
2.7
2.0
0.5
2.0
0.5
30
15
10
2.0
0.5
0.6
0.6
0.6
—
100
45
45
20
1.2
20
1.2
—
—
1.5
1.5
20
20
2.5
1.5
—
—
2.0
0.5
2.0
0.5
0.6
0.6
0.6
0.6
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
3.6
—
—
—
—
—
—
—
—
—
—
—
—
3.6
3.6
3.6
10
—
—
—
—
—
—
—
20
20
3.7
3.7
—
—
—
—
3.6
3.6
—
—
—
—
3.6
3.6
3.6
3.6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
—
—
—
—
—
—
—
20
20
3.7
3.7
—

—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
AD
INF VA
O R NCE
MA
TIO
N
Symbol
Commercial
IDT72T51546L5
IDT72T51556L5
Min.
Max.
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
17
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
tERCLK
tCLKEN
tPAELZ(2)
tPAEHZ(2)
tPAFLZ(2)
tPAFHZ(2)
tFFHZ(2)
tFFLZ(2)
tOVLZ(2)
tOVHZ(2)
tFSYNC
tFXO
tESYNC
tEXO
tPR
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tSKEW5
tXIS
tXIH
Parameter
RCLK to Echo RCLK Output
RCLK to Echo REN Output
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLK to Full Flag to High-Impedance
WCLK to Full Flag to Low-Impedance
RCLK to Output Valid Flag to Low-Impedance
RCLK to Output Valid Flag to High-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
RCLK to Packet Ready Flag
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for PR and OV
SKEW time between RCLK and WCLK for OV when in Packet Mode
Expansion Input Setup
Expansion Input Hold
Com'l & Ind'l(1)
IDT72T51546L6
IDT72T51556L6
Min.
Max.
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4
5
5
5
8
1.0
0.5
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
6
6
10
1.0
0.5
4.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
4.2
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
—
AD
INF VA
O R NCE
MA
TIO
N
Symbol
Commercial
IDT72T51546L5
IDT72T51556L5
Min.
Max.
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
FUNCTIONAL DESCRIPTION
MASTER RESET
A Master Reset is performed by toggling the MRS input from HIGH to LOW
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programming either serially by the user via
the serial port, or using the default settings. During a master reset the state of
the following inputs determine the functionality of the part, these pins should be
held HIGH or LOW.
PKT – Packet Mode
FM – Flag bus Mode
IW, OW, BM – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM – Programming mode, serial or default
DF – Offset value for PAE and PAF
Once a master reset has taken place, the device must be programmed either
serially or via the default method before any read/write operations can begin.
See Figure 5, Master Reset for relevant timing.
PARTIAL RESET
A Partial Reset is a means by which the user can reset both the read and write
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK
cycles before the PRS goes LOW. The partial reset is then performed by toggling
the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least
one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
A Partial Reset only resets the read and write pointers of a given queue, a
partial reset will not effect the overall configuration and setup of the multi-queue
device and its queues.
See Figure 6, Partial Reset for relevant timing.
SERIAL PROGRAMMING
The multi-queue flow-control device is a fully programmable device, providing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the PAF/PAE flags within
respective queues. All user programming is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and PAE/PAF offset values. The
IDT72T51546/72T51556 devices are capable of up to 32 queues and
therefore contain 32 sets of registers for the setup of each queue.
During a Master Reset if the DFM (Default Mode) input is LOW, then the device
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate
a serial bit stream which should be serially loaded into the device via the serial
port. For the IDT72T51546/72T51556 devices the serial programming requires a total number of serially loaded bits per device, (SCLK cycles with SENI
enabled), calculated by: 19+(Qx72) where Q is the number of queues the user
wishes to setup within the device.
Once the master reset is complete and MRS is HIGH, the device can be
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable), is LOW. Once serial programming of the device has been successfully
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
completed the device will indicate this via the SENO (serial output enable) going
active, LOW. Upon detection of completion of programming, the user should
cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI
once programming of a device is complete. Therefore, SENO will go LOW after
programming provided SENI is LOW, once SENI is taken HIGH again, SENO
will also go HIGH. The operation of the SO output is similar, when programming
of a given device is complete, the SO output will follow the SI input.
If devices are being used in expansion mode the serial ports of devices should
be cascaded. The user can load all devices via the serial input port control pins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
program to generate the serial bit stream, the program prompting the user for
the number of devices to be programmed. The SENO and SO (serial out) of
the first device should be connected to the SENI and SI inputs of the second
device respectively and so on, with the SENO & SO outputs connecting to the
SENI & SI inputs of all devices through the chain. All devices in the chain should
be connected to a common SCLK. The serial output port of the final device should
be monitored by the user. When SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully completed. Upon detection of completion of programming, the user should cease all
programming and take SENI of the first device in the chain inactive, HIGH.
As mentioned, the first device in the chain has its serial input port controlled
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream. When programming of this device is complete it will take
its SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its SENI
input LOW. This process continues through the chain until all devices are
programmed and the SENO of the final device goes LOW.
Once all serial programming has been successfully completed, normal
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72T51546/72T51556 devices require
a total number of serially loaded bits per device to complete serial programming,
(SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)] where Q is the
number of queues the user wishes to setup within the device, where n is the
number of devices in the chain.
See Figure 7, Serial Port Connection and Figure 8, Serial Programming for
connection and timing information.
DEFAULT PROGRAMMING
During a Master Reset if the DFM (Default Mode) input is HIGH the multiqueue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means by which to setup the multi-queue flow-control device,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possible are setup, with all of the parts available memory blocks being allocated
equally between the queues. The values of the PAE/PAF offsets is determined
by the state of the DF (default) pin during a master reset.
For the IDT72T51546/72T51556 devices the default mode will setup 32
queues, each queue being 1024 x36 and 2048 x36 deep respectively. For both
devices the value of the PAE/PAF offsets is determined at master reset by the
state of the DF input. If DF is LOW then both the PAE & PAF offset will be 8, if
HIGH then the value is 128.
When configuring the IDT72T51546/72T51556 devices in default mode the
user simply has to apply WCLK cycles after a master reset, until SENO goes
LOW, this signals that default programming is complete. These clock cycles are
required for the device to load its internal setup registers. When a single multiqueue device is used, the completion of device programming is signaled by the
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
SENO output of a device going from HIGH to LOW. Note, that SENI must be
held LOW when a device is setup for default programming mode.
When multi-queue devices are connected in expansion mode, the SENI of
the first device in a chain can be held LOW. The SENO of a device should
connect to the SENI of the next device in the chain. The SENO of the final device
is used to indicate that default programming of all devices is complete. When the
final SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 9, Default Programming.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
selection. The queue selection requires 1 WCLK cycle. All subsequent data
writes will be to this queue until another queue is selected.
Standard mode operation is defined as individual words will be written to the
device as opposed to Packet Mode where complete packets may be written.
The write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
Changing queues requires a minimum of 3 WCLK cycles on the write port
(see Figure 10, Write Queue Select, Write Operation and Full flag Operation).
WADEN goes high signaling a change of queue (clock cycle “A”). The address
on WRADD at that time determines the next queue. Data presented during that
cycle (“A”) and the next cycle (“B” and “C”), will be written to the active (old)
queue, provided WEN is active LOW. If WEN is HIGH (inactive) for these 3 clock
cycles, data will not be written in to the previous queue. The write port discrete
full flag will update to show the full status of the newly selected queue (QX) at this
last cycle’s rising edge (“C”). Data present on the data input bus (Din), can be
written into the newly selected queue (QX) on the rising edge of WCLK on the
third cycle (“D”) following a change of queue, provided WEN is LOW and the
new queue is not full. If the newly selected queue is full at the point of its selection,
any writes to that queue will be prevented. Data cannot be written into a full
queue.
Refer to Figure 10, Write Queue Select, Write Operation and Full flag
Operation, Figure 11, Write Operations & First Word Fall Through for timing
diagrams and Figure 12, Full Flag Timing in Expansion Mode for timing
diagrams.
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured in two distinct modes, namely Standard Mode and Packet Mode.
STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured up to a maximum of 32 queues into which data can be written via
a common write port using the data inputs (Din), write clock (WCLK) and write
enable (WEN). The queue to be written is selected by the address present on
the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of WEN does not impact the queue
TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN FSTR
Write
Queue
Select
1
PAFn
Quadrant
Select
0
0
WRADD[7:0]
7 6 5
4 3 2
1 0
Device Select Write Queue Address
(Compared to (5 bits = 32 Queues)
ID0,1,2)
1
Quadrant
Address
00
01
10
11
7 6 5
Device Select
(Compared to
ID0,1,2)
4 3 2
X
X
1 0
X Quadrant
Address
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
5998 drw05
20
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
READ QUEUE SELECTION AND READ OPERATION
(STANDARD MODE)
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured up to a maximum of 32 queues which data can be read via a common
read port using the data outputs (Qout), read clock (RCLK) and read enable
(REN). An output enable, OE control pin is also provided to allow HighImpedance selection of the Qout data outputs. The multi-queue device read port
operates in a mode similar to “First Word Fall Through” on a SuperSync IDT
FIFO, but with the added feature of data output pipelining (see Figure 11, Write
Operations & First Word Fall Through). The queue to be read is selected by
the address presented on the read address bus (RDADD) during a rising edge
on RCLK while read address enable (RADEN) is HIGH. The state of REN does
not impact the queue selection. The queue selection requires 1 RCLK cycles.
All subsequent data reads will be from this queue until another queue is selected.
Standard mode operation is defined as individual words will be read from the
device as opposed to Packet Mode where complete packets may be read. The
read port is designed such that 100% bus utilization can be obtained. This means
that data can be read out of the device on every RCLK rising edge including
the cycle that a new queue is being addressed.
Changing queues requires a minimum of three RCLK cycles on the read port
(see Figure 13, Read Queue Select, Read Operation). RADEN goes high
signaling a change of queue (clock cycle “D”). The address on RDADD at that
time determines the next queue. Data presented during that cycle (“D”) will be
read at “D” (+ tA), and the next cycle (“E”), can continue to be read from the active
(old) queue (QP), provided REN is active LOW. If REN is HIGH (inactive) for
these two clock cycles, data will not be read from the previous queue. The next
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
cycle’s rising edge (“F”), the read port discrete empty flag will update to show
the empty status of the newly selected queue (QF). The internal pipeline is also
loaded at this time (“F”) with the last word from the previous (old) queue (QF)
as well as the next word from the new queue (QF). Both of these words will fall
through to the output register (provided the OE is asserted) consecutively
(cycles “F” and “G” respectively) following the selection of the new queue
regardless of the state of REN, unless the new queue (QF) is empty. If the newly
selected queue is empty, any reads from that queue will be prevented. Data
cannot be read from an empty queue. The last word in the data output register
(from the previous queue), will remain on the data bus, but the output valid flag,
OV will go HIGH, to indicate that the data present is no longer valid. This pipelining
effect provides the user with 100% bus utilization, and brings about the possibility
that a “NULL” queue may be required within a multi-queue device. Null queue
operation is discussed in the next section. Remember that OE allows the user
to place the data output bus (Qout) into High-Impedance and the data can be
read in to the output register regardless of OE.
Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures
13, 15, and 16 for read queue selection and read port operation timing diagrams.
PACKET MODE OPERATION (PKT = HIGH on Master Reset)
The Packet mode operation provides the capability where, user defined
packets or frames can be written to the device as opposed to Standard mode
where individual words are written. For clarification, in Packet Mode, a packet
can be written to the device with the starting location designated as Transmit Start
of Packet (TSOP) and the ending location designated as Transmit End of Packet
(TEOP). In conjunction, a packet read from the device will be designated as
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
Operation RCLK
RADEN
ESTR
Null-Q
Read Queue
Select
1
0
0
PAEn/PRn
Quadrant
Select
0
1
0
Null Queue
Select
1
0
1
RDADD[7:0]
7 6 5
4 3 2
1 0
Device Select Read Queue Address
(Compared to (5 bits = 32 Queues)
ID0,1,2)
Quadrant
Address
00
01
10
11
7 6 5
Device Select
(Compared to
ID0,1,2)
4 3 2
X
X
X
1 0
Quadrant
Address
7 6 5
4 3 2
1 0
X
X
X
X
X
X
X
X
Queue Status on PAEn/PRn Bus
Q0 : Q7 → PAE0 : PAE7
Q8 : Q15 → PAE0 : PAE7
Q16 : Q23 → PAE0 : PAE7
Q24 : Q31 → PAE0 : PAE7
5998 drw06
21
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Receive Start of Packet (RSOP) and a Receive End of Packet (REOP). The
minimum size for a packet is four words (SOP, two words of data and EOP). The
almost empty flag bus becomes the “Packet Ready” PR flag bus when the device
is configured for packet mode. Valid packets are indicated when both PR and
OV are asserted.
WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)
It is required that a full packet be written to a queue before moving to a different
queue. The device requires three cycles to change queues. Packet mode, has
2 restrictions: <1> An extra word (or filler word) is required to be written after
each packet on the cycle following the queue change to ensure the RSOP in
the old queue is not read out on a queue change because of the first word fall
through. <2> No SOP/EOP is allowed to read/written at cycle (“D” or “K”) the
second cycle after a queue change. In this mode, the write port may not obtain
100% bus utilization.
Changing queues requires a minimum of 3 WCLK cycles on the write port
(see Figure 17, Writing in Packet Mode during a Queue Change). WADEN
goes high signaling a change of queue (clock cycle “B” or “I”). The address
on WRADD at the rising edge of WCLK determines the next queue. Data
presented on Din during that cycle (“B” or “I”) and the next cycle (“C” or “J”)
can continue to be written to the active (old) queue (QA or QB respectively),
provided WEN is LOW (active). If WEN is HIGH (inactive) for these two clock
cycles (H), data will not be written in to the previous queue (QA). The second
cycle following a request for queue change (“D” or “K”) will require a “filler” word
to be written to the device. This can be done by clocking the TEOP twice or by
writing a “filler” word. In packet mode, the multi-queue is designed under the
2 restrictions listed previously. Note, an erroneous Packet Ready flag may occur
if the EOP or SOP marker shows up at the second cycle after a queue change.
To prevent an erroneous Packet Ready flag from occurring a filler word should
be written into the old queue at the last clock cycle of writing. It is important to know
that no SOP or EOP may be written into the device during this cycle (“D” or “K”).
The write port discrete full flag will update to show the full status of the newly
selected queue (QB) at this last cycle’s rising edge (“D” or “K”). Data values
presented on the data input bus (Din), can be written into the newly selected
queue (QX) on the rising edge of WCLK on the third cycle (“E”) following a request
for change of queue, provided WEN is LOW (active) and the new queue is not
full. If a selected queue is full (FF is LOW), then writes to that queue will be
prevented. Note, data cannot be written into a full queue.
Refer to Figure 17, Writing in Packet Mode during a Queue Change and
Figure 19, Data Input (Transit) Packet Mode of Operation for timing diagrams.
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
In packet Mode it is required that a full packet is read from a queue before
moving to a different queue. The device requires three cycles to change queues.
In Packet Mode, there are 2 restrictions <1> An extra word (or filler word) should
have been inserted into the data stream after each packet to insure the RSOP
in the old queue is not read out on a queue change because of the first word
fall through and this word should be discarded. <2> No EOP/SOP is allowed
to be read/written at cycle (“D” or “K”) the second cycle after a queue change).
In this mode, the read port may not obtain 100% bus utilization.
Changing queues requires a minimum of 3 RCLK cycles on the read port (see
Figure 18, Reading in Packet Mode during a Queue Change). RADEN goes
high signaling a change of queue (clock cycle “B” or “I”). The address on
RDADD at the rising edge of RCLK determines the queue. As illustrated in Figure
18 during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue
to be read from the active (old) queue (QA or QB respectively), provided both
REN and OE are LOW (active) simultaneously with changing queues. REOP
for packet located in queue (QA) must be read on or before a queue change
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
request is made (“C” or “J”). If REN is HIGH (inactive) for these two clock cycles,
data will not be read from the previous queue (QA). In applications where the
multi-queue flow-control device is connected to a shared bus, an output enable,
OE control pin is also provided to allow High-Impedance selection of the data
outputs (Qout). With reference to Figure 18 when changing queues, a packet
marker (SOP or EOP) should not be read on cycle (“E” or “L”). Reading a SOP
or EOP should not occur during the cycles required for a queue change. It is
also recommended that a queue change should not occur once the reading of
the packet has commenced, The EOP marker of the packet prior to a queue
change should be read on or before the queue change. If the EOP word is read
before a queue change, REN can be pulled high to disable further reads. When
the queue change is initiated, the filler word written into the current queue after
the EOP word will fall through followed by and the first word from the new queue.
Refer to Figure 18, Reading in Packet Mode during a Queue Change as
well as Figures 13, 15, and 16 for timing diagrams and Table 2, for Read Address
bus arrangement.
Note, the almost empty flag bus becomes the “Packet Ready” flag bus when
the device is configured for packet ready mode. .
PACKET READY FLAG
The 36-bit multi-queue flow-control device provides the user with a Packet
Ready feature. During a Master Reset the logic “1” (HIGH) on the PKT input
signal (packet mode select), configures the device in packet mode. The PR
discrete flag, provides a packet ready status of the active queue selected on the
read port. A packet ready status is individually maintained on all queues;
however only the queue selected on the read port has its packet ready status
indicated on the PR output flag. A packet is available on the output for reading
when both PR and OV are asserted LOW. If less than a full packet is available,
the PR flag will be HIGH (packet not ready). In packet mode, no words can be
read from a queue until a complete packet has been written into that queue,
regardless of REN.
When packet mode is selected the Programmable Almost Empty bus, PAEn,
becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM =
LOW during a master reset), the PRn bus provides packet ready status in 8
queue increments. The PRn bus supports either Polled or Direct modes of
operation. The PRn mode of operation is configured through the Flag Mode
(FM) bit during a Master Reset.
When the multi-queue is configured for packet mode operation, the device
must also be configured for 36 bit write data bus and 36 bit read data bus. The
two most significant bits of the 36-bit data bus are used as “packet markers”. On
the write port these are bits D34 (Transmit Start of Packet,) D35 (Transmit End
of Packet) and on the read port Q34, Q35. All four bits are monitored by the packet
control logic as data is written into and read out from the queues. The packet
ready status for individual queues is then determined by the packet ready logic.
On the write port D34 is used to “mark” the first word being written into the
selected queue as the “Transmit Start of Packet”, TSOP. To further clarify, when
the user requires a word being written to be marked as the start of a packet, the
TSOP input (D34) must be HIGH for the same WCLK rising edge as the word
that is written. The TSOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
On the write port D35 is used to “mark” the last word of the packet currently
being written into the selected queue as the “Transmit End of Packet” TEOP.
When the user requires a word being written to be marked as the end of a packet,
the TEOP input must be HIGH for the same WCLK rising edge as the word that
is written in. The TEOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
The packet ready logic monitors all start and end of packet markers both as
they enter respective queues via the write port and as they exit queues via the
22
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYTE D
TMOD1 (D33)
RMOD1 (Q33)
0
0
1
1
BYTE C
TMOD2 (D32)
RMOD2 (Q32)
0
1
0
1
D0/Q0
D7/Q7
D15/Q15
D23/Q23
D31/Q31
MOD 2 D32/Q32
D34/Q34
SOP
MOD 1 D33/Q33
D35/Q35
EOP
TABLE 5 — PACKET MODE VALID BYTE
BYTE B
BYTE A
VALID BYTES
A, B, C, D
A
A, B
A, B, C
5998 drw07
NOTE:
Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
of packet. This is a useful feature when due to latencies within the system,
monitoring the REOP marker alone does not prevent “over reading” of the data
from the queue selected. For example, an AEOP marker set 4 writes before the
TEOP marker provides the device connected to the read port with and “almost
end of packet” indication 4 cycles before the end of packet.
The AEOP can be set any number of words before the end of packet
determined by user requirements or latencies involved in the system.
See Figure 18, Reading in Packet Mode during a Queue Change, Figure
19, Data Input (Transmit) Packet Mode of Operation and Figure 20, Data
Output (Receive) Packet Mode of Operation.
read port. The multi-queue internal logic increments and decrements a packet
counter, which is provided for each queue. The functionality of the packet ready
logic provides status as to whether at least one full packet of data is available
within the selected queue. A partial packet in a queue is regarded as a packet
not ready and PR (active LOW) will be HIGH. In Packet mode, no words can
be read from a queue until at least one complete packet has been written into
the queue, regardless of REN. For example, if a TSOP has been written and
some number of words later a TEOP is written a full packet of data is deemed
to be available, and the PR flag and OV will go active LOW. Consequently if reads
begin from a queue that has only one complete packet and the RSOP is detected
on the output port as data is being read out, PR will go inactive HIGH. OV will
remain LOW indicating there is still valid data being read out of that queue until
the REOP is read. The user may proceed with the reading operation until the
current packet has been read out and no further complete packets are available.
If during that time another complete packet has been written into the queue and
the PR flag will again gone active, then reads from the new packet may follow
after the current packet has been completely read out.
The packet counters therefore look for start of packet markers followed by end
of packet markers and regard data in between the TSOP and TEOP as a full
packet of data. The packet monitoring has no limitation as to how many packets
are written into a queue, the only constraint is the depth of the queue. Note, there
is a minimum allowable packet size of four words, inclusive of the TSOP marker
and TEOP marker.
The packet logic does expect a TSOP marker to be followed by a TEOP
marker.
If a second TSOP marker is written after a first, it is ignored and the logic
regards data between the first TSOP and the first subsequent TEOP as the full
packet. The same is true for TEOP; a second consecutive TEOP mark is ignored.
On the read side the user should regard a packet as being between the first
RSOP and the first subsequent REOP and disregard consecutive RSOP
markers and/or REOP markers. This is why a TEOP may be written twice, using
the second TEOP as the “filler” word.
As an example, the user may also wish to implement the use of an “Almost
End of Packet” (AEOP) marker. For example, the AEOP can be assigned to
data input bit D33. The purpose of this AEOP marker is to provide an indicator
that the end of packet is a fixed (known) number of reads away from the end
PACKET MODE – MODULO OPERATION
The internal packet ready control logic performs no operation on these
modulo bits, they are only informational bits that are passed through with the
respective data byte(s).
When utilizing the multi-queue flow-control device in packet mode, the user
may also want to consider the implementation of “Modulo” operation or “valid
byte marking”. Modulo operation may be useful when the packets being
transferred through a queue are in a specific byte arrangement even though
the data bus width is 36 bits. In Modulo operation the user can concatenate bytes
to form a specific data string through the multi-queue device. A possible scenario
is where a limited number of bytes are extracted from the packet for either
analysis or filtered for security protection. This will only occur when the first 36
bit word of a packet is written in and the last 36 bit word of packet is written in.
The modulo operation is a means by which the user can mark and identify specific
data within the Queue.
On the write port data input bits, D32 (transmit modulo bit 2, TMOD2) and D33
(transmit modulo bit 1, TMOD1) can be used as data markers. An example of
this could be to use D32 and D33 to code which bytes of a word are part of the
packet that is also being marked as the “Start of Marker” or “End of Marker”.
Conversely on the read port when reading out these marked words, data
outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo bit 1,
RMOD1) will pass on the byte validity information for that word. Refer to Table
5 for one example of how the modulo bits may be setup and used. See Figure
19, Data Input (Transmit) Packet Mode of Operation and Figure 20, Data
Output (Receive) Packet Mode of Operation.
23
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
NULL QUEUE OPERATION (OF THE READ PORT)
Pipelining of data to the output port enables the device to provide 100% bus
utilization in standard mode. Data can be read out of the multi-queue flow-control
device on every RCLK cycle regardless of queue switches or other operations.
The device architecture is such that the pipeline is constantly filled with the next
words in a selected queue to be read out, again providing 100% bus utilization.
This type of architecture does assume that the user is constantly switching
queues such that during a queue switch, the last data word required from the
previous queue will fall through the pipeline to the output.
Note, that if reads cease at the empty boundary of a queue, then the last word
will automatically flow through the pipeline to the output.
The Null Q operation is achieved by setting the Null Q signal HIGH during
a queue select. Note that the read address bus RDADD[7:0] is a don't care. The
Null Queue is a separate queue within the device and thus the maximum number
of queues and memory is always available regardless of whether or not the Null
queue is used. Also note that in expansion mode a user may want to use a
dedicated null queue for each device. A null queue can be selected when no
further reads are required from a previously selected queue. Changing to a null
queue will continue to propagate data in the pipeline to the previous queue's
output. The Null Q can remain selected until a data becomes available in another
queue for reading. The Null-Q can be utilized in either standard or packet mode.
Note: If the user switches the read port to the null queue, this queue is seen
as and treated as an empty queue, therefore after switching to the null queue
the last word from the previous queue will remain in the output register and the
OV flag will go HIGH, indicating data is not valid.
The Null queue operation only has significance to the read port of the multiqueue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 21, Read Operation and Null Queue Select for diagram.
PAFn FLAG BUS OPERATION
The IDT72T51546/72T51556 multi-queue flow-control device can be
configured for up to 32 queues, each queue having its own almost full status.
An active queue has its flag status output to the discrete flags, FF and PAF, on
the write port. Queues that are not selected for a write operation can have their
PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide, so
that 8 queues at a time can have their status output to the bus. If 9 or more queues
are setup within a device then there are 2 methods by which the device can share
the bus between queues, “Direct” mode and “Polled” mode depending on the
state of the FM (Flag Mode) input during a Master Reset. If 8 or less queues
are setup within a device then each will have its own dedicated output from the
bus. If 8 or less queues are setup in single device mode, it is recommended to
configure the PAFn bus to polled mode as it does not require using the write
address (WRADD).
EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES
Expansion can take place using either the standard mode or the packet mode.
In the 32 queue multi-queue device, the WRADD address bus is 8 bits wide.
The 5 Least Significant bits (LSbs) are used to address one of the 32 available
queues within a single multi-queue device. The 3 Most Significant bits (MSbs)
are used when a device is connected in expansion mode with up to 8 devices
connected in width expansion, each device having its own 3-bit address. When
logically expanded with multiple parts, each device is statically setup with a
unique chip ID code on the ID pins, ID0, ID1, and ID2. A device is selected when
the 3 Most Significant bits of the WRADD address bus matches a 3-bit ID code.
The maximum logical expansion is 256 queues (32 queues x 8 devices) or a
minimum of 8 queues (1 queue per device x 8 devices), each of the maximum
size of the individual memory device.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Note: The WRADD bus is also used in conjunction with FSTR (almost full flag
bus strobe), to address the almost full flag bus during direct mode of operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
12, Full Flag Timing Expansion Mode, Figure 14, Output Valid Flag Timing (In
Expansion Mode), and Figure 35, Multi-Queue Expansion Diagram, for timing
diagrams.
BUS MATCHING OPERATION
Bus Matching operation between the input port and output port is available.
During a master reset of the multi-queue the state of the three setup pins, BM
(Bus Matching), IW (Input Width) and OW (Output Width) determine the input and
output port bus widths as per the selections shown in Table 3, “Bus Matching
Set-Up”. 9 bit bytes, 18 bit words and 36 bit long words can be written into and
read from the Queues provided that at least one of the ports is setup for x36
operation. When writing to or reading from the multi-queue in a bus matching
mode, the device orders data in a “Little Endian” format. See Figure 4, Bus
Matching Byte Arrangement for details.
The Full flag and Almost Full flag operation is always based on writes and
reads of data widths determined by the write port width. For example, if the input
port is x36 and the output port is x9, then four data reads from a full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
Output Valid flag and Almost Empty flag operations are always based on writes
and reads of data widths determined by the read port. For example, if the input
port is x18 and the output port is x36, two write operations will be required to
cause the output valid flag of an empty queue to go LOW, output valid (queue
is not empty).
Note, that the input port serves all queues within a device, as does the output
port, therefore the input bus width to all queues is equal (determined by the input
port size) and the output bus width from all queues is equal (determined by the
output port size).
TABLE 3 — BUS-MATCHING SET-UP
BM
IW
x36 DEVICE
OW
Write Port
Read Port
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
FULL FLAG OPERATION
The multi-queue flow-control device provides a single Full Flag output, FF.
The FF flag output provides a full status of the queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the full condition of all queues within it, however
only the queue that is selected for write operations has its full status output to the
FF flag. This dedicated flag is often referred to as the “active queue full flag”.
When queue switches are being made on the write port, the FF flag output
will switch to the new queue and provide the user with the new queue status,
on the cycle after a new queue selection is made. The user then has a full status
for the new queue one cycle ahead of the WCLK rising edge that data can be
written into the new queue. That is, a new queue can be selected on the write
port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the
second rising edge of WCLK, the FF flag output will show the full status of the
newly selected queue. On the third rising edge of WCLK following the queue
selection, data can be written into the newly selected queue provided that data
and enable setup & hold times are met.
24
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Note, the FF flag will provide status of a newly selected queue two WCLK cycle
after queue selection, which is one cycle before data can be written to that queue.
This prevents the user from writing data to a queue that is full, (assuming that
a queue switch has been made to a queue that is actually full).
The FF flag is synchronous to the WCLK and all transitions of the FF flag occur
based on a rising edge of WCLK. Internally the multi-queue device monitors and
keeps a record of the full status for all queues. It is possible that the status of a
FF flag maybe changing internally even though that flag is not the active queue
flag (selected on the write port). A queue selected on the read port may
experience a change of its internal full flag status based on read operations.
See Figure 10, Write Queue Select, Write Operation and Full Flag
Operation and Figure 12, Full Flag Timing in Expansion Mode for timing
information.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
When a queue selection is made the first data from that queue will appear on
the Qout data outputs 3 RCLK cycles later, the OV will change state to indicate
validity of the data from the newly selected queue on this 3rd RCLK cycle also.
The previous cycles will continue to output data from the previous queue and
the OV flag will indicate the status of those outputs. Again, the OV flag always
indicates status for the data currently present on the output register.
The OV flag is synchronous to the RCLK and all transitions of the OV flag occur
based on a rising edge of RCLK. Internally the multi-queue device monitors and
keeps a record of the output valid (empty) status for all queues. It is possible that
the status of an OV flag may be changing internally even though that respective
flag is not the active queue flag (selected on the read port). A queue selected
on the write port may experience a change of its internal OV flag status based
on write operations, that is, data may be written into that queue causing it to
become “not empty”.
See Figure 13, Read Queue Select, Read Operation and Figure 14, Output
Valid Flag Timing for details of the timing.
EXPANSION MODE - FULL FLAG OPERATION
When multi-queue devices are connected in Expansion mode the FF flags
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices write port only looks at a
single FF flag (as opposed to a discrete FF flag for each device). This FF flag
is only pertinent to the queue being selected for write operations at that time.
Remember, that when in expansion mode only one multi-queue device can be
written to at any moment in time, thus the FF flag provides status of the active
queue on the write port.
This connection of flag outputs to create a single flag requires that the FF flag
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the FF flag bus and all other FF flag outputs
connected to the FF flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
device will automatically place its FF flag output into High-Impedance when none
of its queues are selected for write operations.
When queues within a single device are selected for write operations, the FF
flag output of that device will maintain control of the FF flag bus. Its FF flag will
simply update between queue switches to show the respective queue full
status.
The multi-queue device places its FF flag output into High-Impedance based
on the 3 bit ID code found in the 3 most significant bits of the write queue address
bus, WRADD. If the 3 most significant bits of WRADD match the 3 bit ID code setup
on the static inputs, ID0, ID1 and ID2 then the FF flag output of the respective
device will be in a Low-Impedance state. If they do not match, then the FF flag
output of the respective device will be in a High-Impedance state. See Figure
12, Full Flag Timing in Expansion Mode for details of flag operation, including
when more than one device is connected in expansion.
EXPANSION MODE – OUTPUT VALID FLAG OPERATION
When multi-queue devices are connected in Expansion mode, the OV flags
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices read port only looks at a
single OV flag (as opposed to a discrete OV flag for each device). This OV flag
is only pertinent to the queue being selected for read operations at that time.
Remember, that when in expansion mode only one multi-queue device can be
read from at any moment in time, thus the OV flag provides status of the active
queue on the read port.
This connection of flag outputs to create a single flag requires that the OV flag
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the OV flag bus and all other OV flag outputs
connected to the OV flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
device will automatically place its OV flag output into High-Impedance when none
of its queues are selected for read operations.
When queues within a single device are selected for read operations, the OV
flag output of that device will maintain control of the OV flag bus. Its OV flag will
simply update between queue switches to show the respective queue output
valid status.
The multi-queue device places its OV flag output into High-Impedance based
on the 3 bit ID code found in the 3 most significant bits of the read queue address
bus, RDADD. If the 3 most significant bits of RDADD match the 3 bit ID code setup
on the static inputs, ID0, ID1 and ID2 then the OV flag output of the respective
device will be in a Low-Impedance state. If they do not match, then the OV flag
output of the respective device will be in a High-Impedance state. See Figure
14, Output Valid Flag Timing for details of flag operation, including when more
than one device is connected in expansion.
OUTPUT VALID FLAG OPERATION
The multi-queue flow-control device provides a single Output Valid flag
output, OV. The OV provides an empty status or data output valid status for the
data word currently available on the output register of the read port. The rising
edge of an RCLK cycle that places new data onto the output register of the read
port, also updates the OV flag to show whether or not that new data word is
actually valid. Internally the multi-queue flow-control device monitors and
maintains a status of the empty condition of all queues within it, however only
the queue that is selected for read operations has its output valid (empty) status
output to the OV flag, giving a valid status for the word being read at that time.
The nature of the first word fall through operation means that when the last
data word is read from a selected queue, the OV flag will go HIGH on the next
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
When queue switches are being made on the read port, the OV flag will switch
to show status of the new queue in line with the data output from the new queue.
ALMOST FULL FLAG
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Full flag output, PAF. The PAF flag output provides
a status of the almost full condition for the active queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the almost full condition of all queues within
it, however only the queue that is selected for write operations has its full status
output to the PAF flag. This dedicated flag is often referred to as the “active queue
almost full flag”. The position of the PAF flag boundary within a queue can be
at any point within that queues depth. This location can be user programmed
via the serial port or one of the default values (8 or 128) can be selected if the
user has performed default programming.
25
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
As mentioned, every queue within a multi-queue device has its own almost
full status, when a queue is selected on the write port, this status is output via the
PAF flag. The PAF flag value for each queue is programmed during multi-queue
device programming (along with the number of queues, queue depths and
almost empty values). The PAF offset value, m, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAF value of different queues within the same device
can be different values.
When queue switches are being made on the write port, the PAF flag output
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same WCLK cycle
that data can actually be written to the new queue. That is, a new queue can
be selected on the write port via the WRADD bus, WADEN enable and a rising
edge of WCLK. On the third rising edge of WCLK following a queue selection,
the PAF flag output will show the full status of the newly selected queue. The PAF
is flag output is triple register buffered, so when a write operation occurs at the
almost full boundary causing the selected queue status to go almost full the PAF
will go LOW 3 WCLK cycles after the write. The same is true when a read occurs,
there will be a 3 WCLK cycle delay after the read operation.
So the PAF flag delays are:
from a write operation to PAF flag LOW is 2 WCLK + tWAF
The delay from a read operation to PAF flag HIGH is tSKEW2 + WCLK + tWAF
Note, if tSKEW is violated there will be one added WCLK cycle delay.
The PAF flag is synchronous to the WCLK and all transitions of the PAF flag
occur based on a rising edge of WCLK. Internally the multi-queue device
monitors and keeps a record of the almost full status for all queues. It is possible
that the status of a PAF flag maybe changing internally even though that flag is
not the active queue flag (selected on the write port). A queue selected on the
read port may experience a change of its internal almost full flag status based
on read operations. The multi-queue flow-control device also provides a
duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 23 and 24 for Almost Full flag timing and queue switching.
ALMOST EMPTY FLAG
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Empty flag output, PAE. The PAE flag output
provides a status of the almost empty condition for the active queue currently
selected on the read port for read operations. Internally the multi-queue flowcontrol device monitors and maintains a status of the almost empty condition of
all queues within it, however only the queue that is selected for read operations
has its empty status output to the PAE flag. This dedicated flag is often referred
to as the “active queue almost empty flag”. The position of the PAE flag boundary
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
As mentioned, every queue within a multi-queue device has its own almost
empty status, when a queue is selected on the read port, this status is output via
the PAE flag. The PAE flag value for each queue is programmed during multiqueue device programming (along with the number of queues, queue depths
and almost full values). The PAE offset value, n, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAE value of different queues within the same device
can be different values.
When queue switches are being made on the read port, the PAE flag output
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same RCLK cycle
that data actually falls through to the output register from the new queue. That
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
is, a new queue can be selected on the read port via the RDADD bus, RADEN
enable and a rising edge of RCLK. On the third rising edge of RCLK following
a queue selection, the data word from the new queue will be available at the
output register and the PAE flag output will show the empty status of the newly
selected queue. The PAE is flag output is triple register buffered, so when a read
operation occurs at the almost empty boundary causing the selected queue
status to go almost empty the PAE will go LOW 3 RCLK cycles after the read.
The same is true when a write occurs, there will be a 3 RCLK cycle delay after
the write operation.
So the PAE flag delays are:
from a read operation to PAE flag LOW is 2 RCLK + tRAE
The delay from a write operation to PAE flag HIGH is tSKEW2 + RCLK + tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
The PAE flag is synchronous to the RCLK and all transitions of the PAE flag
occur based on a rising edge of RCLK. Internally the multi-queue device
monitors and keeps a record of the almost empty status for all queues. It is possible
that the status of a PAE flag maybe changing internally even though that flag is
not the active queue flag (selected on the read port). A queue selected on the
write port may experience a change of its internal almost empty flag status based
on write operations. The multi-queue flow-control device also provides a
duplicate of the PAE flag on the PAE[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 25 and 26 for Almost Empty flag timing and queue switching.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN and REN signals must be disabled for a minimum of four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired powerdowntime.
During power down, the following conditions for the inputs/outputs signals are:
• All data in Queue(s) memory are retained.
• All data inputs become inactive.
• All write and read pointers maintain their last value before power down.
• All enables, chip selects, and clock input pins become inactive.
• All data outputs become inactive and enter high-impedance state.
• All flag outputs will maintain their current states before power down.
• All programmable flag offsets maintain their values.
• All echo clocks and enables will become inactive and enter highimpedance state.
• The serial programming and JTAG port will become inactive and enter
high-impedance state.
• All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and freerunning during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a minimum of 1µs waiting period before
read and write operations can resume. The device will continue from where it
had stopped and no form of reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to VCC or GND. See Figure 34, Power Down Operation,
for the associated timing diagram.
26
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
I/O Set-Up
Output Valid, OV Flag Boundary
OV Boundary Condition
I/O Set-Up
Full Flag, FF Boundary
FF Boundary Condition
In36 to out36 (Almost Empty Mode)
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 1 below for timing)
In36 to out36
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(see note below for timing)
In36 to out36 (Packet Mode)
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 2 below for timing)
In36 to out36
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In36 to out18
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 1 below for timing)
In36 to out18
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In36 to out9
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 1 below for timing)
In36 to out18
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In18 to out36
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 1 below for timing)
In36 to out9
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In9 to out36
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note 1 below for timing)
In36 to out9
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In18 to out36
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(see note below for timing)
In18 to out36
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(see note below for timing)
In9 to out36
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 4) Writes
(see note below for timing)
In9 to out36
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after (D x 4) Writes
(see note below for timing)
NOTE:
1. OV Timing
Assertion:
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
Read Operation to OV HIGH: tROV
2. OV Timing when in Packet Mode (36 in to 36 out only)
Assertion:
Write to OV LOW: tSKEW4 + RCLK + tROV
If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV
De-assertion:
Read Operation to OV HIGH: tROV
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
in36 to out36
PAF/PAFn Goes LOW after
(Both ports selected for same queue when the 1st D+1-m Writes
Word is written in until the boundary is reached) (see note below for timing)
in36 to out36
PAF/PAFn Goes LOW after
(Write port only selected for same queue when the D-m Writes
1st Word is written in until the boundary is reached) (see note below for timing)
in36 to out18
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
in36 to out9
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
in18 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(see note below for timing)
in9 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 4) Writes
(see note below for timing)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
27
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up
PAE Assertion
I/O Set-Up
PAEn Boundary Condition
in36 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
PAE Goes HIGH after n+2
Writes
(see note below for timing)
in36 to out18
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
PAE Goes HIGH after n+1
Writes
(see note below for timing)
in36 to out9
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
PAE Goes HIGH after n+1
Writes
(see note below for timing)
in36 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
in36 to out36
(Write port only selected for same queue when the
1st Word is written in until the boundary is reached)
in36 to out18
in18 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
PAE Goes HIGH after
([n+2] x 2) Writes
(see note below for timing)
in9 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
PAE Goes HIGH after
([n+2] x 4) Writes
(see note below for timing)
PAEn Goes HIGH after
n+2 Writes
(see note below for timing)
PAEn Goes HIGH after
n+1 Writes
(see note below for timing)
PAEn Goes HIGH after n+1
Writes (see below for timing)
PAEn Goes HIGH after n+1
Writes (see below for timing)
PAEn Goes HIGH after
([n+2] x 2) Writes
(see note below for timing)
PAEn Goes HIGH after
([n+1] x 2) Writes
(see note below for timing)
PAEn Goes HIGH after
([n+2] x 4) Writes
(see note below for timing)
PAEn Goes HIGH after
([n+1] x 4) Writes
(see note below for timing)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE Timing
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
in36 to out9
in18 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
in18 to out36
(Write port only selected for same queue when the
1st Word is written in until the boundary is reached)
in9 to out36
(Both ports selected for same queue when the 1st
Word is written in until the boundary is reached)
in9 to out36
(Write port only selected for same queue when the
1st Word is written in until the boundary is reached)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
PACKET READY FLAG BUS, PRn BOUNDARY
Assertion:
Both the rising and falling edges of PRn are synchronous to RCLK.
PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4
+ 2 RCLK* + tPAE
If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE
*If a queue switch is occurring on the read port at the point of flag assertion there
may be one additional RCLK clock cycle delay.
De-assertion:
PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
3 RCLK* + tPAE
*If a queue switch is occurring on the read port at the point of flag assertion or
de-assertion there may be one additional RCLK clock cycle delay.
PACKET READY FLAG, PR BOUNDARY
Assertion:
Both the rising and falling edges of PR are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4
+ 2 RCLK + tPR
If tSKEW4 is violated:
PR goes LOW after tSKEW4 + 3 RCLK + tPR
(Please refer to Figure 19, Data Input (Transmit) Packet Mode of Operation,
for timing diagram).
De-assertion:
PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
3 RCLK + tPR
(Please refer to Figure 20, Data Output (Receive) Packet Mode of Operation
for timing diagram).
28
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PAFn - DIRECT BUS
If FM is LOW at master reset then the PAFn bus operates in Direct
(addressed) mode. In direct mode the user can address the quadrant of
queues they require to be placed on to the PAFn bus. For example, consider
the operation of the PAFn bus when 26 queues have been setup. To output
status of the first quadrant, Queue[0:7] the WRADD bus is used in conjunction
with the FSTR (PAF flag strobe) input and WCLK. The address present on the
2 least significant bits of the WRADD bus with FSTR HIGH will be selected as
the quadrant address on a rising edge of WCLK. So to address quadrant 1,
Queue[0:7] the WRADD bus should be loaded with “xxxxxx00”, the PAFn bus
will change status to show the new quadrant selected 1 WCLK cycle after
quadrant selection. PAFn[0:7] gets status of queues, Queue[0:7] respectively.
To address the second quadrant, Queue[8:15], the WRADD address is
“xxxxxx01”. PAFn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the WRADD address is “xxxxxx10”.
PAF[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the WRADD address is “xxxxxx11”. PAF[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs PAF[2:7] will
be don't care states.
Note, that if a read or write operation is occurring to a specific queue, say
queue ‘x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra WCLK cycle delay before that queues status
is correctly shown on the respective output of the PAFn bus. However, the
active PAF flag will show correct status at all times.
Quadrants can be selected on consecutive clock cycles, that is the quadrant
on the PAFn bus can change every WCLK cycle. Also, data present on the
input bus, Din, can be written into a Queue on the same WCLK rising edge that
a quadrant is being selected, the only restriction being that a write queue
selection and PAFn quadrant selection cannot be made on the same cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their PAF status
output on PAF[0:7] constantly.
When the multi-queue devices are connected in expansion of more than one
device the PAFn busses of all devices are connected together, when switching
between quadrants of different devices the user must utilize the 3 most significant
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
Please refer to Figure 29 PAFn - Direct Mode Quadrant Selection for timing
information. Also refer to Table 1, Write Address Bus, WRADD.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
devices hold their PAFn outputs in High-Impedance. When the master device
has cycled all of its quadrants it passes a token to the next device in the chain
and that device assumes control of the PAFn bus and then cycles its quadrants
and so on, the PAFn bus control token being passed on from device to device.
This token passing is done via the FXO outputs and FXI inputs of the devices
(“PAF Expansion Out” and “PAF Expansion In”). The FXO output of the master
device connects to the FXI of the second device in the chain and the FXO of
the second connects to the FXI of the third and so on. The final device in a chain
has its FXO connected to the FXI of the first device, so that once the PAFn bus
has cycled through all quadrants of all devices, control of the PAFn will pass
to the master device again and so on. The FSYNC of each respective device
will operate independently and simply indicate when that respective device has
taken control of the bus and is placing its first quadrant on to the PAFn bus.
When operating in single device mode the FXI input must be connected to
the FXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAFn bus.
Please refer to Figure 32, PAFn Bus – Polled Mode for timing information.
PAEn/PRn FLAG BUS OPERATION
The IDT72T51546/72T51556 multi-queue flow-control device can be
configured for up to 32 queues, each queue having its own almost empty/
packet ready status. An active queue has its flag status output to the discrete
flags, OV, PAE and PR, on the read port. Queues that are not selected for a
read operation can have their PAE/PR status monitored via the PAEn/PRn bus.
The PAEn/PRn flag bus is 8 bits wide, so that 8 queues at a time can have their
status output to the bus. If 9 or more queues are setup within a device then there
are 2 methods by which the device can share the bus between queues, "Direct"
mode and "Polled" mode depending on the state of the FM (Flag Mode) input
during a Master Reset. If 8 or less queues are setup within a device then each
will have its own dedicated output from the bus. If 8 or less queues are setup
in single device mode, it is recommended to configure the PAFn bus to polled
mode as it does not require using the write address (WRADD).
PAEn/PRn - DIRECT BUS
If FM is LOW at master reset then the PAEn/PRn bus operates in Direct
(addressed) mode. In direct mode the user can address the quadrant of
queues they require to be placed on to the PAEn/PRn bus. For example,
consider the operation of the PAEn/PRn bus when 26 queues have been
setup. To output status of the first quadrant, Queue[0:7] the RDADD bus is used
in conjunction with the ESTR (PAE/PR flag strobe) input and RCLK. The
address present on the 2 least significant bits of the RDADD bus with ESTR
HIGH will be selected as the quadrant address on a rising edge of RCLK. So
to address quadrant 1, Queue[0:7] the RDADD bus should be loaded with
“xxxxxx00”, the PAEn/PRn bus will change status to show the new quadrant
selected 1 RCLK cycle after quadrant selection. PAEn[0:7] gets status of
queues, Queue[0:7] respectively.
To address the second quadrant, Queue[8:15], the RDADD address is
“xxxxxx01”. PAEn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the RDADD address is “xxxxxx10”.
PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the RDADD address is “xxxxxx11”. PAE[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs PAE[2:7] will
be don't care states.
Note, that if a read or write operation is occurring to a specific queue, say
queue ‘x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra RCLK cycle delay before that queues status
is correctly shown on the respective output of the PAEn/PRn bus.
PAFn – POLLED BUS
If FM is HIGH at master reset then the PAFn bus operates in Polled (looped)
mode. In polled mode the PAFn bus automatically cycles through the 4
quadrants within the device regardless of how many queues have been setup
in the part. Every rising edge of the WCLK causes the next quadrant to be
loaded on the PAFn bus. The device configured as the master (MAST input
tied HIGH), will take control of the PAFn after MRS goes LOW. For the whole
WCLK cycle that the first quadrant is on PAFn the FSYNC (PAFn bus sync)
output will be HIGH, for all other quadrants, this FSYNC output will be LOW.
This FSYNC output provides the user with a mark with which they can
synchronize to the PAFn bus, FSYNC is always HIGH for the WCLK cycle that
the first quadrant of a device is present on the PAFn bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST
tied LOW. The master device is the first device to take control of the PAFn bus
and will place its first quadrant on the bus on the rising edge of WCLK after the
MRS input goes HIGH. For the next 3 WCLK cycles the master device will
maintain control of the PAFn bus and cycle its quadrants through it, all other
29
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
can synchronize to the PAEn/PRn bus, ESYNC is always HIGH for the RCLK
cycle that the first quadrant of a device is present on the PAEn/PRn bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the PAEn/PRn bus
and will place its first quadrant on the bus on the rising edge of RCLK after the
MRS input goes LOW. For the next 3 RCLK cycles the master device will maintain
control of the PAEn/PRn bus and cycle its quadrants through it, all other devices
hold their PAEn/PRn outputs in High-Impedance. When the master device has
cycled all of its quadrants it passes a token to the next device in the chain and
that device assumes control of the PAEn/PRn bus and then cycles its quadrants
and so on, the PAEn/PRn bus control token being passed on from device to
device. This token passing is done via the EXO outputs and EXI inputs of the
devices (“PAE Expansion Out” and “PAE Expansion In”). The EXO output of
the master device connects to the EXI of the second device in the chain and the
EXO of the second connects to the EXI of the third and so on. The final device
in a chain has its EXO connected to the EXI of the first device, so that once the
PAEn/PRn bus has cycled through all quadrants of all devices, control of the
PAEn/PRn will pass to the master device again and so on. The ESYNC of each
respective device will operate independently and simply indicate when that
respective device has taken control of the bus and is placing its first quadrant
on to the PAEn/PRn bus.
When operating in single device mode the EXI input must be connected to
the EXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAEn bus.
Please refer to Figure 33, PAEn/PRn Bus – Polled Mode for timing information.
Quadrants can be selected on consecutive clock cycles, that is the quadrant
on the PAEn/PRn bus can change every RCLK cycle. Also, data can be read
out of a Queue on the same RCLK rising edge that a quadrant is being selected,
the only restriction being that a read queue selection and PAEn/PRn quadrant
selection cannot be made on the same RCLK cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their PAE/PR
status output on PAE[0:7] constantly.
When the multi-queue devices are connected in expansion of more than one
device the PAEn/PRn busses of all devices are connected together, when
switching between quadrants of different devices the user must utilize the 3 most
significant bits of the RDADD address bus (as well as the 2 LSB’s). These 3
MSB’s correspond to the device ID inputs, which are the static inputs, ID0, ID1
& ID2.
Please refer to Figure 28, PAEn/PRn - Direct Mode Quadrant Selection for
timing information. Also refer to Table 2, Read Address Bus, RDADD.
PAEn – POLLED BUS
If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled
(looped) mode. In polled mode the PAEn/PRn bus automatically cycles through
the 4 quadrants within the device regardless of how many queues have been
setup in the part. Every rising edge of the RCLK causes the next quadrant to
be loaded on the PAEn/PRn bus. The device configured as the master (MAST
input tied HIGH), will take control of the PAEn/PRn after MRS goes LOW. For
the whole RCLK cycle that the first quadrant is on PAEn/PRn the ESYNC (PAEn/
PRn bus sync) output will be HIGH, for all other quadrants, this ESYNC output
will be LOW. This ESYNC output provides the user with a mark with which they
30
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via IOSEL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of REN and RADEN.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the Queue device, therefore the
ERCLK output level transitions should always be at the same position in time
relative to the data outputs. Note, that ERCLK is guaranteed by design to be
slower than the slowest Qn, data output. Refer to Figure 3, Echo Read Clock
and Data Output Relationship and Figure 27, Echo RCLK & Echo REN
Operation for timing information.
ECHO READ ENABLE (EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via IOSEL.
The EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data from the Qn output port at high speeds. The EREN output is controlled by
internal logic that behaves as follows: The EREN output is active LOW for the
RCLK cycle that a new word is read out of the Queue. That is, a rising edge
of RCLK will cause EREN to go active (LOW) if REN is active and the Queue
is NOT empty.
RCLK
tERCLK
tERCLK
ERCLK
tA
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tD
QSLOWEST(3)
5998 drw08
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 3. Echo Read Clock and Data Output Relationship
31
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON OUTPUT PORT:
BM
IW
OW
L
L
L
D35-D27
D26-D18
A
B
Q35-Q27
A
D17-D9
C
Q26-Q18
B
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D8-D0
D
Q17-Q9
Q8-Q0
C
D
Write to Queue
Read from Queue
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
BM
IW
OW
H
L
L
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q8-Q0
C
D
Q17-Q9
Q8-Q0
A
B
1st: Read from Queue
2nd: Read from Queue
(b) x36 INPUT to x18 OUTPUT
Q35-Q27
BM
IW
OW
H
L
H
Q26-Q18
Q17-Q9
Q8-Q0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
C
Q35-Q27
Q26-Q18
Q17-Q9
Q26-Q18
Q17-Q9
2nd: Read from Queue
Q8-Q0
B
Q35-Q27
1st: Read from Queue
3rd: Read from Queue
Q8-Q0
A
4th: Read from Queue
(c) x36 INPUT to x9 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
BYTE ORDER ON OUTPUT PORT:
BM
IW
OW
H
H
L
D26-D18
D26-D18
D17-D9
D8-D0
A
B
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
C
D
A
B
1st: Write to Queue
2nd: Write to Queue
Read from Queue
(d) x18 INPUT to x36 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D26-D18
D17-D9
D8-D0
A
D35-D27
D26-D18
D17-D9
D8-D0
B
D35-D27
D26-D18
D17-D9
D26-D18
D17-D9
BM
IW
OW
H
H
H
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D
C
B
A
(e) x9 INPUT to x36 OUTPUT
Figure 4. Bus-Matching Byte Arrangement
32
3rd: Write to Queue
D8-D0
D
BYTE ORDER ON OUTPUT PORT:
2nd: Write to Queue
D8-D0
C
D35-D27
1st: Write to Queue
4th: Write to Queue
Read from Queue
5998 drw09
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
tRSS
WEN
REN
tRSS
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
tRSS
ID0, ID1,
ID2
tRSS
OW, IW,
BM
tRSS
FM
HIGH = Looped
LOW = Strobed (Direct)
tRSS
HIGH = Master Device
MAST
LOW = Slave Device
tRSS
HIGH = Packet Ready Mode
PKT
LOW = Almost Empty
tRSS
DFM
HIGH = Default Programming
LOW = Serial Programming
tRSS
HIGH = Offset Value is 128
DF
LOW = Offset value is 8
tRSF
HIGH-Z if Slave Device
FF
LOGIC "0" if Master Device
tRSF
OV
LOGIC "1" if Master Device
HIGH-Z if Slave Device
tRSF
LOGIC "1" if Master Device
PAF
HIGH-Z if Slave Device
tRSF
HIGH-Z if Slave Device
PAE
LOGIC "0" if Master Device
tRSF
LOGIC "1" if Master Device
PAFn
HIGH-Z if Slave Device
tRSF
HIGH-Z if Slave Device
PAEn
tRSF
LOGIC "0" if Master Device
LOGIC "1" if Master Device
PR
HIGH-Z if Slave Device
tRSF
PRn
LOGIC "1" if Master Device
HIGH-Z if Slave Device
tRSF
LOGIC "1" if OE is LOW and device is Master
Qn
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
HIGH-Z if OE is HIGH or Device is Slave
5998 drw10
Figure 5. Master Reset
33
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
w-3
w-2
w-1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
tENS
tENS
WEN
tAS
tAH
WRADD
Qx
tWFF
FF
tWAF
PAF
tPAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQH
tQS
RADEN
tAS
RDADD
tAH
Qx
tROV
OV
tRAE
PAE
tPAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
r+4
5998 drw11
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 6. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
DFM
Serial Input
SENI
SENO
SI
SO
SCLK
SENI
MQn
SENO
SI
MRS
DFM
MQ2
MQ1
Serial Enable
MRS
DFM
SO
SENI
SENO
SO
SI
SCLK
Serial Loading
Complete
SCLK
Serial Clock
5998 drw12
Figure 7. Serial Port Connection for Serial Programming
34
35
tSCKH
tSCLK
tSCKL
tSDS
tSENS
B11
1st
B12
HIGH - Z
HIGH - Z
tSDH
2nd
1st Device in Chain
B1n
nth
tSENO
tSDO
B21
B21
1st
B22
B22
2nd
2nd Device in Chain
B2n
nth
B2n
tSENO
B81
1st
B81
tSDOP
B82
2nd
B82
Final Device in Chain
B8n
nth
B8n
Figure 8. Serial Programming
NOTES:
1. SENI can be toggled during serial loading. Once serial programming of a device is complete, the SENI and SI inputs become transparent. SENI → SENO and SI → SO.
2. DFM is LOW during Master Reset to provide Serial programming mode, DF is don't care.
3. When SENO of the final device is LOW no further serial loads will be accepted.
4. n = 19+(Qx72); where Q is the number of queues required for the IDT72T51546/72T51556.
5. This diagram illustrates 8 devices in expansion.
6. Programming of all devices must be complete (SENO of the final device is LOW), before any write or read port operations can take place, this includes queue selections.
OV
(Slave Device)
RADEN/
ESTR
RCLK
WEN
FF
(Slave Device)
WADEN/
FSTR
WCLK
SENO
(MQ8)
SENO
(MQ2)
SENO
(MQ1)
SO
(MQ1)
SI
(MQ1)
SENI
(MQ1)
SCLK
MRS
tRSR
tPCWQ
tQS
tQH
tQH
tENS
tWFF
Programming Complete
tPCRQ
tQS
tSENO
tSENOP
5998 drw13
tROV
tSENOP
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
36
1st
HIGH - Z
HIGH - Z
3rd
1st Device in Chain
2nd
nth
tSENO
NOTES:
1. This diagram illustrates multiple devices connected in expansion.
The SENO of the final device in a chain is the "programming complete" signal.
2. SENI of the first device in the chain can be held LOW
3. The SENO of a device should connect to the SENI of the next device in the chain.
The final device SENO is used to indicate programming complete.
4. When Default Programming is complete the SENO of the final device will go LOW.
5. SCLK is not used and can be tied LOW.
6. Programming of all devices must be complete (SENO of the final device is LOW),
before any write or read port operations can take place, this includes queue selections.
OV
(Slave Device)
RADEN/
ESTR
RCLK
WEN
FF
(Slave Device)
WADEN/
FSTR
SENO
(MQ8)
SENO
(MQ2)
SENO
(MQ1)
WCLK
MRS
WCLK
Serial Enable
(can be tied
LOW)
Default Mode
DFM = 1
Master Reset
SI
SENI
DFM
MQ1
X
1st
SI
SENI
DFM
WCLK
MQ2
2nd
SO
SENO
MRS
Final Device in Chain
X
nth
tQS
SI
SENI
DFM
tPCRQ
tQS
tPCWQ
tSENO
WCLK
MQn
tQH
SO
SENO
MRS
tQH
Programming
Complete
Serial Port Connection for Default Programming
SO
SENO
MRS
tSENO
WCLK
nth
Figure 9. Default Programming
1st
2nd
2nd Device in Chain
X
tROV
5998 drw14
Serial Loading
Complete
tENS
tWFF
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
37
tQS
tAS
Qx
*A*
tQH
tENS
tAS
tQS
*C*
Qy
tDS
tAH
tQH
tWFF
*AA*
Previous Q, Word, W
Previous Q Status
tAH
*B*
QX WD
*D*
tWFF
tDH
tQS
tAS
*BB*
1
Qy
*E*
tQH
tAH
No Writes
Queue Full
*F*
*CC*
2
tA
No Writes
Queue Full
*G*
PFT
*DD*
3
Qy WD-2
Previous Q, W+1
tWFF
tDS
*H*
tA
tDH tDS
tDH
Qy WD
*J*
*EE*
Qy, W0
tDS
tSKEW1
Qy WD-1
*I*
tENS
tWFF
tDH
tENH
*K*
Figure 10. Write Queue Select, Write Operation and Full Flag Operation
NOTE:
OE is active LOW.
Cycle:
*A* Queue, Qx is selected on the write port.
The FF flag is providing status of a previously selected queue, within the same device.
*AA* Queue, Qy is selected for read operations.
*B* The FF flag provides status of previous queue for 3 WCLK cycles.
*BB* Current word is kept on the output bus since REN is HIGH.
*C* The FF flag output updates to show the status of Qx, it is not full.
*CC* Word W+1 is read from the previous queue regardless of REN due to FWFT.
*D* Word, Wd is written into Qx. This causes Qx to go full.
*DD* The next available Word W0 of Qy is read out regardless of REN, 3 RCLK cycles after queue selection. This is FWFT operation.
*E* Queue, Qy is selected within the same device as Qx. A write to Qx cannot occur on this cycle because it is full, FF is LOW.
*EE* No reads occur, REN is HIGH.
*F* Again, a write to Qx cannot occur on this cycle because it is full, FF is LOW.
*FF* Word, W1 is read from Qy, this causes Qy to go “not full”, FF flag goes HIGH after time, tSKEW1 + tWFF. Note, if tSKEW1 is violated the time FF HIGH will be: tSKEW1 + WCLK + tWFF.
*G* The FF flag updates after time tWFF to show that queue, Qy is not full.
*GG* Word, W2 is read from Qy.
*H* Word, Wd-2 is written into Qy.
*I*
Word, Wd-1 is written into Qy.
*J* Word, Wd is written into Qy, this causes Qy to go full, FF goes LOW.
*K* A write to Qy cannot occur on this cycle because it is full, FF is LOW.
*L* Qy goes “not full” based on reading word W1 from Qy on cycle *FF*.
Qout
RDADD
RADEN
REN
RCLK
FF
Din
WADEN
WRADD
WEN
WCLK
*FF*
tA
*L*
Qy, W1
*GG*
tWFF
tA
5998 drw15
Qy, W2
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tENH
tENS
WEN
tDS
Dn
tDH
tDS
tDH
tDS
tDH
W3
W2
W1
tSKEW1
RCLK
1
2
tENS
REN
tA
Qout
tA
Last Word Read Out of Queue
W1 Qy
FWFT
tA
W2 Qy
FWFT
tROV
W3 Qy
tROV
OV
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 11. Write Operations & First Word Fall Through
38
5998 drw16
tQS
tAS
39
D1 Q27
Addr=001
11011
tQH
tAH
*B*
tQS
tAS
*C*
D1 Q5
tQS
tAS
2
tWFF
tDS
*H*
tA
tSKEW1
WD
tENS
*G*
D1 Q5
Addr=001
00101
tQH
tAH
*F*
No Write
WD
1
D1 Q5
*E*
D1 Q27
tWFF
tDH
tENH
Previous Q WX-1
tQ
H
tAH
HIGH-Z
tFFHZ
tFFLZ
tDS
tENS
*D*
tWFF
PFT
Previous Q WX
tDH
tENH
*I*
3
tA
tWFF
tQS
tAS
D2 Q9
*J*
tQH
tAH
D1-Q5
tFFLZ
tFFHZ
Word W0
PFT
*K*
5998 drw17
HIGH-Z
Figure 12. Full Flag Timing in Expansion Mode
NOTE:
*AA*
*BB*
*CC*
*DD*
1. REN = HIGH.
Cycle:
*A* Queue, Q27 of device 1 is selected on the write port.
The FF flag of device 1 is in High-Impedance, the write port of device 2 was previously selected.
WEN is HIGH so no write occurs.
*AA* Queue, Q5 of device 1 is selected on the read port.
*B* The FF flag stays in High-Impedance for 2 WCLK cycles.
*BB* Word, Wx-1 is held on the outputs for 2 RCLK cycles after a read Queue switch.
*C* The FF flag of device 2 goes to High-Impedance and the FF flag of device 1 goes to Low-Impedance, logic HIGH indicating that D1 Q27 is not full.
WEN is HIGH so no write occurs.
*CC* Word, Wx is read from the previously selected queue, (due to FWFT).
*D* Word, Wd is written into Q27 of D1. This write operation causes Q27 to go full, FF goes LOW.
*DD* The first word from Q5 of D1 selected on cycle *AA* is read out, this occurred regardless of REN due to FWFT. This read caused Q5 to go not full, therefore the FF flag will go HIGH after: tSKEW1 + tWFF.
Note if tSKEW1 is violated the time to FF flag HIGH is tSKEW1 + WLCK + tWFF.
*E* Queue, Q5 of device 1 is selected on the write port. No write occurs on this cycle.
*F* The FF flag stays in High-Impedance for 2 WCLK cycles.
*G* The FF flag updates to show the status of D1 Q5, it is not full, FF goes HIGH.
*H* Word, Wd is written into Q5 of D1. This causes the queue to go full, FF goes LOW.
*I*
No write occurs regardless of WEN, the FF flag is LOW preventing writes. The FF flag goes HIGH due to the read from Q5 of D1 on cycle *CC*. (This read is not an enabled read, it is due to the FWFT operation).
*J* Queue, Q9 of device 2 is selected on the write port.
*K* The FF flag of device 1 goes to High-Impedance, this device was deselected on the write port on cycle *I*. The FF flag of device 2 goes to Low-Impedance and provides status of Q9 of D2.
Qout
RADEN
RDADD
RCLK
FF
(Device 2)
HIGH-Z
FF
(Device 1)
Din
WADEN
WRADD
WEN
WCLK
*A*
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
QP Wn-3
tENS
tA
*B*
QP Wn-2
Previous Q
*A*
tA
tENH
*C*
QF
tQH
tAH
tENS
Previous Q, QP Wn-1
tQS
tAS
*D*
*E*
1
tA
PFT
QP Wn
*F*
2
tA
QG
3
PFT
QP Wn+1
tQS
tAS
*G*
tA
tQH
tAH
QF W0
*H*
tA
QF W1
*I*
tA
40
Figure 13. Read Queue Select, Read Operation
Cycle:
*A* Word Wn-3 is read from a previously selected queue Qp on the read port.
*B* Wn-2 is read.
*C* Reads are disabled, Wn-1 remains on the output bus.
*D* A new queue, QF is selected for read operations.
*E* Word Wn-1 in Qp is read out.
*F* The next word available in current queue QP, Wn+1 is read regardless of REN due to FWFT.
*G* The next word available in the new queue, QF-W0 falls through to the output bus, again this is regardless of REN. A new queue, QG is selected for read operations. (This queue is an empty queue).
*H* Word, W1 is read from QF.
*I* Word, W2 is read from QF.
*J* Word W2 from QF remains on the output bus because QG is empty. The Output Valid Flag, OV goes HIGH to indicate that the current word is not valid, i.e. QG is empty.
W2 is the last word in QG.
OV
QOUT
RADEN
RDADD
REN
RCLK
QF W2
*J*
tROV
5998 drw18
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
*E*
*F*
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*G*
*H*
*I*
*J*
RCLK
tENS
REN
tAH
tAS
RDADD
tAS
tQS
tAH
D1 Q15
D1 Q30
tQH
tQS
tQH
RADEN
tA
Qout
(Device 1)
tA
tA
tA
tOLZ
D1 Q30 WD Last Word
D1 Q15
D1 Q15 We Last Word
PFT We-1
tROV
tOVLZ
HIGH-Z
OV
(Device 1)
tROV
tROV
W0 Q15
D1
tROV
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
tENH
tENS
WEN
tAS
WRADD
tAH
D1 Q15
tQS
tQ
H
WADEN
tDS
Din
tDH
D1 Q15
W0
5998 drw19
Cycle:
*A* Queue 30 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* After a queue switch, there is a 3 RCLK latency for output data.
*D* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q30 of D1. This happens to be the last word of Q30. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q30 is valid.
*E* Queue 15 of device 1 is selected for read operations. The last word of Q30 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q30 was read to empty). Word, Wd remains on the output bus.
*F* The last word of Q30 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*G* The next word (We-1), available from the newly selected queue, Q15 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag updates 3 RCLK cycles after a queue selection.
*H* The last word, We is read from Q15, this queue is now empty.
*I* The OV flag goes HIGH to indicate that Q15 was read to empty on the previous cycle.
*J* Due to a write operation the OV flag goes LOW and data word W0 is read from Q15. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 14. Output Valid Flag Timing (In Expansion Mode)
41
QP WD
tENS
*A*
tA
tENH
*B*
Qn
QP WD+1
tQS
tAS
*C*
tQH
tAH
tENS
*D*
1
tA
tENH
QP WD+2
*E*
2
tA
QP WD+3
*F*
3
tA
tQS
tAS
QP
*G*
42
tQ
H
tAH
*H*
Qn WX
Figure 15. Read Queue Selection with Reads Disabled
Cycle:
*A* Word Wd+1 is read from the previously selected queue, Qp.
*B* Reads are disabled, word Wd+1 remains on the output bus.
*C* A new queue, Qn is selected for read port operations.
*D* Word, WD+2 of Qp is read out.
*E* Word WD+3 of Qp is read out regardless of REN due to FWFT operation.
*F* The next available word Wx of Qn is read out regardless of REN, 3 RCLK cycles after queue selection. This is FWFT operation.
*G* The queue, Qp is again selected.
*H* Current Word is kept on the output bus since REN is HIGH.
*I* Word Wx+2 is read from Qn. This is read out regardless of REN due to FWFT operation.
*J* Word WD+3 is read from Qp.
*K* Word WD+4 is read from Qp.
*L* Reads are disabled on this cycle, therefore no further reads occur.
OV
QOUT
RADEN
RDADD
REN
RCLK
1
tENS
*I*
2
tA
Qn WX+1
*J*
3
tA
Qn WX+2
*K*
tA
5998 drw20
QP WD+3
tENH
*L*
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tOLZ
tQS
tAS
tOE
QA
*A*
tQH
tAH
*C*
2
tENS
Previous Data in O/P Register
1
*B*
*D*
3
tROV
tA
tENH
*E*
PFT
QA W0
tENS
*F*
tA
QA W1
*G*
tA
QB
QA W2
tQS
tAS
*H*
tA
tQH
tAH
QA W3
*I*
1
tA
QA W4
2
*J*
tA
tROV
tOHZ
3
43
Figure 16. Read Queue Select, Read Operation and OE Timing
5998 drw21
No Read
QB is Empty
*K*
NOTES:
1. The Output Valid flag, OV is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus will go to Low-Impedance after time tOLZ.
The data currently on the output register will be available on the output after time tOE. This data is the previous data on the output register, this is the last word read out of the previous queue.
2. In expansion mode the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled.
Cycle:
*A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty.
*B* No data will fall through on this cycle, the previous queue was read to empty.
*C* Previous data kept on output bus since there is no read operation.
*D* Word, W0 from QA is read out regardless of REN due to FWFT operation. The OV flag goes LOW indicating that Word W0 is valid.
*E* Reads are disabled therefore word, W0 of QA remains on the output bus.
*F* Reads are again enabled so word W1 is read from QA.
*G* Word W2 is read from QA.
*H* Queue, QB is selected on the read port. This queue is actually empty. Word, W3 is read from QA.
*I* Word, W4 is read from QA.
*J* Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, tOHZ.
*K* Output Valid flag, OV goes HIGH to indicate that QB is empty. Data on the output port is no longer valid.
OV
Qout
OE
RADEN
RDADD
REN
RCLK
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
QA
Data
QA
tDS
tAS
tDH
tAH
QA
Data
QB
B
1
QA
TEOP
C
NOTE:
1. Do not Write an SOP or EOP on "D" or "K". A filler word is needed.
(D35)
TSOP
(D35)
TEOP
WEN
Din
WADEN
WRADD
WCLK
A
QB
TSOP
E
QB
Data
F
QB
Data
G
H
QB
TEOP
Figure 17. Writing in Packet Mode during a Queue change
QA
Dummy
2
D(1)
tAS
1
QC
I
tAH
J
2
QB
Dummy
tDS
K(1)
tDH
5998 drw22
QC
TSOP
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
QA
tAS
tA
tAH
QA
Data
QB
B
1
QA
Data
C
tA
D
2
QA
REOP
NOTE:
1. Do not Read an SOP or EOP on "E" or "L". A filler word is needed.
(Q34)
RSOP
(Q35)
REOP
REN
Qout
RADEN
RDADD
RCLK
A
tA
QA
“Dummy”
QB
RSOP
F
tA
QB
Data
G
tA
QB
Data
H
Figure 18. Reading in Packet Mode during a Queue change
tA
E(1)
QC
QB
REOP
tAS
I
tAH
J
1
K
2
tA
QB
“Dummy”
L(1)
tA
5998 drw23
QC
RSOP
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
46
tDS
tDS
tDS
tDS
tENS
P1Wo
tDH
tDH
tDH
tDH
tDS
tDH
P1Wn-3
*B*
P1Wn-1
Last Word Read Out
P1Wn-2
tDS
tDS
tDS
tDH
tDH
tDH
tENH
P1Wn
*C*
tSKEW4
tSKEW5
Figure 19. Data Input (Transmit) Packet Mode of Operation
NOTES:
1. REN is HIGH.
2. If tSKEW4 is violated PR may take one additional RCLK cycle.
3. If tSKEW5 is violated the OV may take one additional RCLK cycle.
4. PR will always go LOW on the same cycle or 1 cycle ahead of OV going LOW, (assuming the last word of the packet is the last word in the queue).
5. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN.
Qn
OV
PR
RCLK
TMOD2
(D32)
TAEOP/ TMOD1
(D33)
TEOP
(D35)
TSOP
(D34)
D0D31
WEN
WCLK
*A*
tPR
tA
tROV
5998 drw24
P1Wo
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
47
tENS
tA
P1Wo
*B*
tA
P1W1
*C*
tA
tPR
P1W2
*D*
tA
P1Wn-3
tA
P1Wn-2
tA
P1Wn-1
*E*
tA
tRO
V
5998 drw35
P1Wn
tA
Figure 20. Data Output (Receive) Packet Mode of Operation
NOTE:
1. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN.
2. The PR flag will go HIGH on cycle *C* regardless of REN.
3. The OV flag will go HIGH (preventing further reads), when the last complete packet has been read out. If there is a partial packet (an incomplete packet) in the queue the OV flag will remain HIGH until further writes have
completed the packet.
OV
RMOD2
(Q32)
RAEOP/ RMOD1
(Q33)
Q0-Q31
REOP
(Q35)
RSOP
(Q34)
PR
REN
RCLK
*A*
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
NULL QUEUE
SELECT
*A*
*B*
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SELECT
NEW QUEUE
*D*
*C*
*E*
*G*
*F*
RCLK
tAS
tAH
tAS
tQS
tQH
tQS
tAS
tAH
00100000
RDADD
tAH
00000100
tQH
RADEN
Null-Q
tENS
tENH
REN
Qout
Q1 Wn-4
tA
tA
tA
Q1 Wn-3
Q1 Wn-2
tA
tA
Q1 Wn-1
Q4 W0
Q1 Wn
tROV
FWFT
tROV
OV
5998 drw26
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 22, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-3 from previously selected Q1 is read.
*C* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 3 RCLK cycles between queue selects.
*D* The Null Q is seen as an empty Queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH. A new queue, Q4 is selected.
*G* 1st word, W0 of Q4 falls through present on the O/P register after 3 RCLK cycles after the queue select.
Figure 21. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
*G*
Queue 1
Memory
Queue 1
Memory
Null
Queue
Null
Queue
Null
Queue
Queue 4
Memory
Queue 4
Memory
Q1
Wn
Q1
Wn
O/P Reg.
Qn
Wn-2
Q1
Wn
O/P Reg.
Q1
Wn-1
Q1
Wn
O/P Reg.
Q1
Wn
Q1
Wn
O/P Reg.
Q1
Wn
Q4
W0
O/P Reg.
Q1
Wn
Q4
W1
O/P Reg.
Q1
Wn
O/P Reg.
Q4
W0
5998 drw27
Figure 22. Null Queue Flow Diagram
48
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*B*
*A*
*D*
*C*
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*G*
*F*
*E*
WCLK
*H*
2
1
tENH
tENS
WEN
tAH
tAS
WRADD
tAS
D1 Q5
tQS
tAH
D1 Q9
tQH
tQH
tQS
WADEN
tDS
Din
tDH
WD-m
D1 Q5
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
5998 drw28
Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* No write occurs.
*D* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.
*E* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.
*F* The PAF flag goes LOW based on the write 2 cycles earlier.
*G* No write occurs.
*H* The PAF flag goes HIGH due to the queue switch to Q9.
Figure 23. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
1
2
1
tENS
tENH
WEN
tWAF
PAF
tWAF
(2)
D - m words in Queue
D - (m+1) words in Queue
tSKEW2
D-(m+1) words
in Queue
RCLK
tENS
REN
tENH
5998 drw29
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 24. Almost Full Flag Timing
49
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*B*
*A*
*C*
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*E*
*D*
*F*
*G*
*H*
RCLK
REN
HIGH
tAH
tAS
RDADD
tAS
tAH
D1 Q30
tQS
D1 Q15
tQH
tQH
tQS
RADEN
tOLZ
Qout
tA
tA
HIGH-Z
D1 Q30 Wn
tA
D1 Q15 W0
D1 Q15 W1
tRAE
tRAE
tAELZ
PAE
(Device 1)
tA
D1 Q30 Wn+1
HIGH-Z
tAEHZ
PAE
(Device 2)
HIGH-Z
5998 drw30
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* No read occurs.
*D* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*E* Q15 of device 1 is selected.
*F* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*G* Word, W0 is read from Q15 due to the FWFT operation.
*H* The PAE flag goes HIGH to show that Q15 is not almost empty.
Figure 25. Almost Empty Flag Timing and Queue Switch
tCLKL
tCLKH
WCLK
tENS
tENH
WEN
PAE
n+1 words in Queue
tSKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
tRAE
RCLK
1
tENS
REN
2
tENH
5998 drw31
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 26. Almost Empty Flag Timing
50
Cycle:
*A*
*B*
*C, D*
*E*
*F, G*
*H*
*I*
QP Wn-3
tENS
tA
tCLKEN
*B*
QP Wn-2
tERCLK
Previous Q
*A*
tA
tENH
tCLKEN
*C*
QF
H
tQ
tAH
tENS
Previous Q, QP Wn-1
tQS
tAS
*D*
51
1
tA
tCLKEN
*E*
1
QG
PFT
tQS
tAS
QP Wn+1
tA
2
*G*
PFT
2
QP Wn
*F*
Figure 27. Echo RCLK and ECHO REN Operation
EREN follow REN provided that the current queue (Qp) is not empty.
EREN stays active since a new word (Wn-1) from Qp is placed on the output bus.
EREN goes HIGH since no new word has been placed on the output bus on this cycle.
REN goes LOW, new word placed on output bus, so EREN goes LOW.
EREN stays active since a new word from Qp has been placed on the output bus.
W0 is the last word in QF thus OV goes HIGH.
EREN goes HIGH since no new word has been placed on the output bus and QF is empty.
OV
QOUT
RADEN
RDADD
EREN
REN
ERCLK
RCLK
tA
tQH
tAH
*H*
QF W0
tROV
*I*
5998 drw32
tCLKEN
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tQH
tQS
tQS
tQH
Device 1
Quadrant 3
Device 1
Quadrant 2
RDADD
001xxx11
001xxx10
tSTS
tQS
tQH
Device 1
Quadrant 0
001xxx00
tSTS
tSTH
tSTH
ESTR
tPAE
tPAE
PAEn/
PRn
Device 1 Quadrant 2
tPAE
Device 1 Quadrant 3
Device 1 Quadrant 0
5998 drw33
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.
3. There is a latency of 2 RCLK for the PAEn bus to switch.
Figure 28. PAEn/PRn - Direct Mode - Quadrant Selection
WCLK
tQH
tQS
tQS
tQH
Device 1
Quadrant 3
Device 1
Quadrant 1
WRADD
001xxx01
tSTS
001xxx11
tSTS
tSTH
tQS
tQH
Device 1
Quadrant 2
001xxx10
tSTH
FSTR
tPAF
tPAF
PAFn
Device 1 Quadrant 1
tPAF
Device 1 Quadrant 3
Device 1 Quadrant 2
5998 drw34
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.
3. There is a latency of 2 WCLK for the PAFn bus to switch.
Figure 29. PAFn - Direct Mode - Quadrant Selection
52
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A*
WCLK
tQS
*B*
1
*C*
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*D*
3
*E*
tQH
tQS
*F*
*G*
*H*
tQS
tQH
tQH
WADEN
tSTS
tSTH
FSTR
tENS
tENS
tENH
tENH
WEN
tAH
tAS
WRADD
D5Q24
100 11000
tAS
tDH tDS
tDS
Wp+1
Wp
Writes to Previous Q
Dn
tDH tDS
Wp+2
tDH
tAH
tAS
tAH
D3Q8
011 01000
D4 quad 3
100 xxx10
Wn+1
D5Q24
Wn
D5 Q24
Wx
D3 Q8
tSKEW3
RCLK
tQS
tQH
1
2
3
3
2
1
RADEN
tSTS
tSTH
ESTR
tENS
tENH
REN
tAH
tAS
RDADD
Device 5 -Qn
Prev PAEn
tAS
D5Q24
100 11000
tAH
D5 quad 4
tA
Wa
D5 Q17
101 xxx11
tA
Wa+1
D5 Q17
tA
Wy
D5 Q24
tA
Wy+1
D5 Q24
tA
Wy+2
D5 Q24
Previous value loaded on to PAE bus
tPAEZL
tPAEHZ
Device 5 PAEn
Bus PAEn
Previous value loaded on to PAE bus
tRAE
Device 5 PAE
Wy+3
D5 Q24
xxxx xxx1
D5Quad 4
xxxx xxx0
D5Quad4
xxxx xxx1
D5Quad 4
xxxx xxx0
D5Quad4
tRAE
tRAE
D5 Q24
status
D5 Q17 Status
*AA*
tPAE
*BB*
*CC*
*DD*
*EE*
5998 drw35
*FF*
*GG*
Cycle:
*A* Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 24 of Device 5 is selected for read operations.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Current Word is kept on the output bus since REN is HIGH.
*C* Word Wp+2 is written into the previously selected queue.
*CC* Word Wa+1 of D5 Q17 is read due to FWFT.
*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).
*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
Quadrant 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
*E* Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
*EE* Word, Wy+1 is read from Q24 of D5.
*F* No writes occur.
*FF* Word, Wy+2 is read from Q24 of D5.
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected
quadrant now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
*G* Quadrant 3 of device 4 is selected on the write port for the PAFn bus.
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
*H* Word, Wx is written into Q8 of D3.
Figure 30. PAEn - Direct Mode, Flag Operation
53
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
*E*
*F*
*G*
RCLK
tQS
*I*
tQH
tQS
tQH
*H*
RADEN
tSTH
tSTS
ESTR
REN
tAS
RDADD
tAH
tAH
tAS
D0Q31
000 11111
tAH
tAS
D6Q2
110 00010
D7 quad 1
111 xxx00
OE
tA
tA
tOLZ
Qout
WX
Prev. Q
WX +1
Prev. Q
tSKEW3
WCLK
tA
WD - M + 2
D0 Q31
WD-M+1
D0 Q31
1
tSTS
tA
2
W0
D6 Q2
3
tSTH
FSTR
tAH
tAS
WRADD
tAS
D0 quad4
tAH
D0 Q31
tENS
000 xxx11
tENH
WEN
tQH
tQS
WADEN
tDS
tDH
tDS
tDH
Wy+1
Word Wy
D0 Q31
D0 Q31
tPAF
Din
tPAFLZ
Device 0 PAFn
D0Quad4
tDS
tDH
Wy+2
D0 Q31
tPAF
0xxx xxxx
D0Quad4
1xxx xxxx
D0Quad4
0xxx xxxx
0xxx xxxx
D0Quad4
1xxx xxxx
D0Quad4
0xxx xxxx
HIGH-Z
Bus PAFn
DXQuad y
Prev.
PAFn
DXQuad y
Device 0
PAF
D0Quad4
tPAFHZ
HIGH-Z
tPAFLZ
tWAF
HIGH - Z
*AA*
*BB*
5998 drw36
*CC*
*DD*
*EE*
*FF*
*GG*
Cycle:
*A* Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B* No read operation.
*BB* Queue 31 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* PAFn continues to show status of Quad4 D0.
The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q31.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H* No read operation.
*I*
Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.
Figure 31. PAFn - Direct Mode, Flag Operation
54
tFSYNC
D0Quad1
tPAF
D0Quad2
tPAF
tFSYNC
NOTE:
1. This diagram is based on 3 devices connected in expansion mode.
PAFn
FXI0
FXO2 /
(SLAVE)
FSYNC2
FXI2
FXO1 /
(SLAVE)
FSYNC1
FXI1
FXO0 /
(MASTER)
FSYNC0
WCLK
D0Quad3
tPAF
tFXO
D1Quad1
tPAF
D1Quad2
tPAF
tFSYNC
D1Quad3
tPAF
tFXO
Figure 32. PAFn Bus - Polled Mode
D0Quad4
tPAF
tFSYNC
tFXO
D1Quad4
tPAF
tFSYNC
D2Quad1
tPAF
tFXO
D2Quad2
tPAF
tFSYNC
D2Quad3
tPAF
tFXO
D2Quad4
tPAF
tFSYNC
D0Quad1
tPAF
tFXO
5998 drw37
D0Quad2
tPAF
tFSYNC
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
55
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tESYNC
D0Quad1
tPAE
D0Quad2
tPAE
tESYNC
D0Quad3
tPAE
tEXO
NOTE:
1. This diagram is based on 3 devices connected in expansion mode.
PAEn
EXI0
EXO2 /
ESYNC2
EXI2
EXO1 /
ESYNC1
EXI1
EXO0 /
ESYNC0
RCLK
D1Quad1
tPAE
D1Quad2
tPAE
tESYNC
D1Quad3
tPAE
tEXO
D1Quad4
tPAE
tESYNC
Figure 33. PAEn/PRn Bus - Polled Mode
D0Quad4
tPAE
tESYNC
tEXO
D2Quad1
tPAE
tEXO
D2Quad2
tPAE
tESYNC
D2Quad3
tPAE
tEXO
D2Quad4
tPAE
tESYNC
D0Quad1
tPAE
tEXO
5998 drw38
D0Quad2
tPAE
tESYNC
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
56
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WEN
tDH
tDS
D[39:0]
WD10
tDS
tDH
tDS
WD11
WD12
tDH
tDS
WD13
1ns
(1)
1
RCLK
2
3
4
REN
tA
Q[39:0]
WD1
tA
WD2
tPDHZ(7)
tA
WD3
tPDLZ(2)
Hi-Z
WD4
tA
WDH
WDS
tPDH(2)
tPDH(2)
tPDL
PD
tERCLK
Hi-Z
ERCLK
tEREN
tEREN
Hi-Z
EREN
5998 drw39
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
Figure 34. Power Down Operation
57
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Serial Programming Data Input
Serial Enable
SENI
Data Bus
Write Clock
Write Enable
Write Queue Select
SI
EXI
Output Data Bus
Q0-Q35
WEN
Almost Full Flag
Serial Clock
Read Queue Select
RDADD
WRADD
DEVICE
1
FSTR
Read Address
RADEN
Empty Strobe
ESTR
Programmable Almost Empty
PAEn
PAFn
Full Flag
Read Enable
REN
WADEN
Full Sync1
Read Clock
RCLK
WCLK
Write Address
Full Strobe
Programmable Almost Full
FXI
D0-D35
Empty Sync 1
ESYNC
FSYNC
Output Valid Flag
OV
FF
PAF
Almost Empty Flag
PAE
Packet
Reads
PR
SCLK
SENO SO FXO EXO
SENI
SI
FXI
EXI
Q0-Q35
D0-D35
WCLK
RCLK
REN
WEN
WRADD
RDADD
RADEN
WADEN
DEVICE
2
FSTR
Full Sync2
PAFn
FSYNC
ESTR
PAEn
ESYNC
FF
OV
PAF
PAE
Empty Sync 2
PR
SCLK
SENO SO FXO EXO
SENI
SI
FXI
EXI
Q0-Q35
D0-D35
WCLK
RCLK
REN
WEN
WRADD
WADEN
Full Sync n
DEVICE
n
FSTR
PAFn
FSYNC
RDADD
RADEN
ESTR
PAEn
ESYNC
FF
Empty Sync n
OV
PAF
PAE
PR
SCLK
SENO
FXO EXO
DONE
5998 drw40
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 35. Multi-Queue Expansion Diagram
58
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
•
•
TAP controller
•
Instruction Register (IR)
•
Data Register Port (DR)
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T51546/72T51556
incorporates the necessary tap controller and modified pad cells to implement
the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
TMS
TCLK
TRST
P
TAP
clkDR, ShiftDR
UpdateDR
Controller
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5998 drw41
Figure 36. Boundary Scan Architecture
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
59
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Test-Logic
Reset
0
0
Run-Test/
Idle
1
SelectDR-Scan
1
SelectIR-Scan
1
0
1
0
Capture-IR
1
Capture-DR
0
0 0
Shift-DR
Shift-IR
1
1
Input = TMS
EXit1-DR
1
0
0
Pause-IR
1
1
Exit2-DR
Exit2-IR
0
1
1
Update-IR
Update-DR
1
1
Exit1-IR
0 0
Pause-DR
0
0
1
0
0
5998 drw42
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 37. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram.
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue and must be reset after power up of the device. See TRST
description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling
the normal operation of the IC. The TAP controller state machine is designed
in such a way that, no matter what the initial state of the controller is, the TestLogic-Reset state can be entered by holding TMS at high and pulsing TCK five
times. This is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
60
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at UpdateIR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Hex
Value
00
01
02
04
0F
Instruction
Function
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
Select Boundary Scan Register
Select Boundary Scan Register
Select Chip Identification data register
JTAG
Select Bypass Register
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T51546/72T51556, the Part Number field contains the
following values:
Device
IDT72T51546
IDT72T51556
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register
containing information regarding the IC manufacturer, device type, and version
code. Accessing the device identification register does not interfere with the
operation of the IC. Also, access to the device identification register should be
immediately available, via a TAP data-scan operation, after power-up of the
IC or after the TAP has been reset using the optional TRST pin or by otherwise
moving to the Test-Logic-Reset state.
Part# Field (HEX)
0x48C
0x48D
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data
into the boundary-scan register before loading an EXTEST instruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
61
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
62
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5998 drw43
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
t5
Figure 38. Standard JTAG Timing
JTAG AC ELECTRICAL
CHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min.
SYSTEM INTERFACE PARAMETERS
IDT72T51546
IDT72T51556
Parameter
Symbol
Test Conditions
Data Output
tDO
-
20
ns
Data Output Hold
tDOH(1)
0
-
ns
Data Input
tDS
tDH
10
10
-
ns
(1)
trise=3ns
tfall=3ns
Min.
Max. Units
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-
40
-
ns
JTAG Clock Low
tTCKLOW
-
40
-
ns
JTAG Clock Rise Time
tTCKRISE
-
-
5(1)
ns
(1)
JTAG Clock Fall Time
tTCKFALL
-
-
5
ns
JTAG Reset
tRST
-
50
-
ns
JTAG Reset Recovery
tRSR
-
50
-
ns
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
63
Max. Units
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
Device Type
Power
Speed
Package
X
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BB
Plastic Ball Grid Array (PBGA, BB256-1)
5
6
Commercial Only
Commercial and Industrial
L
Low Power
72T51546
72T51556
1,179,648 bits  2.5V Multi-Queue Flow-Control Device
2,359,296 bits  2.5V Multi-Queue Flow-Control Device
Clock Cycle Time (tCLK)
Speed in Nanoseconds
5998 drw44
NOTE:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
DATASHEET DOCUMENT HISTORY
06/06/2003
11/06/2003
pgs. 1 through 64.
pgs. 1, 4, 17 and 18.
CORPORATE HEADQUARTERS
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64
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408-330-1533
email: [email protected]
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