ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com Isolated 3.3V RS-485 Transceiver With Integrated Transformer Driver Check for Samples: ISO35T FEATURES 1 • • • • • • • • • • 3000VRMS / 4242VPK Isolation Bus-Pin ESD Protection – 16 kV HBM Between Bus-Pins and GND2 – 6 kV HBM Between Bus-Pins and GND1 1/8 Unit Load – Up to 256 Nodes on a Bus Designed for RS-485 and RS-422 Applications Signaling Rates up to 1 Mbps Thermal Shutdown Protection Typical Efficiency > 60% (ILOAD = 100 mA) - see SLUU470 Low Driver Bus Capacitance 16 pF (Typ) 50 kV/µs Typical Transient Immunity UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2) Approvals Pending Fail-safe Receiver for Bus Open, Short, Idle Logic Inputs are 5-V Tolerant DW PACKAGE D1 D2 GND1 VCC1 R RE DE D 1 2 16 15 3 4 5 6 7 8 14 13 12 11 10 9 VCC2 GND2 A B Z Y NC GND2 FUNCTION DIAGRAM D1 D2 R 1 2 OSC 5 6 RE DE D 7 8 GALVANIC ISOLATIO N • • 14 A 13 12 B Z 11 Y APPLICATIONS • • • • • Isolated RS-485/RS-422 Interfaces Factory Automation Motor/Motion Control HVAC and Building Automation Networks Networked Security Stations DESCRIPTION The ISO35T is an isolated differential line transceiver with integrated oscillator outputs that provide the primary voltage for an isolation transformer. The device is a full-duplex differential line transceiver for RS-485 and RS-422 applications that can easily be configured for half-duplex operation by connecting pin 11 to pin 14, and pin 12 to pin 13. These devices are ideal for long transmission lines since the ground loop is broken to allow for a much larger common-mode voltage range. The symmetrical isolation barrier of the device is tested to provide 4242VPK of isolation per VDE for 60s between the bus-line transceiver and the logic-level interface. Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and duration. The ISO35T can significantly reduce the risk of data corruption and damage to expensive control circuits. The ISO35T is specified for use from –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com 4 X-FMR 8 3 2 7 6 1 5 LDO D1 1 C4 C5 3 2 C1 IN OUT 5 EN C6 GND NC 1 D2 1 2 C2 Control Circuitry VCC2 D1 16 C3 D2 4 V CC1 3 GND1 5 R 6 RE 7 DE 8 D A B Z Y Isolated Supply to other Components 14 13 12 RS-485 Bus Interface 11 15 GND2 9, 10 ISO35T Typical Application Circuit (For details see sluu470) PIN DESCRIPTIONS NAME PIN # FUNCTION D1 1 Transformer Driver Terminal 1, Open Drain Output D2 2 Transformer Driver Terminal 2, Open Drain Output GND1 3 Logic-side Ground VCC1 4 Logic-side Power Supply R 5 Receiver Output RE 6 Receiver Enable Input. This pin has complementary logic. DE 7 Driver Enable Input D 8 Driver Input GND2 9, 15 Bus-side Ground. Both pins are internally connected. NC 10 No Connect. This pin is not connected to any internal circuitry. Y 11 Non-inverting Driver Output Z 12 Inverting Driver Output B 13 Inverting Receiver Input A 14 Non-inverting Receiver Input VCC2 16 Bus-side Power Supply 2 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com vertical spacer ABSOLUTE MAXIMUM RATINGS (1) VCC1,VCC2 Input supply voltage (2) VA,VB,VY,VZ Voltage at any bus I/O terminal (A, B, Y, Z) VD1,VD2 Voltage at D1, D2 V(TRANS) Voltage input, transient pulse through 100Ω, see Figure 12 (A,B,Y,Z) VI Voltage input at any D, DE or RE terminal IO ID1,ID2 V –9 to 14 V 14 V –50 to +50 V V ±10 mA Transformer Driver Output Current 450 mA Bus pins and GND1 ±6 kV Bus pins and GND2 ±16 kV All pins ±4 kV ±1.5 kV Electrostatic discharge Charged Device Model Machine Model Maximum junction temperature TSTG Storage temperature (2) –0.3 to 6 Receiver output current TJ (1) UNIT –0.5 to 7 Human Body Model ESD VALUE JEDEC Standard 22, Test Method A114-C.01 JEDEC Standard 22, Test Method C101 All pins ANSI/ESDS5.2-1996 ±200 V 170 °C -65 to 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX VCC1,VCC2 Supply Voltage 3.0 3.3 3.6 V VI or VIC Voltage at any bus terminal (separately or common-mode) –7 12 V VIH High-level input voltage 2 VCC VIL Low-level input voltage 0 0.8 VID Differential input voltage A with respect to B –12 12 RL Differential load resistance Driver –60 60 –8 8 D, DE, RE 54 V V Ω 60 IO Output Current TA Ambient temperature -40 85 TJ Operating junction temperature –40 150 1 / tUI Signaling Rate Receiver UNIT 1 mA °C °C Mbps SUPPLY CURRENT & COMMON MODE TRANSIENT IMMUNITY over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC1 (1) Logic-side quiescent supply current DE & RE = 0V or VCC1 (Driver and Receiver Enabled or Disabled), D = 0 V or VCC1, No load 4.5 8 mA ICC2 (1) Bus-side quiescent supply current RE = 0 V or VCC1, DE = 0 V (driver disabled), No load 7.5 13 mA 9 16 Common-mode transient immunity See Figure 13 CMTI (1) RE = 0 V or VCC1, DE = VCC1 (driver enabled), D = 0 V or VCC1, No Load 25 50 kV/µs ICC1 and ICC2 are measured when device is connected to external power supplies, VCC1 & VCC2. In this case, D1 & D2 are open and disconnected from external transformer. Copyright © 2010–2011, Texas Instruments Incorporated 3 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com RS-485 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| TEST CONDITIONS Differential output voltage magnitude MIN IO = 0 mA (No Load) 2.5 RL = 54 Ω (RS-485), See Figure 1 1.5 2 2 2.3 RL = 100 Ω (RS-422) (1), See Figure 1 Vtest = –7 V to +12 V, See Figure 2 Δ|VOD| Change in magnitude of the differential output voltage VOC(SS) Steady-state common-mode output voltage See Figure 1 and Figure 2 ΔVOC(SS) Change in steady-state common-mode output voltage Figure 3 VOC(pp) Peak-to-peak common-mode output voltage See Figure 3 II Input current, D & DE VI at 0 V or VCC1 IOZ IOS(P) (2) IOS(SS) C(OD) (1) (2) –0.2 0 0.2 V 1 2.6 3 V 0.1 V 10 µA 0.25 90 µA –10 Other input at 0 V 300 -250 mA 250 VI = 0.4 sin (4E6πt) + 0.5V, DE at 0 V Differential output capacitance V Other input at 0 V VY or VZ = –7 V to +12 V, See Figure 4 Steady-state short-circuit output current V 1.5 –10 VY or VZ = –7 V, VCC = 0 V or 3 V, DE = 0 V Peak short-circuit output current (2) UNIT VCC2 –0.1 VY or VZ = 12V, VCC = 0 V or 3 V, DE = 0 V High-impedance state output current TYP MAX 16 mA pF VCC2 = 3.3 V ± 5% This device has thermal shutdown and output current-limiting features to protect in short-circuit fault condition. RS-485 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN See Figure 5 TYP MAX 205 340 tPLH, tPHL Propagation delay tsk(p) Pulse skew (|tPHL – tPLH|) tr Differential output signal rise time 120 185 300 tf Differential output signal fall time 120 180 300 tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level to high-impedance output tPZL Propagation delay, high-impedance-to-low-level output 1.5 See Figure 6 UNIT ns 205 530 See Figure 7 330 ns 530 RS-485 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT(+) Positive-going input threshold voltage IO = -8 mA VIT(–) Negative-going input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ – VIT–) VOH See Figure 8 Low-level output voltage IO(Z) High-impedance state output current 4 TYP MAX –20 –200 50 High-level output voltage VOL MIN VO = 0 or VCC1, RE = VCC1 VID = +200 mV, IO = -8 mA UNIT mV mV 2.4 V VID = –200 mV, IO = 8 mA 0.4 –1 1 µA Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com RS-485 RECEIVER ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VA or VB = 12 V IA, IB VA or VB = 12 V, VCC2 = 0 V Bus input current VA or VB = –7 V Other input at 0 V VA or VB = -7 V, VCC2 = 0 V TYP MAX 50 100 60 100 –100 –40 –100 –30 UNIT µA IIH High-level input current, RE VIH = 2. V –10 10 IIL Low-level input current, RE VIL = 0.8 V –10 10 RID Differential input resistance Measured between A & B CID Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5V, DE at 0 V 96 µA kΩ 2 pF RS-485 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay tsk(p) Pulse skew (|tPHL – tPLH|) tr Output signal rise time tf Output signal fall time tPHZ, tPZH Propagation delay, high-level to high-impedance output Propagation delay, high-impedance to high-level output See Figure 10, DE at 0 V tPLZ tPZL Propagation delay, low-level to high-impedance output Propagation delay, high-impedance to low-level output See Figure 11, DE at 0 V MIN TYP MAX 85 115 13 See Figure 9 UNIT ns 1 4 1 4 13 25 13 25 MIN TYP MAX UNIT 300 400 550 kHz 1 2.5 ns TRANSFORMER DRIVER CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS fOSC Oscillator frequency VCC1 = 3.3V ± 10%, D1 and D2 connected to Transformer RON Switch on resistance D1 and D2 connected to 50Ω pull-up resistors tr_D D1, D2 output rise time VCC1 = 3.3V ± 10%, see Figure 14, D1 and D2 connected to 50-Ω pull-up resistors. 70 ns tf_D D1, D2 output fall time VCC1 = 3.3V ± 10%, see Figure 14, D1 and D2 connected to 50-Ω pull-up resistors. 80 ns fSt Startup frequency VCC1 = 2.4 V, D1 and D2 connected to Transformer 350 kHz tBBM Break before make time delay VCC1 = 3.3V ± 10%, see Figure 14, D1 & D2 connected to 50-Ω pull-up resistors. 140 ns Copyright © 2010–2011, Texas Instruments Incorporated Ω 5 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC1 VCC2 IY DE 0 or VCC1 Y VOD D RL D 0 or 3 V Z GND1 375 W DE Y II . + VOD - Z 60 W IZ GND2 VI 375 W GND2 VY VZ GND1 VTEST = -7 V to 12 V GND2 Figure 1. Driver VOD Test and Current Definitions VCC1 IY DE 27 W ±1% Y II Input D VOD Z GND2 GND1 VI 27 W ±1% IZ VZ GND1 Figure 2. Driver VOD With Common-Mode Loading Test Circuit VY Y VY Z VZ VOC VOC(SS) VOC(p-p) VOC Input Generator: PRR= 100 kHz, 50 % duty cycle, t r < 6ns , t f <6 ns , ZO = 50 W GND2 Figure 3. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage Y IOS D Z IOS + V_ OS GND1 GND2 Output Current - mA DE 300 250 time Figure 4. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0 3V DE VCC1 Y D Input Generator VI Z VOD RL= 54 W ±1% CL = 50pF ± 20% VI Generator: PRR = 100 kHz, 50 % duty cycle, t r < 6ns , t f <6 ns , ZO = 50W C L includes fixture and instrumentation capacitance 50% tpLH 50W GND1 50% VOD tpHL 90% 50 % 10 % tr VOD(H) 90% tf 50 % 10% VOD(L) Figure 5. Driver Switching Test Circuit and Voltage Waveforms 6 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Y S1 3V VO D D S1 3V Y 0V Z 50% 0V DE Input Generator 50% VI Z RL = 110 W ±1 % C L = 50 pF ± 20 % VI tpZH 90% CL includes fixture and instrumentation capacitance 50 W VOH 50% VO »0V tpHZ GND1 Generator: PRR = 50 kHz, 50% duty cycle, tr <6ns, tf <6ns, ZO = 50 W GND2 Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms VCC2 D S1 3V Y 0V Z 3V Y R L = 110 W ± 1% VO S1 D Generator: PRR=50 kHz, 50% duty cycle, t r < 6ns, t f < 6ns, ZO = 50 W VI 50% 0V tpZL Z DE tpLZ C L = 50 pF ± 20 % Input Generator 50% VI VO CL includes fixture and instrumentation capacitance 50 W GND1 VCC2 50% 10% V OL GND2 Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform A IA R VA VA + VB IO V ID B VIC VB VO IB 2 Figure 8. Receiver Voltage and Current Definitions 3 V A Input Generator VI 1.5 V VI R VO 50W B GND2 Generator : PRR=100 kHz, 50% duty cycle , t < 6 ns, t < 6 ns, ZO = 50 W r f RE GND1 50% CL includes fixture and instrumentation capacitance 0 V tpLH CL = 15 pF ± 20% VO 50% tpHL 90 % 50 % 10 % 50 % tr tf VOH VOL Figure 9. Receiver Switching Test Circuit and Waveforms Copyright © 2010–2011, Texas Instruments Incorporated 7 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC A 1.5 V R VO B 0V 1 k W ±1% 0V CL includes fixture and instrumentation capacitance Input Generator tpHZ tpZH 90% VO VI 50% 50% VI CL = 15 pF± 20 % RE 3V S1 VOH 50% 50 W »0V Generator: PRR=100 kHz, 50% duty cycle, t r<6ns, t f<6ns, ZO = 50 W Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output High VCC A 0V R B 1.5 V 3V VO 1 k W ±1% S1 VI VI 50% CL = 15 pF± 20 % RE 0V CL includes fixture and instrumentation capacitance Input Generator 50% tpZL VCC 50% VO 50 W tpLZ 10% V OL Generator : PRR =100 kHz , 50 % duty cycle , t r< 6ns , t f< 6ns , Z O= 50 W Figure 11. Receiver Enable Test Circuit and Waveforms, Data Output Low 0 V or 3 V DE A Y D R Z 100 W ±1% + – Pulse Generator 15 ms duration 1% Duty Cycle tr, tf £ 100 ns 100 W ±1% B RE 0 V or 3 V + – Figure 12. Transient Over-Voltage Test Circuit 8 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) C = 0.1 mF ± 1% 2.0 V VCC 2 VCC 1 GND 1 C = 0.1 m F ±1% Y DE D 54 W S1 VOD Z A 0.8 V 1.5 V or 0 V R 54 W VOH or VOL RE B 1 kW GND 1 0 V or 1.5 V GND 2 CL = 15 pF (includes probe and jig capacitance) VTEST Figure 13. Common-Mode Transient Immunity Test Circuit tf_D tr_D 90% D1 10% tBBM tBBM 90 % D2 10 % tf_D tr_D Figure 14. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs Copyright © 2010–2011, Texas Instruments Incorporated 9 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com DEVICE INFORMATION Table 1. Driver Function Table (1) (1) INPUT ENABLE (D) (DE) Y OUTPUTS Z H H H L L H L H X L hi-Z hi-Z X OPEN hi-Z hi-Z OPEN H H L H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off) Table 2. Receiver Function Table (1) (1) 10 DIFFERENTIAL INPUT VID = (VA – VB) ENABLE (RE) OUTPUT (R) –0.02 V ≤ VID L H –0.2 V < VID –0.02 V L ? VID ≤ –0.2 V L L X H hi-Z X OPEN hi-Z Open circuit L H Short Circuit L H Idle (terminated) bus L H H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off), ? = Indeterminate Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com IEC INSULATION AND SAFETY RELATED SPECIFICATIONS FOR 16-DW PACKAGE over recommended operating conditions (unless otherwise noted) PARAMETER (1) ) TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance Shortest terminal to terminal distance through air 8.3 mm L(I02) Minimum external tracking (Creepage (1)) Shortest terminal to terminal distance across the package surface 8.1 mm CTI Tracking resistance(Comparative Tracking Index) DIN IEC 60112 / VDE 0303 Part 1 400 V Minimum Internal Gap (Internal Clearance) Distance through the insulation RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance Input to output CI Input capacitance to ground (1) 0.008 mm >1012 Ω VIO = 0.4 sin (2πft), f = 1 MHz 2 pF VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2 pF Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS Material group SPECIFICATION II Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III Rated mains voltage ≤ 400 VRMS I-II IEC 60747-5-2 INSULATION CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER VIORM Maximum working insulation voltage VPR Input to output test voltage TEST CONDITIONS SPECIFICATION UNIT 566 Vpeak Method b1, VPR = VIORM × 1.875, 100% Production test with t = 1 s, Partial discharge < 5 pC 1062 Vpeak Method a, After environmental tests subgroup 1, VPR = VIORM × 1.6, t = 10 s, Partial discharge < 5pC 906 After Input/Output Safety Test Subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 680 VIOTM Transient overvoltage t = 60 s (Qualification) t = 1 s (100% Production) 4242 Vpeak VIOSM Maximum surge voltage Tested per IEC 60065 (Qualification Test) 4242 Vpeak RS Insulation resistance Pollution degree (1) VIO = 500 V at TS 9 > 10 Ω 2 Climatic Classification 40/125/21 Copyright © 2010–2011, Texas Instruments Incorporated 11 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com REGULATORY INFORMATION VDE UL Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2) Recognized under 1577 Component Recognition Program Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Surge Voltage, 4242 VPK Maximum Working Voltage, 566 VPK Single / Basic Isolation Voltage, 2500 VRMS (1) File Number: 40016131 (Approval Pending) File Number: E181974 (Approval Pending) (1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply. Without current limiting, sufficient power is dissipated to overheat the die; and, damage the isolation barrier—potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum case temperature DW-16 MIN θJA = 80.5°C/W, VI = 3.6V, TJ = 170°C, TA = 25°C TYP MAX UNIT 500 mA 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed on the High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 600 VCC1 = VCC2 = 3.6 V Safety Limiting Current - mA 500 400 300 200 100 0 0 50 100 150 TC - Case Temperature - °C 200 Figure 15. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2 12 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com THERMAL INFORMATION ISO35T THERMAL METRIC (1) DW UNITS 16 PINS θJA Junction-to-ambient thermal resistance 80.5 θJC(TOP) Junction-to-case(top) thermal resistance 43.8 θJB Junction-to-board thermal resistance 49.7 ψJT Junction-to-top characterization parameter 13.8 ψJB Junction-to-board characterization parameter 41.4 θJC(BOTTOM) Junction-to-case(bottom) thermal resistance n/a PD (2) VCC1 = VCC2 = 3.6V, TJ = 150°C, RL = 54Ω, CL = 50pF (Driver), CL = 15pF (Receiver), Input a 0.5 MHz 50% duty cycle square wave to Driver and Receiver 373 (1) (2) °C/W mW For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. PD = Maximum device power dissipation EQUIVALENT CIRCUIT SCHEMATICS B Input A Input VCC 2 VCC 2 16V Input 36 kW 16V 36 kW 180 kW 180 k W Input 16V 36 k W 16V R Output 36 kW Y and Z Outputs VCC 1 VCC 2 16V 4W Output output 6 .5 W Copyright © 2010–2011, Texas Instruments Incorporated 16V 13 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com DE Input D, RE Input VCC 1 VCC 1 VCC 1 VCC 1 VCC 1 1 MW input 500 W input 500 W 1 MW 14 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs DATA RATE WITH NO LOAD SUPPLY CURRENT vs DATA RATE WITH LOAD 60 25 VCC1 = VCC2 = 3.3 V, No Load TA = 25°C ICC2 50 ICC - Supply Current - mA ICC - Supply Current - mA 20 PRBS Data 216 - 1 ICC2 15 10 ICC1 5 0 0 30 16 PRBS Data 2 - 1 20 200 400 600 Data Rate - Kbps 800 0 0 1000 ICC1 200 400 600 Data Rate - Kbps 800 Figure 16. Figure 17. DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE RECEIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE 1000 100 VCC1 = VCC2 = 3.3 V, VCC1 = VCC2 = 3.3 V, CL = 15 pF Receiver Propagation Delay - ns RL = 54 W, CL = 50 pF, 225 Driver Propagation Delay - ns Driver: RL = 54 W, CL = 50 pF, Receiver: CL = 15 pF TA = 25°C 10 230 220 215 VCC1 = VCC2 = 3.3 V, 40 tPHL 210 tPLH 205 90 tPHL 80 tPLH 200 195 -40 -15 10 35 60 TA - Free-Air Temperature - °C Figure 18. Copyright © 2010–2011, Texas Instruments Incorporated 85 70 -40 -15 10 35 60 TA - Free-Air Temperature - °C 85 Figure 19. 15 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DRIVER RISE, FALL TIME vs FREE-AIR TEMPERATURE RECEIVER RISE, FALL TIME vs FREE-AIR TEMPERATURE 1200 220 VCC1 = VCC2 = 3.3 V, CL = 15 pF VCC1 = VCC2 = 3.3 V, RL = 54 W, CL = 50 pF 1100 Receiver Rise, Fall Time - ps Driver Rise, Fall Time - ns 215 210 205 200 tr tf 195 1000 800 tr 700 190 185 -40 -15 10 35 60 TA - Free-Air Temperature - °C 600 -40 85 -15 10 35 60 TA - Free-Air Temperature - °C Figure 20. Figure 21. DIFFERENTIAL OUTPUT VOLTAGE vs LOAD CURRENT RECEIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 85 140 3.5 VCC2 = 3.6 V o TA = 25 C 120 3 VCC2 = 3.3 V 100 2.5 IO - Output Current - mA VOD - Differential Output Voltage - V tf 900 2 VCC2 = 3 V 1.5 100 W 1 80 60 40 50 W 20 0.5 TA = 25°C 0 0 0 10 20 30 40 50 IL - Load Current - mA Figure 22. 16 60 70 0 1 2 3 4 5 VO - Output Voltage - V Figure 23. Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) RECEIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE BUS INPUT CURRENT vs INPUT VOLTAGE -120 60 o TA = 25 C TA = 25°C 40 II - Bus Input Current - mA IO - Output Current - mA -100 -80 -60 -40 20 0 VCC = 3.3 V -20 -40 -20 0 0 1 2 VO - Output Voltage - V Figure 24. Copyright © 2010–2011, Texas Instruments Incorporated 3 4 -60 -7 -4 -1 2 5 8 11 14 VI - Bus Input Voltage - V Figure 25. 17 ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION REFERENCE DESIGN ISO35T Reference design (sluu470) and miniature evaluation boards are available to provide a complete isolated data and power solution. TRANSIENT VOLTAGES Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast transients that occur after installation and the transient ratings of ISO35T are sufficient for all but the most severe installations. However, some equipment manufacturers use their ESD generators to test transient susceptibility of their equipment and can easily exceed insulation ratings. ESD generators simulate static discharges that may occur during device or equipment handling with low-energy but very high voltage transients. Figure 26 models the ISO35T bus IO connected to a noise generator. CIN and RIN is the device and any other stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and resistance between GND1 and GND2 of ISO35T plus those of any other insulation (transformer, etc.), and we assume stray inductance negligible. From this model, the voltage at the isolated bus return is Z ISO vGND2 = vN ZISO + ZIN and will always be less than 16 V from V . N 4 If ISO35T is tested as a stand-alone device, RIN= 6 × 10 Ω, CIN= 16 × 10-12 F, RISO= 109Ω and CISO= 10-12 F. . Note from Figure 26 that the resistor ratio determines the voltage ratio at low frequency and it is the inverse capacitance ratio at high frequency. In the stand-alone case and for low frequency, vGND2 RISO 109 = = vN RISO + RIN 109 + 6 ´ 104 . or essentially all noise appears across the barrier. . . A,B, Y, or Z C IN R IN VN 16 V Bus Return(GND2) At very high frequency, v GND2 vN = 1 CISO 1 1 + CISO CIN = 1+ 1 = CISO CIN C ISO 1 1+ 1 16 R ISO = 0.94 and 94% of VN appears across the barrier. As long as RISO is greater than RIN and CISO is less than CIN, most of transient noise appears across the isolation barrier, as it should. System Ground (GND1) Figure 26. Noise Model We recommend the reader not test equipment transient susceptibility with ESD generators or consider product claims of ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through recessing or covering connector pins in a conductive connector shell and installer training. 18 Copyright © 2010–2011, Texas Instruments Incorporated ISO35T SLLSE26C – NOVEMBER 2010 – REVISED AUGUST 2011 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A • Changed the data sheet From: Product Preview To: Production data ................................................................................. 1 Changes from Revision A (March 2011) to Revision B • Page Page Changed pin 16 From: VCC1 To: VCC2 in the DW Package drawing ..................................................................................... 1 Changes from Revision B (June 2011) to Revision C Page • Deleted MIN and MAX values from the tr_D, tf_D, and tBBM specifications in theTransformer Driver Chara table. ................ 5 • Changed conditions statement from 1.9V to 2.4V; and changed TYP value from 230 to 350 for fSt specification in Transformer Driver Characteristics table. ............................................................................................................................. 5 • Added "D1 and D2 connected to 50-Ω pull-up resistors" to conditions statement for tr_D, tf_D, and tBBM specifications in theTransformer Driver Chara table. .................................................................................................................................. 5 Copyright © 2010–2011, Texas Instruments Incorporated 19 PACKAGE OPTION ADDENDUM www.ti.com 31-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ISO35TDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO35TDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO35TDWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO35TDWR SOIC DW 16 2000 533.4 186.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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