MAS MAS9180A1UC06 Am receiver ic Datasheet

DA9180.004
15 September, 2005
MAS9180
AM Receiver IC
• Single Band Receiver IC
• High Sensitivity
• Very Low Power Consumption
• Wide Supply Voltage Range
• Power Down Control
• Control for AGC On
• High Selectivity by Crystal Filter
• Fast Startup Feature
DESCRIPTION
The MAS9180 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to receive
time signals in the frequency range from 40 kHz to 100
kHz. Only a few external components are required for
time signal receiver. The circuit has preamplifier, wide
range automatic gain control, demodulator and output
comparator built in. The output signal can be
processed directly by an additional digital circuitry to
extract the data from the received signal. The control
for AGC (automatic gain control) can be used to switch
AGC on or off if necessary.
MAS9180 has both differential and asymmetric input
options and also options for compensating shunt
capacitances of different crystals (See ordering
information on page 15).
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
Single Band Receiver IC
Highly Sensitive AM Receiver, 0.4 µVRMS typ.
Wide Supply Voltage Range from 1.1 V to 5.5 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Both Differential and Asymmetric Input Versions
Crystal Compensation Capacitance Options
Single Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
QOP
QI
AGC Amplifier
RFIM
AON
QOM
RFIP
Demodulator
&
Comparator
OUT
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
1 (15)
DA9180.004
15 September, 2005
MAS9180 PAD LAYOUT
VDD
VSS
QOP
RFIM
QOM
RFIP
QI
PDN
AGC
AON
OUT
DEC
1456 µm
MAS9180Ax,
x = 1..5 differential input,
B..F asymmetric input
1474 µm
DIE size = 1.47 x 1.46 mm; PAD size = 80 x 80 µm
Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left
floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Name
X-coordinate
Y-coordinate
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
VDD
QOP
QOM
QI
174 µm
174 µm
174 µm
174 µm
1262 µm
1057 µm
854 µm
648 µm
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
174 µm
175 µm
1295 µm
1295 µm
1295 µm
1295 µm
1295 µm
1282 µm
444 µm
240 µm
225 µm
425 µm
624 µm
825 µm
1039 µm
1200 µm
Note
4
1
2
3
5
5
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
3) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
4) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left
unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.
5) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
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15 September, 2005
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature
Storage Temperature
VDD-VSS
VIN
PMAX
TOP
TST
Conditions
Min
Max
Unit
-0.3
VSS-0.3
6
VDD+0.3
100
+85
+150
V
V
mW
o
C
o
C
-40
-55
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25°C
Parameter
Operating Voltage
Current Consumption
Symbol
VDD
IDD
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
IDDoff
fIN
VIN min
VIN max
RRFI
CRFI
Receiver Input Resistance
Receiver Input Capacitance
RRFI
CRFI
Input Levels |lIN|<0.5 µA
VIL
VIH
|IOUT|
Output Current
VOL<0.2 VDD;VOH >0.8 VDD
Output Pulse
T100ms
T200ms
T500ms
T800ms
Startup Time
TStart
Output Delay Time
TDelay
Conditions
Min
Typ
1.10
VDD=1.4 V, Vin=0 µVrms
VDD=1.4 V, Vin=20 mVrms
VDD=3.6 V, Vin=0 µVrms
VDD=3.6 V, Vin=20 mVrms
31
27
64
37
67
40
40
0.4
Max
Unit
5.5
V
µA
91
65
0.1
100
1
20
Differential Input
MAS9180A1..5
f=40 kHz..77.5 kHz
Asymmetric Input
MAS9180AB..F
f=40 kHz..77.5 kHz
µVrms
mVrms
330
4.5
kΩ
pF
670
6.4
kΩ
pF
0.2 VDD
0.8 VDD
5
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
1 µVrms ≤ VIN ≤
20 mVrms
Fast Start-up, Vin=0.4 µVrms
Fast Start-up, Vin=20 mVrms
µA
kHz
V
µA
50
140
ms
150
230
ms
400
500
600
ms
700
800
900
ms
1.3
3.5
50
s
100
ms
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15 September, 2005
TYPICAL APPLICATION
Note 1
MAS9180A1
Note 5
Ferrite
Antenna
QOP
Note 4
Optional
Control
for AGC on/hold
QI
Demodulator
&
Comparator
AGC Amplifier
RFIM
AON
QOM
RFIP
OUT
Receiver
Output
Power Supply/Biasing
VDD
VSS
AGC
PDN
DEC
CAGC +
10 µF
1.4 V
CDEC
47 nF
Note 2
Note 3
Power Down /
Fast Startup
Control
Figure 1
Application circuit of differential input and internal compensation capacitance option version
MAS9180A1.
Note 1
CC_EXT=C0
Note 4
Optional
MAS9180A5
Control
for AGC on/hold
Note 5
Ferrite
Antenna
QOP
QI
AGC Amplifier
RFIM
AON
QOM
RFIP
Demodulator
&
Comparator
OUT
Receiver
Output
Power Supply/Biasing
VDD
1.4 V
Figure 2
VSS
PDN
AGC
CAGC +
10 µF
DEC
CDEC
47 nF
Note 3
Note 2
Power Down /
Fast Startup
Control
Application circuit of differential input and external compensation capacitance option version
MAS9180A5.
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15 September, 2005
TYPICAL APPLICATION (Continued)
Note 1
Note 4
Optional
Control
for AGC on/hold
MAS9180A5
QOP
Note 5
QI
AON
QOM
RFIP
Ferrite
Antenna
AGC Amplifier
RFIM
Antenna
Frequency
Selection
Demodulator
&
Comparator
OUT
Receiver
Output
Power Supply/Biasing
VDD
VSS
AGC
PDN
DEC
CAGC +
10 µF
1.4 V
CDEC
47 nF
Note 3
Note 2
Power Down /
Fast Startup
Control
Figure 3
Dual band application circuit of differential input and external compensation capacitance option
version MAS9180A5.
Note 1
Note 4
Optional
MAS9180AB..E
Control
for AGC on/hold
Note 5
Ferrite
Antenna
QOP
QI
AGC Amplifier
RFIM
AON
QOM
RFIP
Demodulator
&
Comparator
OUT
Receiver
Output
X
Power Supply/Biasing
VDD
1.4 V
Figure 4
VSS
PDN
AGC
CAGC +
10 µF
DEC
CDEC
47 nF
Note 2
Note 3
Power Down /
Fast Startup
Control
Application circuit of asymmetric input and internal compensation capacitance version option
MAS9180AB..E.
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15 September, 2005
TYPICAL APPLICATION (Continued)
Note 1
MAS9180AF
QOP
Note 5
CC_EXT=C0
QI
Note 4
Optional
Control
for AGC on/hold
AON
QOM
RFIP
Ferrite
Antenna
Demodulator
&
Comparator
AGC Amplifier
RFIM
OUT
Receiver
Output
X
Power Supply/Biasing
VDD
VSS
AGC
PDN
CAGC +
10 µF
1.4 V
Figure 5
DEC
CDEC
47 nF
Note 3
Note 2
Power Down /
Fast Startup
Control
Application circuit of asymmetric input and external compensation capacitance option version
MAS9180AF.
Note 1
Note 4
Optional
Control
for AGC on/hold
MAS9180AF
Note 5
QOP
QI
RFIP
Ferrite
Antenna
AGC Amplifier
RFIM
AON
QOM
Demodulator
&
Comparator
OUT
Receiver
Output
X
Antenna
Frequency
Selection
Power Supply/Biasing
VDD
1.4 V
Figure 6
VSS
PDN
AGC
CAGC +
10 µF
DEC
CDEC
47 nF
Note 3
Note 2
Power Down /
Fast Startup
Control
Dual band application circuit of asymmetric input and external compensation capacitance
option version MAS9180AF.
6 (15)
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15 September, 2005
TYPICAL APPLICATION (Continued)
Note 1: Crystals
The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The
crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance
compensation capacitor CC of MAS9180. MAS9180A5 and MAS9180AF are options for external crystal
compensation capacitor. The external compensation capacitor should be matched similarly as well as possible
with crystals shunt capacitance. See Compensation Capacitance Options on table 2.
Table 1 Time-Signal System Frequencies
Time-Signal System
Location
Antenna Frequency
Recommended Crystal Frequency
DCF77
HGB
MSF
WWVB
JJY
BPC
77.5 kHz
75 kHz
60 kHz
60 kHz
40 kHz and 60 kHz
68.5 kHz
77.503 kHz
75.003 kHz
60.003 kHz
60.003 kHz
40.003 kHz and 60.003 kHz
68.505 kHz
Germany
Switzerland
United Kingdom
USA
Japan
China
Table 2 Compensation Capacitance Options
Crystal Description
Device
CC
Input
MAS9180A1
MAS9180A5
MAS9180AB
MAS9180AC
MAS9180AD
MAS9180AE
MAS9180AF
Differential
Differential
Asymmetric
Asymmetric
Asymmetric
Asymmetric
Asymmetric
0.75 pF
CC_EXT
0.75 pF
1.25 pF
1.5 pF
2.5 pF
CC_EXT
For low C0 crystal
For any crystals, external compensation capacitor
For low C0 crystal
For low C0 crystal
For low C0 crystal
For low C0 crystal
For any crystals, external compensation capacitor
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of
floating crystal shunt capacitance. For example crystal with 1 pF floating package shunt capacitance can have
0.85 pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance
should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance
mismatching.
In dual band receiver configuration the crystals can be connected in parallel thus external compensation
capacitor value CC_EXT must be sum of two crystals’ shunt capacitances. Instead of parallel crystal connection it is
also possible to connect other crystal from QOP pin and the other crystal from QOM pin to common QI pin (figure
3). In this circuit configuration no external compensation capacitor is required since the crystals compensate
each other. The sensitivity of dual band receiver configuration will be lower than that of single band receiver
configuration since the noise band width of crystal filter with two parallel crystals is double.
Table 3 below presents some crystal manufacturers having suitable crystals for timesignal receiver application.
Table 3. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application
Manufacturer
Crystal Type
Dimensions
Web Link
Citizen
Epson
KDS Daishinku
Microcrystal
Seiko
Instruments
CFV-206
C-2-Type
C-4-Type
DT-261
MX1V-L2N
MX1V-T1K
VTC-120
ø 2.0 x 6.0
ø 1.5 x 5.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 6.0
ø 2.0 x 8.1
ø 1.2 x 4.7
http://www.citizen.co.jp/tokuhan/quartz/
http://www.epsondevice.com/e/
http://www.kdsj.co.jp/english.html
http://www.microcrystal.com/
http://speed.sii.co.jp/pub/compo/quartz/topE.jsp
7 (15)
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15 September, 2005
TYPICAL APPLICATION (Continued)
Note 2: AGC Capacitor
The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the
capacitors. The insulation resistance of these capacitors should be at minimum 100 MΩ. Also probes with at
least 100 MΩ impedance should be used for voltage probing of AGC and DEC pins. DEC capacitor can be low
leakage chip capacitor.
Note 3: Power Down / Fast Startup Control
Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if
PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered automatically by the falling edge
of PDN signal, i.e., controlling device from power down to power up. The VDD must be high before falling edge of
PDN to guarantee proper operation of fast startup circuitry. The startup time without proper fast startup control
can be several minutes but with fast startup it is shortened typically to few seconds.
Note 4: Optional Control for AGC On/Hold
AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected.
Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive etc. can produce
disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can be avoided by
controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC (AON=VDD) when
motors are not driven.
Note 5: Ferrite Antenna
The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in
determining receiver performance. Recommended antenna impedance at resonance is around 150 kΩ.
Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand
high antenna impedance corresponds to high noise but also large signal. The optimum performance where
signal-to-noise ratio is at maximum is achieved in between.
The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by
the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from
extensive tuning accuracy requirements and possible tuning drifts by the temperature.
Antenna impedance can be calculated using equation 1 where f0, L, Qant and C are resonance frequency, coil
inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is
defined by ratio of resonance frequency f0 and antenna bandwidth B (equation 2).
Rantenna = 2π ⋅ f 0 ⋅ L ⋅ Qantenna =
Qantenna =
Qantenna
1
=
2π ⋅ f 0 ⋅ C 2π ⋅ B ⋅ C
f0
B
Equation 1.
Equation 2.
Table 4 below presents some antenna manufacturers for timesignal application.
Table 4. Antenna Manufacturers and Antenna Types in Alphaphetical Order for Timesignal Application
Manufacturer
Antenna Type
Dimensions
Web Link
HR Electronic GmbH
Sumida
60716 (60kHz)
60708 (77.5kHz)
ACL80A (40kHz)
ø 10 x 60 mm
http://www.hrelectronic.com/
ø 10 x 80 mm
http://www.sumida.com/
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MAS9180 SAMPLES IN SBDIL 20 PACKAGE
NC 1
20 VSS
19 NC
18 RFIM
VDD 2
NC 3
NC 6
QI 7
AGC 8
9180Az
YYWW
XXXXX.X
QOP 4
QOM 5
17 RFIP
16 NC
15 NC
14 PDN
13 AON
NC 9
12 DEC
11 NC
OUT 10
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
z=Sample Version Number
PIN DESCRIPTION
Pin Name
Pin
NC
VDD
NC
QOP
QOM
1
2
3
4
5
NC
QI
6
7
AGC
NC
OUT
NC
DEC
AON
PDN
NC
NC
RFIP
RFIM
NC
VSS
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AI
Function
Note
Positive Power Supply
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for External
Compensation Capacitor or Second Crystal
5
1
AO
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
DO
Receiver Output
2
AO
DI
DI
Demodulator Capacitor
AGC On Control
Power Down Input
3
4
AI
AI
Positive Receiver Input
Negative Receiver Input
6
6
G
Power Supply Ground
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left
unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.
6) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
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15 September, 2005
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VSS
RFIM
NC
RFIP
NC
PDN
AON
DEC
9180Az
YYWW
VDD
QOP
QOM
NC
QI
AGC
NC
OUT
Top Marking Definitions:
z = Version Number
YYWW = Year Week
PIN DESCRIPTION
Pin Name
Pin
Type
Function
Note
VDD
QOP
QOM
1
2
3
P
AO
AO
NC
QI
4
5
Positive Power Supply
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for
External Compensation Capacitor or
Second Crystal
AI
AGC
NC
OUT
DEC
AON
PDN
NC
RFIP
NC
RFIM
VSS
6
7
8
9
10
11
12
13
14
15
16
AO
Quartz Filter Input for Crystal and
External Compensation Capacitor
AGC Capacitor
DO
AO
DI
DI
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
3
4
AI
Positive Receiver Input
6
AI
G
Negative Receiver Input
Power Supply Ground
6
5
1
2
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pin 4 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up (to AGC on) with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left
unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.
6) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
10 (15)
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PACKAGE (TSSOP16) OUTLINES
C
E
D
Seating Plane
B
F
G
H
A
O
Pin 1
B
Detail A
B
L
I
I1
K
P
Section B-B
J1
M
J
Dimension
N
Min
A
B
C
D
E
F
G
H
I
I1
J
J1
K
L
M
(The length of a terminal for
soldering to a substrate)
N
O
P
Detail A
4.30
0.05
0.19
0.18
0.09
0.09
0.19
0.19
0°
0.24
0.50
Max
6.40 BSC
5.00 BSC
0.65 BSC
4.50
0.15
1.10
0.30
0.28
0.20
0.16
0.30
0.25
8°
0.26
0.75
1.00 REF
12°
12°
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Dimensions do not include mold flash, protrusions, or gate burrs.
All dimensions are in accordance with JEDEC standard MO-153.
11 (15)
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SOLDERING INFORMATION
◆ For Eutectic Sn/Pb TSSOP-16
Resistance to Soldering Heat
Maximum Temperature
Maximum Number of Reflow Cycles
Reflow profile
Seating Plane Co-planarity
Lead Finish
According to RSH test IEC 68-2-58/20 2*220°C
240°C
2
Thermal profile parameters stated in JESD22-A113 should not
be exceeded. http://www.jedec.org
max 0.08 mm
Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15%
◆ For Pb-Free, RoHS Compliant TSSOP-16
Resistance to Soldering Heat
Maximum Temperature
Maximum Number of Reflow Cycles
Reflow profile
Seating Plane Co-planarity
Lead Finish
According to RSH test IEC 68-2-58/20
260°C
3
Thermal profile parameters stated in IPC/JEDEC J-STD-020
should not be exceeded. http://www.jedec.org
max 0.08 mm
Solder plate 7.62 - 25.4 µm, material Matte Tin
12 (15)
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15 September, 2005
EMBOSSED TAPE SPECIFICATIONS
Tape Feed Direction
P0
D0
P2
A
E1
F1
W
D1
A
A0
P
Tape Feed Direction
T
Section A - A
B0
S1
K0
Pin 1 Designator
Dimension
Min
Max
Unit
A0
B0
D0
D1
E1
F1
K0
P
P0
P2
S1
T
W
6.50
5.20
6.70
5.40
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
1.50
1.65
7.20
1.20
11.90
1.95
0.6
0.25
11.70
1.50 +0.10 / -0.00
4.0
1.85
7.30
1.40
12.10
2.05
0.35
12.30
13 (15)
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15 September, 2005
REEL SPECIFICATIONS
W2
A
D
C
Tape Slot for Tape Start
N
B
W1
2000 Components on Each Reel
Reel Material: Conductive, Plastic Antistatic or Static Dissipative
Carrier Tape Material: Conductive
Cover Tape Material: Static Dissipative
Carrier Tape
Cover Tape
End
Start
Trailer
Dimension
A
B
C
D
N
W1
(measured at hub)
W2
(measured at hub)
Trailer
Leader
Weight
Leader
Components
Min
1.5
12.80
20.2
50
12.4
160
390,
of which minimum 160
mm of empty carrier tape
sealed with cover tape
Max
Unit
330
14.4
mm
mm
mm
mm
mm
mm
18.4
mm
13.50
mm
mm
1500
g
14 (15)
DA9180.004
15 September, 2005
ORDERING INFORMATION
Product Code
Product
Description
Capacitance Option
MAS9180A1TC00
Single Band AM-Receiver IC
with Differential Input
Single Band AM-Receiver IC
with Differential Input
Single Band AM-Receiver IC
with Differential Input
Single Band AM-Receiver IC
with Differential Input
Single Band AM-Receiver IC
with Asymmetric Input
Single Band AM-Receiver IC
with Asymmetric Input
Single Band AM-Receiver IC
with Asymmetric Input
Single Band AM-Receiver IC
with Asymmetric Input
Single Band AM-Receiver IC
with Asymmetric Input
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
TSSOP-16,
Tape & Reel
TSSOP-16, Pb-free, RoHS
compliant, Tape & Reel
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
EWS-tested wafer,
Thickness 400 µm.
CC = 0.75 pF
MAS9180A5TC00
MAS9180A1UA06
MAS9180A1UC06
MAS9180ABTC00
MAS9180ACTC00
MAS9180ADTC00
MAS9180AETC00
MAS9180AFTC00
External compensation
capacitor
CC = 0.75 pF
CC = 0.75 pF
CC = 0.75 pF
CC = 1.25 pF
CC = 1.5 pF
CC = 2.5 pF
External compensation
capacitor
Contact Micro Analog Systems Oy for other wafer thickness options.
◆ The formation of product code
An example for MAS9180A1TC00:
MAS9180 A
1
Product
Design
Input type and
name
version
capacitance option:
Differential input
and CC = 0.75 pF
TC
Package type:
TC = 400 µm thick EWS tested wafer
UA = TSSOP16 (Pb/Sn)
UC = TSSOP16 (Pb-free, RoHS compliant)
00
Delivery format:
00 = bare wafer
06 = Tape &
Reel
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits
shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no
claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and
Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or
modification.
15 (15)
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