WJ FP31QF-PCB2140 2-watt hfet Datasheet

FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
•
•
•
•
•
•
Mobile Infrastructure
CATV / DBS
W-LAN / ISM
RFID
Defense / Homeland Security
Fixed Wireless
Saturated Drain Current, Idss
Transconductance, Gm
Pinch Off Voltage, Vp (1)
RF Parameter (2)
Operational Bandwidth
Test Frequency
Small Signal Gain
Maximum Stable Gain
Output P1dB
Output IP3 (3)
Noise Figure
GND
GND
GND
GND
26
GND
GND
27
25
24
23
22
21 GND
GND 2
20 GND
GATE / 3
RF IN
The product is targeted for use as driver amplifiers for
wireless infrastructure where high performance and high
efficiency are required.
19 DRAIN /
RF OUT
16 GND
GND 7
15 GND
8
9
10
11
12
Function
Gate /
RF Input
Drain /
RF Output
13
14
GND
17 GND
GND 6
GND
18 GND
GND 5
GND
GND 4
GND
The device conforms to WJ Communications’ long
history of producing high reliability and quality
components. The FP31QF has an associated MTTF of a
minimum of 100 years at a mounting temperature of
85°C. All devices are 100% RF & DC tested.
Pin No.
3
19
All other pins &
backside copper
Ground
Typical Performance (4)
Specifications
DC Parameter
28
GND 1
GND
Applications
The FP31QF is a high performance 2-Watt HFET
(Heterostructure FET) in a low-cost lead-free 28-pin 6x6
mm QFN (Quad Flatpack, No-Lead) surface-mount
package. This device works optimally at a drain bias of
+9 V and 450 mA to achieve +46 dBm output IP3
performance and an output power of +34 dBm at 1-dB
compression.
GND
50 – 4000 MHz
18 dB Gain @ 900 MHz
+34 dBm P1dB
+46 dBm Output IP3
High Drain Efficiency
Pb-free 6mm 28-pin QFN package
MTTF > 100 years
Functional Diagram
GND
•
•
•
•
•
•
•
Product Description
GND
Product Features
Units Min
mA
mS
V
Max
1170
590
-2.0
Units Min
MHz
MHz
dB
dB
dBm
dBm
dB
Typ
Typ
50
Max
4000
800
18
24
+34
+46
3.5
Parameter
Units
Frequency
Gain
S11
S22
Output P1dB
Output IP3 (3)
Noise Figure
IS-95 Channel Power
@ -45 dBc ACPR
W-CDMA Ch. Power
@ -45 dBc ACLR
(5)
Drain Voltage
Drain Current (5)
MHz
dB
dB
dB
dBm
dBm
dB
dBm
Typical
915
18
-20
-12
+34
+46
3.5
1960 2140 2450
13.5
13
12
-20
-18
-18
-11
-24
-15
+33.8 +33.2 +33.5
+46.8 +46.6 +46.8
4.5
4.6
4.6
+27.8 +27.3
dBm
V
mA
+25
+9
450
1. Pinch-off voltage is measured when Ids = 4.8 mA.
2. Test conditions unless otherwise noted: T = 25ºC, VDS = 9 V, IDQ = 450 mA, in a tuned application
circuit with ZL = ZLOPT, ZS = ZSOPT (optimized for output power).
3. 3OIP measured with two tones at an output power of +18 dBm/tone separated by 1 MHz. The
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
4. Typical parameters represent performance in an application circuit.
5. Empirical measurements showed optimal power performance at a drain voltage = 9 volts at 450 mA.
Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance
may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million
hours MTTF rating, the biasing condition should maintain a junction temperature below 160° C over all
operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5° C/W +
(maximum operating temperature).
Absolute Maximum Rating
Ordering Information
Parameter
Operating Case Temperature
Storage Temperature
DC Power
RF Input Power (continuous)
Drain to Gate Voltage, Vdg
Junction Temperature
Rating
-40 to +85 °C
-55 to +125 °C
7.5 W
6 dB above Input P1dB
+14 V
+220° C
Part No.
Description
2-Watt HFET
FP31QF
(Leaded QFN Pkg)
2-Watt HFET
FP31QF-F
(lead-free/RoHS-compliant QFN Pkg)
FP31QF-PCB900
FP31QF-PCB1900
FP31QF-PCB2140
870 – 960 MHz Application Circuit
1930 – 1990 MHz Application Circuit
2110 – 2170 MHz Application Circuit
Operation of this device above any of these parameters may cause permanent damage.
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Typical Device Data
S-Parameters (VDS = +9 V, IDS = 450 mA, T = 25°C, calibrated to device leads)
S22
0
4.
5 .0
2
10
-1 0. 0
1
0
1.0
-3
.0
2.
0
-0
.6
10.0
.0
-2
.4
-0
.0
-2
Swp Min
0.01GHz
Swp Min
0.01GHz
-1.0
-0 .8
3
-1.0
2.5
-0 .8
2
-0
.6
1.5
Frequency (GHz)
-3
.0
1
5.0
4.0
3.0
2.0
1.0
0.8
-4
.0
.4
-0
0.5
-4
.0
DB(MSG)
0
0
1
2
- 0.
- 5.
DB(|S[2,1]|)
2
0
- 0.
0.6
10 .0
0.4
0
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0.2
0
5 .0
0.2
0 .2
10 .0
2
0
4.
6
5
4
3
0 .2
3
0
3.
-1 0. 0
0.
4
S21, MSG (dB)
0. 8
2.
0
0
3.
4
20
0.
4
6
5
Swp Max
6GHz
6
0.
0. 8
6
0.
Swp Max
6GHz
- 5.
1.0
S11
S21, Maximum Stable Gain vs. Frequency
30
Note:
Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines.
The S-parameters shown are the de-embedded data down to the device leads and represents typical performance of the device.
Freq (MHz)
50
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
3000
3250
3500
3750
4000
S11 (mag)
S11 (ang)
S21 (mag)
S21 (ang)
S12 (mag)
S12 (ang)
S22 (mag)
0.985
-21.82
24.458
166.25
0.006
76.01
0.096
0.936
-88.63
17.968
128.52
0.020
43.34
0.329
0.913
-128.61
11.520
104.42
0.025
22.03
0.431
0.899
-148.43
8.132
90.03
0.026
10.75
0.465
0.900
-160.54
6.225
79.35
0.026
4.56
0.490
0.900
-169.15
4.988
70.50
0.025
0.35
0.514
0.900
-176.01
4.125
62.56
0.025
-2.975
0.532
0.905
178.53
3.504
55.28
0.024
-4.91
0.560
0.909
172.99
3.046
47.93
0.023
-5.54
0.587
0.910
168.27
2.656
41.65
0.022
-4.44
0.606
0.914
164.14
2.349
34.95
0.021
-1.12
0.629
0.914
160.09
2.117
28.98
0.021
5.24
0.656
0.915
156.76
1.897
23.31
0.022
12.75
0.671
0.922
153.22
1.721
17.69
0.026
23.36
0.695
0.926
149.22
1.563
11.97
0.034
32.54
0.720
0.941
144.67
1.433
6.20
0.058
34.08
0.734
0.943
140.45
1.318
0.98
0.102
23.74
0.768
Device S-parameters are available for download off of the website at: http://www.wj.com
S22 (ang)
-110.34
-135.13
-151.01
-158.3
-162.14
-163.92
-166.86
-168.72
-170.95
-172.86
-175.13
-177.13
-179.41
177.36
175.05
171.21
165.82
Load-Pull Data at 1.96 and 2.14 GHz
(Vds = 8 V, Ids = 500 mA, 25°C, ZS = 50 Ω, calibrated to device pins)
ZS (Ω)
5 + j0
5 - j2
ZL (Ω)
8 - j2
8 - j3
Gain (dB)
18.5
18.0
P1dB (dBm) OIP3 (dBm)
+34
+48
+34
+48
P1dB
0.
4
3.
0.8
1.96 GHz
r 8 Ohm
x -2 Ohm
Swp Max
1.96GHz
2.
0
6
0.
2.
0
0.
6
0.8
1.0
Output IP3
Swp Max
1.96GHz
0.
4
1.96 GHz
r 8 Ohm
x -2 Ohm
PAE (%)
49
50
1.0
Freq (GHz)
1.96
2.14
0
4.
0
3.
0
0
4.
5. 0
5. 0
0. 2
0.2
10.0
5.0
4.0
3.0
2.0
1.0
0.8
48
0.6
0.4
0.2
10.0
0
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0
0.2
10.0
47
33
46
45
-1 0.0
43
42
41
0
-4
.0
.4
-0
0
.0
-2
-0.8
Swp Min
1e-009GHz
P1dB max (1.96 GHz) = +34 dBm at ZL = 8 - j2 Ω
-1.0
.6
-0
-1.0
-0.8
-0
.6
-2
.0
-3
.
.4
-0
- 5.
27
44
-3
.0
28
-4
.0
29
2
-0 .
0
-
30
0.2
-5.
31
-10.0
32
Swp Min
1e-009GHz
OIP3 max (1.96 GHz) = +48 dBm at ZL = 8 - j2 Ω
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Application Circuit: 870 – 960 MHz (FP31QF-PCB900)
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
Frequency
S21 – Gain
S11 – Input Return Loss
S22 – Output Return Loss
Output P1dB
Output IP3
(+18 dBm / tone, 1 MHz spacing)
Noise Figure
IS-95 Channel Power
@ -45 dBc ACPR
MHz
dB
dB
dB
dBm
870
18.3
-15
-9.3
+33.9
915
18
-20
-12
+34
dBm
960
17.7
-16
-16
+33.7
+46
dB
3.4
dBm
3.5
3.5
+27.8
Bill of Materials
C2
Ref. Desig.
C1, C4, C8, C10
C2, C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
C3
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 Ω.
•
•
•
•
Value
100 pF
4.7 pF
0.018 µF
1000 pF
0.1 µF
27 nH
3.3 nH
10 Ω
51 Ω
FP31QF
Part style
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Wirewound chip inductor
Multilayer chip inductor
Chip resistor
Chip resistor
WJ 2W HFET
Do Not Place
Size
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
The C2 and C3 placements are at silk screen markers, “H” and “9.5”, respectively.
The via hole spacing along the main microstrip line is .040”.
The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
CA P
CA P
CAP
ID=C6
ID =C7
ID=C8
C=10 0 pF C =100 0 pF C=1.8e 4 pF
-Vgg
Vds=9V @ 450 mA
CAP
ID=C12
C=1e 5 pF
RES
ID=R2
R=51 Ohm
CAP
ID=C11
C=1.8e 4 pF
CAP
ID=C5
C=DNP pF
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=10 0 pF
TL INP
ID=TL1
Z0 =50 Ohm
L =500 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
IND
ID=L3
L =3.3 nH
IND
ID=L1
L =2 7 nH
CAP
ID =C10
C =10 0 pF
IND
ID=L2
L =2 7 nH
2
CAP
P ORT
ID=C4
P =2
C=10 0 pF Z=50 Ohm
1
CAP
ID=C2
C=4.7 pF
RES
ID=R1
R=10 Ohm
SUB CKT
ID=Q1
NET="FP31QF"
TL INP
ID=TL2
Z0 =50 Ohm
L =520 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
CAP
ID=C3
C=4.7 pF
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
FP31QF-PCB900 Application Circuit Performance Plots
S11 vs. Frequency
S21 vs. Frequency
-10
-15
-20
-5
18
17
-25
16
-30
860
15
860
-40c
880
900
920
940
960
880
900
960
30
940
3
2
1
+85c
920
4
-40c
0
860
960
-40 C
+85c
880
900
920
940
22
960
IMD products (dBm)
46
44
freq = 915, 916 MHz
+18 dBm / tone
IMD_Low
IMD_High
-80
4
8
Temperature (°C)
12
16
20
Output Power (dBm)
24
Output Power / Gain vs. Input Power
Output Power / Gain vs. Input Power
frequency = 915 MHz, Temp = -40° C
frequency = 915 MHz, Temp = +25° C
32
18
16
28
14
24
12
20
Output Power
16
10
0
4
8
12
Input Power (dBm)
16
20
Gain (dB)
20
Output Power (dBm)
Gain
36
26
27
28
29
45
40
30
85
28
36
20
32
18
16
28
14
24
20
Output Power
10
16
-4
0
4
8
12
Input Power (dBm)
16
8
12
16
20
Output Power (dBm)
24
28
Output Power / Gain vs. Input Power
Gain
12
4
Gain (dB)
60
25
35
Output Power (dBm)
35
24
OIP3 vs. Output Power
-40
-60
+85 C
fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C
50
-100
20
23
IMD products vs. Output Power
48
+25 C
Output Channel Power (dBm)
fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C
-20
10
-60
-70
OIP3 vs. Temperature
-15
-50
Frequency (MHz)
50
-4
+25c
OIP3 (dBm)
900
+25c
960
freq = 915 MHz
Frequency (MHz)
40
-40
940
IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW
-40
ACPR (dBc)
NF (dB)
32
42
920
Frequency (MHz)
5
880
900
+85c
ACPR vs. Channel Power
6
26
860
880
+25c
Frequency (MHz)
-40c
OIP3 (dBm)
-40c
-30
860
Noise Figure vs. Frequency
28
Gain (dB)
940
-20
-25
+85c
920
-15
Frequency (MHz)
34
18
+25c
-10
P1dB vs. Frequency
36
P1dB (dBm)
19
+85c
S21 (dB)
S11 (dB)
+25c
0
S22 (dB)
-40c
-5
S22 vs. Frequency
20
frequency = 915 MHz, Temp = +85° C
36
32
Gain
16
28
14
24
12
20
Output Power
16
10
20
Output Power (dBm)
0
-4
0
4
8
12
Input Power (dBm)
16
20
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Application Circuit: 1930 – 1960 MHz (FP31QF-PCB1900)
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
Frequency
S21 – Gain
S11 – Input Return Loss
S22 – Output Return Loss
Output P1dB
Output IP3
(+18 dBm / tone, 1 MHz spacing)
Noise Figure
IS-95 Channel Power
@ -45 dBc ACPR
MHz
dB
dB
dB
dBm
1930
14
-17
-11
+33.5
dBm
1960
13.8
-21
-11
+33.8
1990
13.8
-27
-13
+33.8
+46.8
dB
4.3
dBm
4.5
4.4
+27.3
Bill of Materials
C2
Ref. Desig.
C1, C4, C8, C10
C2
C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
C3
•
•
•
•
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 Ω.
Value
22 pF
2.2 pF
2.0 pF
0.018 µF
1000 pF
0.1 µF
12 nH
4.7 nH
5.1 Ω
51 Ω
FP31QF
Part style
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Wirewound chip inductor
Multilayer chip inductor
Chip resistor
Chip resistor
WJ 2W HFET
Do Not Place
Size
0603
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
The C2 and C3 placements are at silk screen markers, “B” and “3”, respectively.
The via hole spacing along the main microstrip line is .040”.
The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
CA P
CA P
CAP
ID=C6
ID =C7
ID=C8
C=2 2 pF C =100 0 pF C=1.8e 4 pF
-Vgg
Vds=9V @ 450 mA
CAP
ID=C12
C=1e 5 pF
RES
ID=R2
R=51 Ohm
CAP
ID=C11
C=1.8e 4 pF
CAP
ID=C5
C=DNP pF
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=2 2 pF
IND
ID=L3
L =4.7 nH
TLINP
ID =TL1
Z0 =50 Ohm
L =190 mil
Eeff =3 .46
Loss =0
F0 =0 MHz
IND
ID=L1
L =1 2 nH
CAP
ID =C10
C =2 2 pF
IND
ID=L2
L =1 2 nH
2
CAP
ID=C4
C=2 2 pF
P ORT
P =2
Z=50 Ohm
1
CA P
ID=C2
C=2.2 pF
RES
ID=R1
R=5 Ohm
SUB CKT
ID=Q1
NET="FP31QF"
TL INP
ID=TL2
Z0 =50 Ohm
L =200 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
CAP
ID=C3
C=2 pF
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
FP31QF-PCB1900 Application Circuit Performance Plots
S11 vs. Frequency
S21 vs. Frequency
-10
-15
-20
-5
14
13
-25
12
-30
1930
11
1930
-40C
1950
1970
1990
1950
freq = 1960 MHz
3
2
1
+85c
1970
4
-40c
1950
Frequency (MHz)
OIP3 vs. Temperature
IMD products (dBm)
48
46
44
freq = 1960, 1961 MHz
+18 dBm / tone
-40 C
1970
22
1990
-40
-60
IMD_Low
-80
85
8
12
16
20
Output Power (dBm)
24
Output Power / Gain vs. Input Power
Output Power / Gain vs. Input Power
frequency = 1960 MHz, Temp = -40° C
frequency = 1960 MHz, Temp = +25° C
14
12
28
10
24
8
20
Gain (dB)
32
Gain
Output Power (dBm)
14
16
16
10
14
18
Input Power (dBm)
22
26
28
29
40
8
16
32
14
20
Output Power
16
6
6
10
14
18
Input Power (dBm)
22
4
36
24
10
2
27
45
28
28
Output Power
6
26
8
12
16
20
Output Power (dBm)
24
28
Output Power / Gain vs. Input Power
Gain
12
25
30
4
36
24
35
IMD_High
Temperature (°C)
6
23
fundamental frequency = 1960, 1961 MHz; Temp = +25° C
50
Gain (dB)
60
+85 C
OIP3 vs. Output Power
fundamental frequency = 1960, 1961 MHz; Temp = +25° C
Output Power (dBm)
35
+25 C
Output Channel Power (dBm)
-100
16
-65
+85c
IMD products vs. Output Power
-20
10
-55
Frequency (MHz)
50
-15
-45
-75
0
1930
1990
+25c
OIP3 (dBm)
1950
+25c
ACPR (dBc)
NF (dB)
30
1990
IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW
-35
5
40
-40
1970
Frequency (MHz)
6
26
1930
1950
+85C
ACPR vs. Channel Power
-40c
OIP3 (dBm)
1990
+25C
Frequency (MHz)
28
Gain (dB)
-40C
-30
1930
Noise Figure vs. Frequency
32
2
-20
-25
+85C
1970
-15
Frequency (MHz)
34
42
+25C
-10
P1dB vs. Frequency
36
P1dB (dBm)
15
+85C
S21 (dB)
S11 (dB)
+25C
0
S22 (dB)
-40C
-5
S22 vs. Frequency
16
frequency = 1960 MHz, Temp = +85° C
36
32
12
28
Gain
24
10
8
20
Output Power
16
6
26
Output Power (dBm)
0
2
6
10
14
18
Input Power (dBm)
22
26
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Application Circuit: 2110 – 2170 MHz (FP31QF-PCB2140)
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
Frequency
S21 – Gain
S11 – Input Return Loss
S22 – Output Return Loss
Output P1dB
Output IP3
(+18 dBm / tone, 1 MHz spacing)
Noise Figure
IS-95 Channel Power
@ -45 dBc ACPR
MHz
dB
dB
dB
dBm
2110
13.2
-17
-14
+33.6
dBm
2140
13.3
-19
-24
+33.2
2170
13.1
-16
-18
+33.3
+46.6
dB
4.7
4.6
dBm
4.9
+25
Bill of Materials
C2
Ref. Desig.
C1, C4, C8, C10
C2, C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
C3
•
•
•
•
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 Ω.
Value
22 pF
2 pF
0.018 µF
1000 pF
0.1 µF
12 nH
4.7 nH
5.1 Ω
51 Ω
FP31QF
Part style
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Wirewound chip inductor
Multilayer chip inductor
Chip resistor
Chip resistor
WJ 2W HFET
Do Not Place
Size
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
The C2 and C3 placements are at silk screen markers, “A” and “2.5”, respectively.
The via hole spacing along the main microstrip line is .040”.
The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
CA P
CA P
CAP
ID=C6
ID =C7
ID=C8
C=2 2 pF C =100 0 pF C=1.8e 4 pF
-Vgg
Vds=9V @ 450 mA
CAP
ID=C12
C=1e 5 pF
RES
ID=R2
R=51 Ohm
CAP
ID=C11
C=1.8e 4 pF
CAP
ID=C5
C=DNP pF
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=2 2 pF
IND
ID=L3
L =4.7 nH
TLINP
ID =TL1
Z0 =50 Ohm
L =150 mil
Eeff =3 .46
Loss =0
F0 =0 MHz
IND
ID=L1
L =1 2 nH
CAP
ID =C10
C =2 2 pF
IND
ID=L2
L =1 2 nH
2
CAP
ID=C4
C=2 2 pF
P ORT
P =2
Z=50 Ohm
1
CA P
ID=C2
C=2 pF
RES
ID=R1
R=5 Ohm
SUB CKT
ID=Q1
NET="FP31QF"
TL INP
ID=TL2
Z0 =50 Ohm
L =180 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
CAP
ID=C3
C=2 pF
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
FP31QF-PCB2140 Application Circuit Performance Plots
S11 vs. Frequency
S21 vs. Frequency
14
-5
+85c
-10
S21 (dB)
-15
-20
13
12
-25
11
-30
2110
10
2110
-40c
2150
2170
2130
5
32
30
28
+25C
2150
IMD products (dBm)
2
freq = 2140, 2141 MHz
+18 dBm / tone
35
60
-40 C
2130
2150
22
2170
50
6
9
12
15
Output Power (dBm)
18
frequency = 2140 MHz, Temp = +25° C
28
8
24
20
Output Power
4
16
6
10
14
18
Input Power (dBm)
22
26
Gain (dB)
10
45
40
21
36
14
32
12
10
28
8
24
6
3
20
Output Power
18
21
frequency = 2140 MHz, Temp = +85° C
36
32
Gain
10
28
24
8
20
6
16
10
14
18
Input Power (dBm)
9
12
15
Output Power (dBm)
Output Power
4
6
6
Output Power / Gain vs. Input Power
Gain
2
27
30
3
12
26
35
IMD_High
32
25
OIP3 vs. Output Power
Output Power / Gain vs. Input Power
Gain
24
fundamental frequency = 2140, 2141 MHz; Temp = +25° C
frequency = 2140 MHz, Temp = -40° C
6
23
IMD products vs. Output Power
-80
14
+85 C
fundamental frequency = 2140, 2141 MHz; Temp = +25° C
IMD_Low
36
+25 C
Output Channel Power (dBm)
-60
85
Output Power (dBm)
Gain (dB)
+85C
Output Power / Gain vs. Input Power
14
-50
-60
Temperature (°C)
2
+25C
-100
10
-45
-55
-40C
Gain (dB)
OIP3 (dBm)
44
12
ACPR vs. Channel Power
3
-40
46
2170
3GPP W-CDMA, Test Model 1 + 64 DPCH, ±5 MHz offset
Frequency (MHz)
48
2150
Frequency (MHz)
4
OIP3 vs. Temperature
-15
2130
+85c
freq = 2140 MHz
0
2110
2170
+25c
-40
1
+85C
50
40
-40
2170
-35
Frequency (MHz)
42
-40c
-30
2110
ACPR (dBc)
34
2130
-20
Noise Figure vs. Frequency
6
NF (dB)
P1dB (dBm)
P1dB vs. Frequency
36
26
2110
-15
Frequency (MHz)
Frequency (MHz)
-40C
2150
-10
-25
+85c
OIP3 (dBm)
2130
+25c
Output Power (dBm)
S11 (dB)
+25c
0
S22 (dB)
-40c
-5
S22 vs. Frequency
15
Output Power (dBm)
0
22
16
4
26
2
6
10
14
18
Input Power (dBm)
22
26
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Reference Design: 2400 – 2500 MHz
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
(+18 dBm / tone, 1 MHz spacing)
Noise Figure
MHz
dB
dB
dB
dBm
2400
2500
12.1
12.0
-13
-16
-13
-17
+33.5
dBm
+46.8
-10
dB
4.6
-15
10
5
0
(dB)
Frequency
S21 – Gain
S11 – Input Return Loss
S22 – Output Return Loss
Output P1dB
Output IP3
Measured S-Parameters
15
DB(|S[1,1]|)
DB(|S[2,1]|)
DB(|S[2,2]|)
-5
-20
The 2.4 – 2.5 GHz Reference Circuit is shown for design purposes only. An
evaluation board is not readily available for this application. The reader can
obtain any FP31QF evaluation board and modify it with the circuit shown to
achieve the performance shown in this reference design.
-25
2.3
2.35
2.4
2.45
2.5
Frequency (GHz)
2.55
2.6
Bill of Materials
C2
Ref. Desig.
C1, C4, C8, C10
C2, C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
C3
•
•
•
•
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 Ω.
Value
22 pF
1.5 pF
0.018 µF
1000 pF
0.1 µF
12 nH
3.3 nH
5.1 Ω
50 Ω
FP31QF
Part style
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Wirewound chip inductor
Multilayer chip inductor
Chip resistor
Chip resistor
WJ 2W HFET
Do Not Place
Size
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
The C2 and C3 placements are at silk screen markers, “A” and “2”, respectively.
The via hole spacing along the main microstrip line is .040”.
The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
CA P
CA P
CAP
ID=C8
ID=C6
ID =C7
C=2 2 pF C =100 0 pF C=1.8e 4 pF
-Vgg
Vds=9V @ 450 mA
CAP
ID=C12
C=1e 5 pF
RES
ID=R2
R=51 Ohm
CAP
ID=C11
C=1.8e 4 pF
CAP
ID=C5
C=DNP pF
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=2 2 pF
IND
ID=L3
L =3.3 nH
TLINP
ID =TL1
Z0 =50 Ohm
L =150 mil
Eeff =3 .46
Loss =0
F0 =0 MHz
CAP
ID =C10
C =2 2 pF
IND
ID=L1
L =1 2 nH
IND
ID=L2
L =1 2 nH
2
CAP
ID=C4
C=2 2 pF
P ORT
P =2
Z=50 Ohm
1
CAP
ID=C2
C=1.5 pF
TL INP
ID=TL2
Z0 =50 Ohm
L =180 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
RES
ID=R1
R=5.1 Ohm
SUB CKT
ID=Q1
NET="FP31QF"
CAP
ID=C3
C=1.5 pF
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Reference Design: 3500 MHz
The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +9 V, Ids = 450 mA, 25°C
(+18 dBm / tone, 1 MHz spacing)
MHz
dB
dB
dB
dBm
3500
11.9
-16
-8.8
+33.5
dBm
+45
10
5
0
(dB)
Frequency
S21 – Gain
S11 – Input Return Loss
S22 – Output Return Loss
Output P1dB
Output IP3
Measured S-Parameters
15
DB(|S[1,1]|)
DB(|S[2,1]|)
DB(|S[2,2]|)
-5
-10
-15
The 3.5 GHz Reference Circuit is shown for design purposes only. An
evaluation board is not readily available for this application. The reader can
obtain any FP31QF evaluation board and modify it with the circuit shown to
achieve the performance shown in this reference design.
-20
-25
3.3
3.35
3.4
3.45
3.5
3.55
Frequency (GHz)
3.6
3.65
3.7
Bill of Materials
Ref. Desig.
C1, C4, C8, C10
C2
C3
C6, C11
C7
C12
L1, L2
L3
R1
R2
Q1
C5
C3
C2
Value
22 pF
0.9 pF
1.0 pF
0.018 µF
1000 pF
0.1 µF
6.8 nH
3.3 nH
2.2 Ω
50 Ω
FP31QF
Part style
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Wirewound chip inductor
Multilayer chip inductor
Chip resistor
Chip resistor
WJ 2W HFET
Do Not Place
Size
0603
0603
0603
0805
0603
1206
0805
0603
0603
0603
QFN 6x6
• Both the C2 and C3 placements are between the first and second via locations
along the main microstrip line leading from the FP31QF device. Further
descriptions are shown in the diagram on the left.
• The via hole spacing along the main microstrip line is .040”.
• The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
• The transmission line lengths shown in the schematic are from the FP31QF
device edge to the component edge.
Circuit Board Material: .014” FR-4 (εr = 4.6),
4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper
The main microstrip line has a line impedance of 50 Ω.
CA P
CA P
CAP
ID =C7
ID=C6
ID=C8
C=2 2 pF C =100 0 pF C=1.8e 4 pF
-Vgg
Vds=9V @ 450 mA
CAP
ID=C12
C=1e 5 pF
RES
ID=R2
R=51 Ohm
CAP
ID=C11
C=1.8e 4 pF
CAP
ID=C5
C=DNP pF
P ORT
P =1
Z=50 Ohm
CAP
ID=C1
C=2 2 pF
TL INP
ID=TL1
Z0 =50 O hm
L =30 mil
Eeff=3.46
Loss=0
F0 =0 MHz
IND
ID=L3
L =3.3 nH
CAP
ID =C10
C =2 2 pF
IND
ID=L1
L =6.8 nH
IND
ID=L2
L =6.8 nH
2
CAP
ID=C4
C=2 2 pF
P ORT
P =2
Z=50 Ohm
1
RES
I D=R1
R =2.2 O hm
CAP
ID=C2
C=0.9 pF
SUB CKT
ID=Q1
NET="FP31QF"
TL INP
ID=TL2
Z0 =50 Ohm
L =65 mil
Eeff=3 .46
Loss=0
F0 =0 MHz
CAP
ID=C3
C=1 pF
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
Application Note: Constant-Current Active-Biasing
Special attention should be taken to properly bias the FP31QF.
Power supply sequencing is required to prevent the device from
operating at 100% Idss for a prolonged period of time and possibly
causing damage to the device. It is recommended that for the safest
operation, the negative supply be “first on and last off.” With a
negative gate voltage present, the drain voltage can then be applied
to the device. The gate voltage can then be adjusted to have the
device be used at the proper quiescent bias condition.
An optional active-bias current mirror is recommended for use with
the application circuits shown this datasheet. Generally in a
laboratory environment, the gate voltage is adjusted until the drain
draws the recommended operating current. The gate voltage
required can vary slightly from device to device because of device
pinchoff variation, while also varying slightly over temperature.
+Vdd
R1
R2
U1
5
2
3
6
R4
1 kΩ
R3
R5
RF OUT
RF IN
The active-bias circuit, shown on the right, uses dual PNP transistors
to provide a constant drain current into the FP31QF, while also
eliminating the effects of pinchoff variation. This configuration is
best suited for applications where the intended output power level of
the amplifier is backed off at least 6 dB away from its compression
point. With the implementation of the circuit, lower P1dB values
may be measured for a Class-AB amplifier, where the device will
attempt to source more drain current while the circuit tries to provide
a constant drain current. The circuit should be connected directly in
line with where the voltage supplies would be normally connected
with the amplifier circuit, as shown the diagram. Any required
matching circuitry remains the same, although it is not shown in the
diagram. This recommended active-bias constant-current circuit
adds 7 components to the parts count for implementation, but should
cost only an extra $0.144 to realize ($0.10 for U1, $0.0029 for R1,
R3, R4, R5, $0.024 for R2, and $0.0085 for C1).
Temperature compensation is achieved by tracking the voltage
variation with the temperature of the emitter-to-base junction of the
two PNP transistors. As a 1st order approximation, this is achieved
by using matched transistors with approximately the same Ibe
current. Thus the transistor emitter voltage adjusts the HFET gate
voltage so that the device draws a constant current, regardless of the
temperature. A Rohm dual transistor - UMT1N - is recommended
for cost, minimal board space requirements, and to minimize the
variation between the two transistors. Minimizing the variability
between the base-to-emitter junctions allow more accuracy in setting
the current draw. More details can be found in a separate application
note “Active-bias Constant-current Source Recommended for
HFETs” found on the WJ website.
C1
.01 µF
4 Rohm UMT1N 1
M.N.
-Vgg
DUT
M.N.
HFET Application Circuit
Parameter
Pos Supply, Vdd
Neg Supply, Vgg
Vds
Ids
R1
R2*
R3
R4
R5
FP31QF
+9 V
-5 V
+8.75. V
450 mA
62 Ω
0.56 Ω
2 kΩ
1 kΩ
1 kΩ
*R2 should be of size 1206 to dissipate 0.113 Watts.
This should be of 1% tolerance. Two 1.1 Ω resistors in
parallel of size 0805 can also be used.
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
FP31QF Mechanical Information
This package may contain lead-bearing materials. The plating material on the pins is SnPb.
Product Marking
Outline Drawing
The component will be lasermarked with a
“FP31QF”
product
label
with
an
alphanumeric lot code on the top surface of
the package.
Tape and reel specifications for this part will
be located on the website in the “Application
Notes” section.
ESD / MSL Information
Mounting Configuration / Land Pattern
ESD Rating:
Value:
Test:
Standard:
Class 1C
Passes 1000V to <2000V
Human Body Model (HBM)
JEDEC Standard JESD22-A114
ESD Rating:
Value:
Test:
Standard:
Class IV
Passes 1000V
Charged Device Model (CDM)
JEDEC Standard JESD22-C101
MSL Rating: Level 1 at +250°C convection reflow
Standard:
JEDEC Standard J-STD-020
Functional Pin Layout
Pin
3
19
FUNCTION
Gate / RF Input
Drain / RF Output
The backside paddle is the Source and should be
grounded for thermal and electrical purposes. All
other pins should be grounded on the PCB.
Thermal Specifications
Parameter
Rating
Operating Case Temperature
Thermal Resistance, Rth (1)
Junction Temperature, Tjc (2)
-40 to +85°C
17.5° C/W
156° C
1. The thermal resistance is referenced from the hottest part
of the junction to the ground copper on the backside.
2. This corresponds to the typical drain biasing condition
of +9V, 450 mA at an 85°C case temperature. A
minimum MTTF of 1 million hours is achieved for
junction temperatures below 160 °C.
MTTF vs. GND Tab Temperature
100
10
1
0
60
70
80
90
100
Tab Temperature (°C)
110
120
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004
FP31QF
The Communications Edge TM
2-Watt HFET
Product Information
FP31QF-F Mechanical Information
This package is lead-free/RoHS-compliant. It is compatible with both lead-free (maximum 260°C reflow temperature) and leaded (maximum
245°C reflow temperature) soldering processes. The plating material on the pins is annealed matte tin over copper.
Product Marking
Outline Drawing
The component will be lasermarked with a
“FP31QFF” product label with an
alphanumeric lot code on the top surface of
the package.
Tape and reel specifications for this part will
be located on the website in the “Application
Notes” section.
ESD / MSL Information
Mounting Configuration / Land Pattern
ESD Rating:
Value:
Test:
Standard:
Class 1C
Passes 1000V to <2000V
Human Body Model (HBM)
JEDEC Standard JESD22-A114
ESD Rating:
Value:
Test:
Standard:
Class IV
Passes 1000V
Charged Device Model (CDM)
JEDEC Standard JESD22-C101
MSL Rating: Level 2 at +260°C convection reflow
Standard:
JEDEC Standard J-STD-020
Functional Pin Layout
Pin
3
19
FUNCTION
Gate / RF Input
Drain / RF Output
The backside paddle is the Source and should be
grounded for thermal and electrical purposes. All
other pins should be grounded on the PCB.
Thermal Specifications
Parameter
Rating
Operating Case Temperature
Thermal Resistance, Rth (1)
Junction Temperature, Tjc (2)
-40 to +85°C
17.5° C/W
156° C
1. The thermal resistance is referenced from the hottest part
of the junction to the ground copper on the backside.
2. This corresponds to the typical drain biasing condition
of +9V, 450 mA at an 85°C case temperature. A
minimum MTTF of 1 million hours is achieved for
junction temperatures below 160 °C.
MTTF vs. GND Tab Temperature
100
10
1
0
60
70
80
90
100
Tab Temperature (°C)
110
120
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
November 2004