AVAGO HCMS-2904 High performance cmos 5 x 7 alphanumeric display Datasheet

HCMS-29xx Series
High Performance CMOS 5 x 7 Alphanumeric Displays
Data Sheet
Description
Features
The HCMS-29xx series are high performance, easy
to use dot matrix displays driven by on-board CMOS ICs.
Each display can be directly inter­faced with a microproces­
sor, thus eliminat­ing the need for cum­ber­some interface
compo­nents. The serial IC interface allows higher char­ac­
ter count information displays with a minimum of data
lines. A variety of colors, font heights, and character
counts gives designers a wide range of prod­uct choices
for their specific appli­cations and the easy to read 5 x 7
pixel format allows the display of uppercase, lower case,
Kata­kana, and custom user-defined characters. These dis­
plays are stackable in the x- and y- directions, making
them ideal for high character count displays.
• Easy to use
• Interfaces directly with microprocessors
• 0.15” character height in 4, 8, and 16 (2x8) character
packages
• 0.20” character height in 4 and 8 character packages
• Rugged X- and Y-stackable package
• Serial input
• Convenient brightness controls
• Wave solderable
• Offered in five colors
• Low power CMOS technology
• TTL compatible
Applications
•
•
•
•
•
•
•
•
Telecommunications equipment
Portable data entry devices
Computer peripherals
Medical equipment
Test equipment
Business machines
Avionics
Industrial controls
Device Selection Guide
Description
1 x 4 0.15” Character
1 x 8 0.15” Character
2 x 8 0.15” Character
1 x 4 0.20” Character
1 x 8 0.20” Character
AlGaAs
HCMS2905
2915
2925
2965
2975
HER
HCMS2902
2912
2922
2962
2972
Orange
HCMS2904
2914
2924
2964
2974
Yellow
HCMS2901
2911
2921
2961
2971
Green
HCMS2903
2913
2923
2963
2973
Package
Drawing
A
B
C
D
E
ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID STATIC DISCHARGE.
HCMS-290x
17.78 (0.700) MAX.
PIN FUNCTION
ASSIGNMENT TABLE
PIN # FUNCTION
4.45 (0.175) TYP.
1
2
3
4
5
6
7
8
9
10
11
12
2.22 (0.087) SYM.
12
3.71 (0.146) TYP.
1
2
3
4
10.16 (0.400) MAX.
1
DATA OUT
OSC
V LED
DATA IN
RS
CLK
CE
BLANK
GND
SEL
V LOGIC
RESET
2.11 (0.083) TYP.
DATE CODE
LIGHT INTENSITY CATEGORY
COLOR BIN
COUNTRY OF ORIGIN
PIN # 1 IDENTIFIER
PART NUMBER
5.08
(0.200)
0.25
(0.010)
HCMS-290X X Z
YYWW COO
4.32
TYP.
(0.170)
0.51 (0.020)
PIN # 1
2.54
SYM.
(0.100)
1.27
(0.050) SYM.
2.54 ± 0.13 TYP.
(0.100 ± 0.005)
(NON ACCUM.)
0.51 ± 0.13 TYP.
(0.020 ± 0.005)
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
HCMS-291x
35.56 (1.400) MAX.
2.22 (0.087) SYM.
4.45
(0.175) TYP.
3.71
TYP.
(0.146)
PIN FUNCTION
ASSIGNMENT TABLE
26
0
1
2
3
4
5
6
7
PIN # FUNCTION
10.16 (0.400) MAX.
3
2.11 (0.083) TYP.
DATE CODE (YEAR, WEEK)
PIN # 1 IDENTIFIER
INTENSITY CATEGORY
COLOR BIN
PART NUMBER
COUNTRY OF ORIGIN
0.51
(0.020)
HCMS-291X
YYWW
X
Z
COO
0.25
(0.010)
5.08 (0.200)
4.32
(0.170)TYP.
2.54
SYM.
(0.100)
0.51 ± 0.13
TYP.
(0.020 ± 0.005)
2.54 ± 0.13
TYP.
(0.100 ± 0.005)
(NON ACCUM.)
1.27
SYM.
(0.050)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
7.62
(0.300)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
V LOGIC
NO PIN
RESET
OSC
DATA OUT
HCMS-292x
PIN FUNCTION ASSIGNMENT TABLE
35.56 (1.400) MAX.
2.22 (0.088) SYM.
4.45 (0.175) MAX.
26B
ROW B
0
1
2
3
4
5
6
7
3B
9.65 (0.380)
4.83
(0.190)
19.81 (0.780) MAX.
26A
8
ROW A
9
10
11
12
13
14
15
3.71 (0.146) TYP.
3A
2.11 (0.083) TYP.
DATE CODE (YEAR, WEEK)
PIN # 1 IDENTIFIER
INTENSITY CATEGORY
COLOR BIN
PART NUMBER
PIN # FUNCTION
PIN # FUNCTION
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
25A
26A
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
V LOGIC
NO PIN
RESET
OSC
DATA OUT
COUNTRY OF ORIGIN
HCMS-292X
YYWW
0.51
(0.020)
X
Z
COO
0.25
(0.010)
5.08 (0.200)
2.54
(0.100) SYM.
0.51 ± 0.13
TYP.
(0.020 ± 0.005)
1.27
(0.050)
2.03
(0.080)
2.54 ± 0.13
TYP.
(0.100 ± 0.005)
(NON ACCUM.)
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
HCMS-296x
PIN FUNCTION
ASSIGNMENT TABLE
PIN # FUNCTION
21.46 (0.845) MAX.
1
2
3
4
5
6
7
8
9
10
11
12
2.67 (0.105) SYM.
2.54 (0.100) TYP.
4.57
(0.180)TYP.
0
1
2
3
11.43 (0.450) MAX.
DATA OUT
OSC
V LED
DATA IN
RS
CLK
CE
BLANK
GND
SEL
V LOGIC
RESET
5.36 (0.211) TYP.
PIN # 1 IDENTIFIER
DATE CODE (YEAR, WEEK)
INTENSITY CATEGORY
COLOR BIN
COUNTRY OF ORIGIN
PART NUMBER
HCMS-296X
YYWW
X Z
0.25
(0.010)
5.31
(0.209)
COO
0.51 ± 0.13
TYP.
(0.020 ± 0.005)
2.54 ± 0.13 TYP.
(0.100 ± 0.005)
1.83
(0.072) SYM.
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
3.71
TYP.
(0.146)
0.50
(0.020)
4.28
(0.169) SYM.
7.62
(0.300)
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
V LOGIC
NO PIN
RESET
OSC
DATA OUT
HCMS-297x
42.93 (1.690) MAX.
2.67 (0.105) SYM.
5.36 (0.211) TYP.
PIN FUNCTION
ASSIGNMENT TABLE
26
4.57
(0.180) TYP.
1
2
3
4
5
6
7
8
PIN # FUNCTION
11.43 (0.450) MAX.
3
2.54 (0.100) TYP.
PIN # 1 IDENTIFIER
DATE CODE (YEAR, WEEK)
INTENSITY CATEGORY
COLOR BIN
COUNTRY OF ORIGIN
PART NUMBER
0.51
(0.020)
HCMS-297X
YYWW
0.25
(0.010)
5.31
(0.209)
X Z
COO
3.71
TYP.
(0.146)
6.22
SYM.
(0.245)
0.51 ± 0.13
(0.020 ± 0.005) TYP.
1.90
(0.075) SYM.
2.54 ± 0.13 TYP.
(0.100 ± 0.005)
(NON ACCUM.)
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
Absolute Maximum Ratings
Logic Supply Voltage, VLOGIC to GNDLOGIC ‑0.3 V to 7.0 V
LED Supply Voltage, VLED to GNDLED ‑0.3 V to 5.5 V
Input Voltage, Any Pin to GND ‑0.3 V to VLOGIC +0.3 V
Free Air Operating Temperature Range TA[1] ‑40°C to +85°C
Relative Humidity (noncondensing)
85%
Storage Temperature, TS ‑55°C to 100°C
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping
260°C for 5 secs
Wave Soldering 250°C for 3 secs
ESD Protection @ 1.5 kΩ, 100 pF (each pin) Class 1, 0-1999 V
[2]
TOTAL Package Power Dissipation at TA = 25°C
4 Character 1.2 W
8 Character 2.4 W
16 Character 4.8 W
Note:
1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations.
Recommended Operating Conditions Over Temperature Range (-40°C to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Units
Logic Supply Voltage
VLOGIC
3.0
5.0
5.5
V
LED Supply Voltage
VLED
4.0
5.0
5.5
V
GNDLED to GNDLOGIC
–
-0.3
0
+0.3
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
V LOGIC
NO PIN
RESET
OSC
DATA OUT
Electrical Characteristics Over Operating Temperature Range (-40°C to +85°C)
TA = 25°C
-40°C < TA < 85°C
VLOGIC = 5.0 V
3.0 V < VLOGIC < 5.5 V
Parameter
Symbol
Typ.
Max.
Min.
Max.
Units
Input Leakage Current
II
µA
HCMS-290X/296X (4 char)
+7.5
-2.5
+50
HCMS-291X/297X (8 char)
+15
-5.0
+100
HCMS-292X (16 char)
+15
-5.0
+100
ILOGIC OPERATING
ILOGIC(OPT)
mA
HCMS-290X/296X (4 char)
0.4
2.5
5
HCMS-291X/297X (8 char)
0.8
5
10
HCMS-292X (16 char)
0.8
5
10
ILOGIC SLEEP[1]
ILOGIC(SLP)
µA
HCMS-290X/296X (4 char)
5
15
25
HCMS-291X/297X (8 char)
10
30
50
HCMS-292X (16 char)
10
30
50
ILED BLANK
ILED(BL)
mA
HMCS-290X/296X (4 char)
2.0
4
4.0
HCMS-291X/297X (8 char)
4.0
8
8
HCMS-292X (16 char)
4.0
8
8
[1]
ILED SLEEP
ILED(SLP)
µA
HCMS-290X/296X (4 char)
1
3
50
HCMS 291X/297X (8 char)
2
6
100
HCMS-292X (16 char)
2
6
100
Peak Pixel Current[2]
IPIXEL
HCMS-29X5 (AlGaAs)
15.4
17.1
18.7
mA
HCMS-29XX (Other Colors)
14.0
15.9
17.1
mA
pixel
HIGH Level Input Voltage
Vih
2.0
V
0.8 VLOGIC
V
LOW Level Input Voltage
Vil
0.8
V
0.2 VLOGIC V
HIGH Level Output Voltage Voh
2.0
V
0.8 VLOGIC
V
LOW Level Output Voltage Vol
0.4
V
0.2 VLOGIC V
Thermal Resistance
RqJ-P
70
°C/W
Test Conditions
VIN = 0 V to VLOGIC
VIN = VLOGIC
VIN = VLOGIC
BL = 0 V
VLED = 5.5 V
All pixels ON,
Average value per
4.5 V < VLOGIC < 5.5 V
3.0 V < VLOGIC < 4.5 V
4.5 V < VLOGIC < 5.5 V
3.0 V < VLOGIC < 4.5 V
VLOGIC = 4.5 V,
Ioh = -40 µA
3.0 V < VLOGIC < 4.5 V
VLOGIC = 5.5 V,
Iol = 1.6 mA[3]
3.0 V < VLOGIC < 4.5 V
IC junction to pin
Notes:
1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off.
2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value.
3. For the Oscillator Output, Iol = 40 µA.
Optical Characteristics at 25°C[1]
VLED = 5.0 V, 50% Peak Current, 100% Pulse Width
Luminous Intensity per LED[2]
Character Average (µcd)
Display Color
Part Number
Min.
Typ.
AlGaAs Red HCMS-29X5
95
230
High Efficiency Red
HCMS-29X2
29
64
Orange
HCMS-29X4
29
64
Yellow
HCMS-29X1
29
64
Green
HCMS-29X3
57
114
Peak
Wavelength
lPeak (nm)
Typ.
645
635
600
583
568
Dominant
Wavelength
ld[3] (nm)
Typ.
637
626
602
585
574
Notes:
1. Refers to the initial case temperature of the device immediately prior to measurement.
2. Measured with all LEDs illuminated.
3. Dominant wavelength, ld, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the perceived
LED color.
Electrical Description
Pin Function
RESET (RST)
Description
Sets Control Register bits to logic low. The Dot Register contents are unaffected by
the Reset pin. (logic low = reset; logic high = normal operation).
DATA IN (DIN)
Serial Data input for Dot or Control Register data. Data is entered on the rising edge
of the Clock input.
DATA OUT (DOUT )
Serial Data output for Dot or Control Register data. This pin is used for cascading
multiple displays.
CLOCK (CLK)
Clock input for writing Dot or Control Register data. When Chip Enable is logic low,
data is entered on the rising Clock edge.
REGISTER SELECT (RS)
Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data entry. The logic level of RS is latched on the falling edge of the
Chip Enable input.
CHIP ENABLE (CE)
This input must be a logic low to write data to the display. When CE returns to logic
high and CLK is logic low, data is latched to either the LED output drivers or a Control
Register.
OSCILLATOR SELECT (SEL)
Selects either an internal or external display oscillator source. (logic low = External
Display Oscillator; logic high = Internal Display Oscillator).
OSCILLATOR (OSC)
Output for the Internal Display Oscillator (SEL = logic high) or input for an External
Display Oscillator (SEL = logic low).
BLANK (BL)
Blanks the display when logic high. May be modulated for brightness control.
GNDLED
Ground for LED drivers.
GNDLOGIC
Ground for logic.
VLED Positive supply for LED drivers.
VLOGIC Positive supply for logic.
AC Timing Characteristics Over Temperature Range (-40°C to +85°C)
Timing
Diagram Ref.
Number
Description Symbol
4.5 V < VLOGIC <5.5 V
Min.
Max.
VLOGIC = 3 V
Min.
Max.
Units
1
Register Select Setup Time to Chip Enable
trss
10
10
ns
2
Register Select Hold Time to Chip Enable
trsh
10
10
ns
3
Rising Clock Edge to Falling
Chip Enable Edge
tclkce
20
20
ns
4
Chip Enable Setup Time to Rising Clock Edge
tces
35
55
ns
5
Chip Enable Hold Time to Rising Clock Edge
tceh
20
20
ns
6
Data Setup Time to Rising Clock Edge
tds
10
10
ns
7
Data Hold Time after Rising Clock Edge
tdh
10
10
ns
8
Rising Clock Edge to DOUT[1]
tdout
10
10
65
ns
9
Propagation Delay DIN to DOUT Simultaneous Mode for One IC[1,2]
tdoutp
18
30
ns
10
CE Falling Edge to DOUT Valid
tcedo
25
45
ns
11
Clock High Time
tclkh
80
100
ns
12
Clock Low Time
tclkl
80
100
ns
Reset Low Time
trstl
50
50
ns
Clock Frequency Fcyc
5
4
MHz
Internal Display Oscillator Frequency
Finosc
80
210
80
210
KHz
Internal Refresh Frequency
Frf
150
410
150
400
Hz
External Display Oscillator Frequency
Fexosc
40
Prescaler = 1
51.2
1000
51.2
1000
KHz
Prescaler = 8
410
8000
410
8000
KHz
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
Display Overview
Dot Register
The HCMS‑29xx series is a family of LED displays driven
by on‑board CMOS ICs. The LEDs are configured as 5 x 7
font characters and are driven in groups of 4 characters
per IC. Each IC consists of a 160‑bit shift register (the Dot
Register), two 7‑bit Control Words, and refresh circuitry.
The Dot Regis­ter contents are mapped on a one‑to‑one
basis to the display. Thus, an individual Dot Register bit
uniquely controls a single LED.
The Dot Register holds the pattern to be displayed by
the LEDs. Data is loaded into the Dot Register according
to the procedure shown in Table 1 and the Write Cycle
Timing Diagram.
8‑character displays have two ICs that are cascaded. The
Data Out line of the first IC is internally connected to
the Data In line of the second IC forming a 320‑bit Dot
Register. The dis­play’s other control and power lines are
connected directly to both ICs. In 16‑character displays,
each row functions as an independent 8‑character display
with its own 320‑bit Dot Register.
Reset
Reset initializes the Control Registers (sets all Control
Register bits to logic low) and places the display in the
sleep mode. The Reset pin should be con­nected to the
system power‑on reset circuit. The Dot Registers are not
cleared upon power‑on or by Reset. After power‑on, the
Dot Register contents are random; however, Reset will
put the display in sleep mode, there­by blanking the
LEDs. The Control Register and the Control Words are
cleared to all zeros by Reset.
To operate the display after being Reset, load the Dot
Register with logic lows. Then load Control Word 0 with
the desired bright­ness level and set the sleep mode bit
to logic high.
First RS is brought low, then CE is brought low. Next,
each successive rising CLK edge will shift in the data
at the DIN pin. Loading a logic high will turn the corresponding LED on; a logic low turns the LED off. When
all 160 bits have been loaded (or 320 bits in an 8‑digit
display), CE is brought to logic high.
When CLK is next brought to logic low, new data is
latched into the display dot drivers. Loading data into
the Dot Register takes place while the previous data is
displayed and eliminates the need to blank the display
while loading data.
Pixel Map
In a 4‑character display, the 160‑bits are arranged as 20
columns by 8 rows. This array can be conceptualized as
four 5 x 8 dot matrix character loca­tions, but only 7 of
the 8 rows have LEDs (see Figures 1 & 2). The bottom
row (row 0) is not used. Thus, latch location 0 is never
displayed. Column 0 controls the left‑most column. Data
from Dot Latch locations 0‑7 determine whether or not
pixels in Column 0 are turned‑on or turned‑off. Therefore,
the lower left pixel is turned‑on when a logic high is
stored in Dot Latch location 1. Characters are loaded
in serially, with the left‑most character being loaded
first and the right‑most character being loaded last. By
loading one character at a time and latching the data
before loading the next character, the figures will appear
to scroll from right to left.
Table 1. Register Truth Table
Function
CLK
CE
Select Dot Register
Not Rising
↑↓
Load Dot Register
DIN = HIGH LED = “ON”↑ ↓
L
DIN = LOW LED = “OFF”
Copy Data from Dot Register to Dot Latch
L
H
Select Control Register
Not Rising
↑↓
Load Control Register[1,3]↑ ↓
L
[2]
Latch Data to Control Word
L↑ ↓
RS
L
X
X
H
X
X
Notes:
1. BIT D0 of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.
2. Selection of Control Word 1 or Control Word 0 is set by D7 of the Control Shift Register. The unselected control word retains its previous value.
3. Control Word data is loaded Most Significant Bit (D7) first.
HCMS-29xx Write Cycle Diagram
RS
TRSS
TRSH
1
2
CE
TCLKCE
TCES
TCLKH
TCLKL
TCEH
3
4
11
12
5
CLK
D
TDS
TDH
6
7
NEW DATA LATCHED HERE
[1]
IN
TCEDO
TDOUT
10
8
D OUT (SERIAL)
TDOUTP
9
D OUT
(SIMULTANEOUS)
LED OUTPUTS,
CONTROL
REGISTERS
PREVIOUS DATA
NEW DATA
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
Control Register
Control Word 0
The Control Register allows software modification of the
IC’s opera­tion and consists of two independent 7‑bit
control words. Bit D7 in the shift register selects one of
the two 7‑bit control words. Control Word 0 performs
pulse width modula­tion brightness control, peak pixel
current brightness control, and sleep mode. Control Word
1 sets serial/simultaneous data out mode, and external
oscilla­tor prescaler. Each function is independent of
the others.
Loading the Control Register with D7 = Logic low selects Control Word 0 (see Table 2). Bits D0‑D3 adjust the
display brightness by pulse width modulating the LED
on-time, while Bits D4‑D5 adjust the display brightness
by changing the peak pixel current. Bit D6 selects normal
operation or sleep mode.
Control Register Data Loading
Data is loaded into the Control Register, MSB first, according to the proce­dure shown in Table 1 and the
Write Cycle Timing Diagram. First, RS is brought to logic
high and then CE is brought to logic low. Next, each
successive rising CLK edge will shift in the data on the
DIN pin. Finally, when 8 bits have been loaded, the CE
line is brought to logic high. When CLK goes to logic
low, new data is copied into the selected control word.
Loading data into the Control Register takes place while
the previous control word configures the display.
Sleep mode (Control Word 0, bit D6 = Low) turns off the
Internal Display Oscillator and the LED pixel drivers. This
mode is used when the IC needs to be powered up, but
does not need to be active. Current draw in sleep mode
is nearly zero. Data in the Dot Register and Control Words
are retained during sleep mode.
DATA OUT
RS (LATCHED)
DATA IN
H
L
L
CLK
H
H
SER/PAR
MODE
CHIP
ENABLE
DATA IN
REGISTER
SELECT
CONTROL
REGISTER
CLR
D Q
L
DI
40 BIT
S.R.
DO
DATA
OUT
DI
40 BIT
S.R.
DO
DI
40 BIT
S.R.
DO
V LED +
RST
÷8
OSC
H
L
H
ANODE
CURRENT SOURCES
PWM BRIGHTNESS
CONTROL
3:8 DECODER
PRESCALE
VALUE
CURRENT
REFERENCE
DOT
REGISTER
BIT # 159
CATHODE
FIELD DRIVERS
RESET
ROW 7
0xxxx
xxxxx
xxxxx
CHAR 1
CHAR 2
H
OSC
SELECT
CHAR 0
COLUMN 19
GND (LED)
BLANK
Figure 1.
PIXEL
DATA TO
NEXT
CHARACTER
ROW 1
x x x x x ROW 0 (NO LEDS)
L
OSCILLATOR
COLUMN 0
L
DATA FROM
PREVIOUS
CHARACTER
ROW 7
ROW 6
ROW 5
ROW 4
ROW 3
ROW 2
ROW 1
ROW 0
(NOT USED)
10
DOT
REGISTERS
AND
LATCHES
RS
(LATCHED)
REFRESH
CONTROL
Figure 2.
DI
40 BIT
S.R.
DO
CHAR 3
Control Word 1
Bits D2‑D6
Loading the Control Register with D7 = logic high selects
Control Word 1. This Control Word performs two functions: serial/simultaneous data out mode and external
oscillator prescale select (see Table 2).
These bits must always be pro­grammed to logic low.
Serial/Simultaneous Data Output D0
Bit D0 of control word 1 is used to switch the mode of
DOUT between serial and simul­ta­neous data entry during
Control Register writes. The default mode (logic low) is
the serial DOUT mode. In serial mode, DOUT is connected
to the last bit (D7) of the Control Shift Register.
Storing a logic high to bit D0 changes DOUT to simultaneous mode which affects the Control Register only. In
simul­taneous mode, DOUT is logically con­nected to DIN.
This arrange­ment allows multiple ICs to have their Control
Registers written to simul­taneously. For example, for N
ICs in the serial mode, N * 8 clock pulses are needed to
load the same data in all Control Registers. In the simultaneous mode, N ICs only need 8 clock pulses to load
the same data in all Control Registers. The propaga­tion
delay from the first IC to the last is N * tDOUTP.
External Oscillator Prescaler Bit D1
Bit D1 of Control Word 1 is used to scale the frequency
of an external Display Oscillator. When this bit is logic
low, the external Display Oscil­la­tor directly sets the internal display clock rate. When this bit is a logic high, the
external oscilla­tor is divided by 8. This scaled frequency
then sets the internal display clock rate. It takes 512
cycles of the display clock (or 8 x 512 = 4096 cycles of
an external clock with the divide by 8 pre­scaler) to com­
pletely refresh the display once. Using the pre­scaler bit
allows the designer to use a higher external oscillator
fre­quency without extra circuitry.
This bit has no affect on the internal Display Oscillator
Frequency.
11
Cascaded ICs
Figure 3 shows how two ICs are connected within an
HCMS‑29XX display. The first IC controls the four left‑most
characters and the second IC controls the four right‑most
characters. The Dot Registers are connected in series to
form a 320‑bit dot shift register. The location of pixel 0
has not changed. However, Dot Shift Register bit 0 of IC2
becomes bit 160 of the 320‑bit dot shift register.
The Control Registers of the two ICs are independent
of each other. This means that to adjust the display
brightness the same control word must be entered
into both ICs, unless the Control Registers are set to
simultaneous mode.
Longer character string systems can be built by cascading multi­ple displays together. This is accomplished by
creating a five line bus. This bus consists of CE, RS, BL,
Reset, and CLK. The display pins are connected to the
corresponding bus line. Thus, all CE pins are connected to
the CE bus line. Similarly, bus lines for RS, BL, Reset, and
CLK are created. Then DIN is connected to the right‑most
display. DOUT from this display is connected to the next
display. The left‑most display receives its DIN from the
DOUT of the display to its right. DOUT from the left‑most
display is not used.
Each display may be set to use its internal oscillator, or
the displays may be synchronized by setting up one
display as the master and the others as slaves. The slaves
are set to receive their oscillator input from the master’s
oscillator output.
Table 2. Control Shift Register
CONTROL WORD 0
L
D6
D5
D4
Bit D7
Set Low
to Select
Control
Word 0
D3
D2
D1
D0
PWM Brightness
Control
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Peak Current
Brightness
Control
H L
L H
L L
H H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Typical Peak
Pixel Current
(mA)
4.0
6.4
9.3
12.8
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
On-Time
Oscillator
Cycles
Duty
Factor
(%)
Relative
Brightness
(%)
0
1
2
3
4
5
7
9
11
14
18
22
28
36
48
60
0
0.2
0.4
0.6
0.8
1.0
1.4
1.8
2.1
2.7
3.5
4.3
5.5
7.0
9.4
11.7
0
1.7
3.3
5.0
6.7
8.3
11.7
15
18
23
30
37
47
60
80
100
Relative Full
Scale Current
(Relative Brightness, %)
31
50
73 (Default at Power Up)
100
L − DISABLES INTERNAL OSCILLATOR-DISPLAY BLANK
H − NORMAL OPERATION
SLEEP MODE
CONTROL WORD 1
H
Bit D7
Set High
to Select
Control
Word 1
12
L
L
L
L
Reserved for Future
Use (Bits D2-D6
must be set Low)
L
D1
D0
Serial/Simultaneous Data Out
L − Dout holds contents of Bit D7
H − Dout is functionally tied to Din
External Display Oscillator Prescaler
L − Oscillator Freq 1
H − Oscillator Freq 8
CE
RS
BL
RESET
CLK
CE
CE
RS
RS
BL
BL
RESET
CLK
D
CLK
DOUT
OUT
DOUT
SEL
SEL
OSC
OSC
OSC
SEL
D
IN
Figure 3. Cascaded ICs.
13
RESET
IC1
BITS 0-159
CHARACTERS 0-3
D
IN
IC2
BITS 160-319
CHARACTERS 4-7
D
IN
Appendix A. Thermal Considerations
A typical value for RqJA is 100°C/W. This value is typical
for a display mounted in a socket and covered with a
plastic filter. The socket is soldered to a .062 in. thick PCB
with .020 inch wide, one ounce copper traces.
PD can be calculated as Equa­tion 2 below.
Figure 4 shows how to derate the power of one IC versus
ambient temperature. Opera­tion at high ambient temperatures may require the power per IC to be reduced.
The power con­sump­tion can be reduced by changing
either the N, IPIXEL, Osc cyc or VLED. Changing VLOGIC has
very little impact on the power consumption.
Rθ
1.2
1.1
PD MAX – MAXIMUM POWER
DISSIPATION PER IC – W
The display IC has a maximum junction temperature of
150°C. The IC junction temperature can be calculated
with Equation 1 below.
1.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25 30 35 40 45 50 55 60 65 70 75 80 85 90
TA – AMBIENT TEMPERATURE – °C
Figure 4.
Equation 1:
TJMAX = TA + PD * RqJA
Where:
TJMAX = maximum IC junction temperature
TA = ambient temperature surrounding the display
RqJA = thermal resistance from the IC junction to ambient
PD = power dissipated by the IC
Equation 2:
PD = (N * IPIXEL * Duty Factor * VLED) + ILOGIC * VLOGIC
Where:
PD = total power dissipation
N = number of pixels on (maximum 4 char * 5 * 7 = 140) IPIXEL = peak pixel current.
Duty Factor = 1/8 * Osccyc/64
Osc cyc = number of ON oscillator cycles per row
ILOGIC = IC logic current
VLOGIC = logic supply voltage
Equation 3:
IPEAK = M * 20 * IPIXEL
Where:
IPEAK = maximum instantaneous peak current for the display
M = number of ICs in the system
20 = maximum number of LEDs on per IC
IPIXEL = peak current for one LED
(see Variable Definitions above)
14
= 100°C/W
1.0
Appendix B. Electrical Considerations
Equation 4:
ILED(AVG) = N * IPIXEL * 1/8 * (oscillator cycles)/64
J-A
Current Calculations
Electrostatic Discharge
The peak and average display current requirements have
a significant impact on power supply selection. The
maximum peak current is calculated with Equation 3.
The inputs to the ICs are pro­tected against static discharge and input current latchup. How­ever, for best
results, standard CMOS handling precautions should
be used. Before use, the HCMS‑29XX should be stored
in antistatic tubes or in conductive material. During
assembly, a grounded conductive work area should be
used and assembly personnel should wear conduc­tive
wrist straps. Lab coats made of synthetic material should
be avoided since they are prone to static buildup. Input current latchup is caused when the CMOS inputs
are subjected to either a voltage below ground (VIN <
ground) or to a voltage higher than VLOGIC (VIN > VLOGIC)
and when a high current is forced into the input. To
prevent input current latchup and ESD damage, unused
inputs should be con­nected to either ground or VLOGIC.
Voltages should not be applied to the inputs until VLOGIC
has been applied to the display.
The average current required by the display can be
calculated with Equation 4.
The power supply has to be able to supply IPEAK transients and supply ILED(AVG) continuously. The range on
VLED allows noise on this supply without sig­nifi­cantly
changing the display brightness.
VLOGIC and VLED Considerations
The display uses two indepen­dent electrical systems.
One system is used to power the display’s logic and the
other to power the display’s LEDs. These two systems
keep the logic supply clean.
Separate electrical systems allow the voltage applied
to VLED and VLOGIC to be varied independently. Thus,
VLED can vary from 0 to 5.5 V without affecting either
the Dot or the Control Registers. VLED can be varied
between 4.0 to 5.5 V with­out any noticeable variation in
light output. However, oper­at­ing VLED below 4.0 V may
cause objectionable mismatch between the pixels and is
not recommended. Dimming the display by pulse width
modulat­ing VLED is also not recommended.
VLOGIC can vary from 3.0 to 5.5 V without affecting either
the displayed message or the display intensity. However,
operation below 4.5 V will change the timing and logic
levels and operation below 3 V may cause the Dot and
Control Registers to be altered.
The logic ground is internally connected to the LED
ground by a substrate diode. This diode becomes forward biased and conducts when the logic ground is 0.4
V greater than the LED ground. The LED ground and
the logic ground should be connected to a common
ground which can withstand the current introduced by
the switching LED drivers. When separate ground connections are used, the LED ground can vary from ‑0.3
V to +0.3 V with respect to the logic ground. Voltages
below ‑0.3 V can cause all the dots to be ON. Voltage
above +0.3 V can cause dimming and dot mismatch. The
LED ground for the LED drivers can be routed separately
from the logic ground until an appropri­ate ground
plane is available. On long interconnections between
the display and the host system, voltage drops on the
analog ground can be kept from affecting the display
logic levels by isolating the two grounds.
15
Appendix C. Oscillator
The oscillator provides the internal refresh circuitry with
a signal that is used to synchron­ize the columns and
rows. This ensures that the right data is in the dot drivers for that row. This signal can be supplied from either
an external source or the internal source.
A display refresh rate of 100 Hz or faster ensures
flicker‑free operation. Thus for an external oscillator
the frequency should be greater than or equal to 512
x 100 Hz = 51.2 kHz. Operation above 1 MHz without
the prescaler or 8 MHz with the prescaler may cause
noticeable pixel to pixel mismatch.
Appendix D. Refresh Circuitry
This display driver consists of 20 one‑of‑eight column
decoders and 20 constant current sources, 1 one‑of‑eight
row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the
circuit to refresh the LEDs. The refresh counters and oscillator are used to synchronize the columns and rows.
The 160 bits are organized as 20 columns by 8 rows. The
IC illuminates the display by sequentially turning ON each
of the 8 row‑drivers. To refresh the display once takes
512 oscillator cycles. Because there are eight row drivers, each row driver is selected for 64 (512/8) oscillator
cycles. Four cycles are used to briefly blank the display
before the following row is switched on. Thus, each row
is ON for 60 oscillator cycles out of a possible 64. This
corresponds to the maximum LED on time.
Appendix E. Display Brightness
Two ways have been shown to control the brightness
of this LED display: setting the peak current and setting
the duty factor. Both values are set in Control Word 0.
To compute the resulting display brightness when both
PWM and peak current control are used, simply multiply the two relative bright­ness factors. For example, if
Control Register 0 holds the word 1001101, the peak
current is 73% of full scale (BIT D5 = L, BIT D4 = L) and
the PWM is set to 60% duty factor (BIT D3 = H, BIT D2
= H, BIT D1 = L, BIT D0 = H). The resulting brightness is
44% (.73 x .60 = .44) of full scale.
The temperature of the display will also affect the LED
bright­ness as shown in Figure 5.
RELATIVE LUMINOUS INTENSITY
(NORMALIZED TO 1 AT 25°C)
3.0
2.6
HER/ORANGE
2.2
YELLOW
1.8
GREEN
1.4
AlGaAs
1.0
0.6
0.2
-55
-35
-15
5
Figure 5.
Appendix F. Reference Material
Application Note 1027: Soldering LED Components
Applica­tion Note 1015: Contrast Enhancement Techniques
for LED Displays
For product information and a complete list of distributors, please go to our website:
25
45
65
TA – AMBIENT TEMPERATURE – °C
www.avagotech.com
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3181EN
AV02-0699EN - September 18, 2007
85
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