Hynix HMS87C1302AD Cmos single-chip 8-bit microcontroller Datasheet

HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
HMS87C1304A / HMS87C1302A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS87C1304A and HMS87C1302A are an advanced CMOS 8-bit microcontroller with 4K/2K bytes of EPROM. The
HYUNDAI MicroElectronics HMS87C1304A and HMS87C1302A are powerful microcontroller which provides a highly
flexible and cost effective solution to many small applications such as controller for battery charger. The HMS87C1304A
and HMS87C1302A provide the following standard features: 4K/2K bytes of EPROM, 128bytes of RAM, 8-bit timer/
counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, power-on reset circuit, onchip oscillator and clock circuitry. In addition, the HMS87C1304A and HMS87C1302A supports power saving modes to
reduce power consumption.
Device name
EPROM Size
RAM Size
Operatind
Voltage
Package
HMS87C1304A
4K bytes
128bytes
2.0 ~ 5.5V
24 PDIP or SOP
HMS87C1302A
2K bytes
128bytes
2.0 ~ 5.5V
24 PDIP or SOP
• 4K/2K Bytes On-chip Program Memory
• 128 Bytes of On-chip Data RAM
(Included stack memory)
• Instruction Cycle Time:
- 250nS at 8MHz
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• 19 Programmable I/O pins
(LED direct driving can be source and sink)
• 2.0V to 5.5V Wide Operating Range
• One 8-bit A/D Converter
- 8 channels
• One 8-bit Basic Interval Timer
• Two 8-bit Timer / Counters
• One 10-bit High Speed PWM Outputs
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1.2 Features
ry
• Seven Interrupt sources
- External input: 2
- A/D Conversion: 1
- Timer: 4
• One Programmable Buzzer Driving port
- 500Hz ~ 130kHz
• Oscillator Type
- Crystal
- Ceramic Resonator
- RC-oscillation ( C can be omit )
• Power-On Reset
• Noise Immunity Circuit
- Power Fail Processor
• Power Down Mode
- STOP mode
- Wake-up Timer mode
• Watchdog timer
Jan. 2001
Preliminary
1
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
1.3 Development Tools
The HMS87C1304A and HMS87C1302A are supported
by a full-featured macro assembler, an in-circuit emulator
CHOICE-DrTM.
In Circuit Emulators
CHOICE-Dr.
Assembler
HME Macro Assembler
Single Writer : Dr. Writer
OTP Writer
4-Gang Writer : Dr.Gang
1.4 Ordering Information
ROM Size
4K bytes (OTP)
2K bytes (OTP)
Package Type
Ordering Device Code
24 PDIP
HMS87C1304A
24 SOP
HMS87C1304A D
24 PDIP
HMS87C1302A
24 SOP
HMS87C1302A D
Operating Temperature
-20 ~ +85°C
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in
P
2
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Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
2. BLOCK DIAGRAM
PSW
Accumulator
ALU
PC
Stack Pointer
Data
Memory
RESET
Program
Memory
System controller
System
Clock Controller
Timing generator
8-bit Basic
Interval
Timer
Data Table
In te rru p t C o n tro lle r
Xin
Xout
Clock Generator
Watch-dog
Timer
8-bit
A/D
Converter
RA
Power
Supply
P
Jan. 2001
High
Speed
PWM
in
VDD
VSS
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8-bit
Timer/
Counter
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RA0 / EC0
RA1 / AN1
RA2 / AN2
RA3 / AN3
RA4 / AN4
RA5 / AN5
RA6 / AN6
RA7 / AN7
RB
RB0 / AN0 / Avref
RB1 / BUZ
RB2 / INT0
RB3 / INT1
RB4 / CMP0 / PWM0
Preliminary
Instruction
Decoder
Buzzer
Driver
RC
RD
RC0
RC1
RD0
RD1
RD2
RD3
3
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
3. PIN ASSIGNMENT
24 PDIP
AN4 / RA4
1
24
RA3 / AN3
AN5 / RA5
2
23
RA2 / AN2
AN6 / RA6
3
22
RA1 / AN1
AN7 / RA7
4
21
RA0 / EC0
VDD
5
20
RC1
RD0
6
19
RC0
RD1
7
18
VSS
AN0 / AVref / RB0
8
17
RESET
BUZ / RB1
9
16
Xout
INT0 / RB2
10
15
INT1 / RB3
11
14
PWM0 / COMP0 / RB4
12
13
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Xin
RD3
RD2
in
AN4 / RA4
24 SOP
1
24
RA3 / AN3
2
23
RA2 / AN2
3
22
RA1 / AN1
AN7 / RA7
4
21
RA0 / EC0
VDD
5
20
RC1
RD0
6
19
RC0
RD1
7
18
VSS
AN0 / AVref / RB0
8
17
RESET
BUZ / RB1
9
16
Xout
INT0 / RB2
10
15
Xin
INT1 / RB3
11
14
RD3
PWM0 / COMP0 / RB4
12
13
RD2
P
AN5 / RA5
AN6 / RA6
4
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Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
4. PACKAGE DIAGRAM
24 PDIP
unit: inch
MAX
MIN
TYP 0.300
1.265
0.300
in
0.021
0.065
0.019
0.0138
Jan. 2001
0 ~ 8°
TYP 0.050
Preliminary
0.0125
0.104
0.093
0.614
0.593
0.0118
0.004
0.299
P
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0 ~ 15°
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0.009
24 SOP
4
0.01
8
0.00
0.419
0.398
0.045
TYP 0.100
0.292
0.015
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0.250
0.120
0.140
MAX 0.180
MIN 0.015
1.160
0.042
0.016
5
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
5. PIN FUNCTION
RB0~RB7: RB is a 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RBIO).
VDD: Supply voltage.
VSS: Circuit ground.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
RB serves the functions of the various following special
features in Table 5-2
XOUT: Output from the inverting oscillator amplifier.
Port pin
Alternate function
RB0
AN0 ( Analog Input Port 0 )
AVref ( External Analog Reference Pin )
BUZ ( Buzzer Driving Output Port )
INT0 ( External Interrupt Input Port 0 )
INT1 ( External Interrupt Input Port 1 )
PWM0 (PWM0 Output)
COMP0 (Timer1 Compare Output)
RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port.
RA pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RAIO).
Port pin
Alternate function
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
EC0 ( Event Counter Input Source )
AN1 ( Analog Input Port 1 )
AN2 ( Analog Input Port 2 )
AN3 ( Analog Input Port 3 )
AN4 ( Analog Input Port 4 )
AN5 ( Analog Input Port 5 )
AN6 ( Analog Input Port 6 )
AN7 ( Analog Input Port 7 )
Table 5-1 RA Port
P
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Table 5-2 RB Port
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RC0, RC1: RC is a 2-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RCIO).
in
RD0~RD3: RD is a 4-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RDIO).
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In addition, RA serves the functions of the various special
features in Table 5-1 .
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RB1
RB2
RB3
RB4
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
PIN NAME
HMS87C1304A/HMS87C1302A
Pin No.
In/Out
Function
VDD
5
-
Supply voltage
VSS
18
-
Circuit ground
RESET
17
I
Reset signal input
XIN
15
I
XOUT
16
O
RA0 (EC0)
21
I/O (Input)
External Event Counter input 0
RA1 (AN1)
22
I/O (Input)
Analog Input Port 1
RA2 (AN2)
23
I/O (Input)
Analog Input Port 2
RA3 (AN3)
24
I/O (Input)
Analog Input Port 3
8-bit general I/O ports
RA4 (AN4)
1
I/O (Input)
Analog Input Port 4
RA5 (AN5)
2
I/O (Input)
Analog Input Port 5
RA6 (AN6)
3
I/O (Input)
Analog Input Port 6
RA7 (AN7)
4
I/O (Input)
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Analog Input Port 7
RB0 (AVref/AN0)
8
I/O (Input)
RB1 (BUZ)
9
I/O (Input)
RB2 (INT0)
10
I/O (Input)
RB3 (INT1)
11
I/O (Output)
RB4 (PWM0/COMP0)
12
I/O (Output/Output)
RC0
19
I/O
RC1
20
I/O
RD0
6
Analog Input Port 0 / Analog Reference
Buzzer Driving Output
in
5-bit general I/O ports
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External Interrupt Input 0
External Interrupt Input 1
PWM0 Output or Timer1 Compare Output
2-bit general I/O ports
RD1
7
RD2
13
RD3
14
Jan. 2001
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I/O
I/O
P
4-bit general I/O ports
I/O
I/O
Table 5-3 Pin Description
Preliminary
7
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
6. PORT STRUCTURES
• RESET
Internal RESET
VSS
• Xin, Xout
Crystal or Ceramic
VDD
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in
STOP
To System CLK
RC Oscillation
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Xout
VSS
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Xin
VDD
Xout
STOP
VSS
To System CLK
Xin
Internal Capacitor 6 pF
8
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
• RA0/EC0
Open Drain
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
Read
EC0
Schmitt Trigger
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• RA1/AN1 ~ RA7/AN7
in
Data Reg.
Data Bus
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VDD
Direction Reg.
Data Bus
Data Bus
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VSS
Read
To A/D Converter
Analog Input Mode
(ANSEL7 ~ 1)
Analog CH. Selection
(ADCM.4 ~ 2)
Jan. 2001
Preliminary
9
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
• RB0 / AN0 / AVref
VDD
Data Reg.
Data Bus
AVREFS
Direction Reg.
Data Bus
VSS
Data Bus
Read
To A/D Converter
Analog Input Mode
(ANSEL0)
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Analog CH0 Selection
(ADCM.4 ~ 2)
1
To Vref of A/D
0
Internal VDD
in
AVREFS
• RB1/BUZ, RB4/PWM0/COMP0
PWM/COMP
BUZ
P
Data Reg.
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VDD
1
0
Data Bus
Function
Select
Direction Reg.
Data Bus
VSS
Data Bus
Read
10
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
• RB2/INT0, RB3/INT1
Open Drain
Pull-up
Select
Weak Pull-up
Data Reg.
VDD
Data Bus
Function
Select
Direction Reg.
Data Bus
VSS
Data Bus
Read
Schmitt Trigger
INT0, INT1
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• RC0, RD0, RD1, RD2, RD3
in
Data Reg.
Data Bus
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Direction Reg.
Data Bus
Data Bus
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Read
• RC1
Open Drain
VDD
Data Reg.
Data Bus
Direction Reg.
Data Bus
VSS
Data Bus
Read
Jan. 2001
Preliminary
11
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V
Storage Temperature ................................-40 to +125 °C
Voltage on any pin with respect to Ground (VSS)
............................................................... -0.3 to VDD+0.3
Maximum current out of VSS pin ........................200 mA
Maximum current into V DD pin ..........................150 mA
Maximum current sunk by (I OL per I/O Pin) ........25 mA
Maximum output current sourced by (IOH per I/O Pin)
...............................................................................15 mA
Maximum current (ΣIOL) ....................................150 mA
Maximum current (ΣIOH).................................... 100 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
7.2 Recommended Operating Conditions
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Specifications
Parameter
Symbol
fXIN=8MHz
VDD
Supply Voltage
Operating Frequency
Operating Temperature
Condition
in
fXIN=4.2MHz
VDD=4.5~5.5V
fXIN
VDD=2.0~5.5V
TOPR
7.3 A/D Converter Characteristics
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Unit
Min.
Max.
4.5
5.5
V
2.0
5.5
V
1
8
MHz
1
4.2
MHz
-20
85
°C
(TA=25°C, VSS=0V, VDD=5.12V @fXIN =8MHz, VDD=3.072V @fXIN =4MHz)
Parameter
P
Analog Input Voltage Range
Analog Power Supply Input Voltage Range
Specifications
Symbol
VAIN
VREF
Condition
Unit
Min.
Typ.
Max.
AVREFS=0
VSS
-
VDD
AVREFS=1
VSS
-
VREF
VDD=5V
3
-
VDD
V
VDD=3V
2.4
-
VDD
V
V
Overall Accuracy
NACC
-
±1.0
±1.5
LSB
Non-Linearity Error
NNLE
-
±1.0
±1.5
LSB
Differential Non-Linearity Error
NDNLE
-
±1.0
±1.5
LSB
Zero Offset Error
NZOE
-
±0.5
±1.5
LSB
Full Scale Error
NFSE
-
±0.25
±0.5
LSB
Gain Error
NNLE
-
±1.0
±1.5
LSB
fXIN=8MHz
-
-
10
fXIN=4MHz
-
-
20
AVREFS=1
-
0.5
1.0
Conversion Time
AVREF Input Current
12
TCONV
IREF
Preliminary
µS
mA
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
7.4 DC Electrical Characteristics
(TA=-20~85°C, VDD=2.0~5.5V, VSS=0V),
Specifications
Parameter
Symbol
Pin
Condition
Unit
Min.
Typ.
Max.
VIH1
XIN, RESET
0.8 VDD
-
VDD
VIH2
Hysteresis Input1
0.8 VDD
-
VDD
VIH3
Normal Input
0.7 VDD
-
VDD
VIL1
XIN, RESET
0
-
0.2 VDD
VIL2
Hysteresis Input1
0
-
0.2 VDD
VIL3
Normal Input
0
-
0.3 VDD
Output High Voltage
VOH
All Output Port
VDD=5V, IOH=-5mA
VDD -1
-
-
V
Output Low Voltage
VOL
All Output Port
VDD=5V, IOL=10mA
-
-
1
V
Input Pull-up Current
IP
-550
-420
-200
µA
-
-
5
µA
-
-
15
µA
-5
-
-
µA
-15
-
-
µA
0.5
-
-
V
PFD Level = 0
2.5
3.0
3.5
PFD Level = 1
2.0
2.5
3.0
VDD=5V
40
120
VDD=3V
95
280
Input High Voltage
Input Low Voltage
Input High
Leakage Current
Input Low
Leakage Current
Hysteresis
PFD Voltage
RB2, RB3, RD0, RD1 VDD=5V
IIH1
All Pins (except XIN)
VDD=5V
IIH2
XIN
VDD=5V
IIL1
All Pins (except XIN)
VDD=5V
IIL2
XIN
VDD=5V
| VT |
Hysteresis
VPFD1
VDD
VPFD2
VDD
Internal RC WDT
Period
TRCWDT
Operating Current
IDD
VDD
Wake-up Timer
Mode Current
IWKUP
VDD
RCWDT Mode
Current at STOP
Mode
IRCWDT
VDD
ISTOP
VDD
Stop Mode Current
P
Input1
VDD=5V
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V
V
V
VDD=5.5V, fXIN=8MHz
-
5
6
VDD=3.0V, fXIN=4MHz
-
2
3
VDD=5.5V, fXIN=8MHz
-
1
2
VDD=3.0V, fXIN=4MHz
-
0.5
1
VDD=5.5V
-
-
200
VDD=3.0V
-
-
100
VDD=5.5V, fXIN=8MHz
-
0.5
3
VDD=3.0V, fXIN=4MHz
-
0.2
1
µS
mA
mA
µA
µA
1. Hysteresis Input: RB2, RB3
Jan. 2001
Preliminary
13
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
7.5 AC Characteristics
(TA=-20~+85°C, VDD=5V±10%, VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
fCP
XIN
1
-
8
MHz
tCPW
XIN
80
-
-
nS
tRCP,tFCP
XIN
-
-
20
nS
Oscillation Stabilizing Time
tST
XIN, XOUT
-
-
20
mS
External Input Pulse Width
tEPW
INT0, INT1, EC0
2
-
-
tSYS
RESET Input Width
tRST
RESET
8
-
-
tSYS
Operating Frequency
External Clock Pulse Width
External Clock Transition Time
tCPW
1/fCP
a
n
XIN
i
tRCP
tSYS
ry
tCPW
VDD-0.5V
0.5V
tFCP
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tRST
RESET
INT0, INT1
EC0
P
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tEPW
0.2VDD
tEPW
0.8VDD
0.2VDD
Figure 7-1 Timing Chart
14
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
7.6 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
Operating Area
Normal Operation
IDD−VDD
fXIN
(MHz)
IDD
(mA)
Ta= 25°C
10
Ta=25°C
8
8
6
6
fXIN = 8MHz
4
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4
4MHz
2
2
0
0
2
3
4
5
in
VDD
(V)
6
STOP Mode
ISTOP−VDD
IDD
(µA)
fXIN = 8MHz
0.8
P
0.6
0.4
0.2
0
2
3
4
5
2
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3
4
5
VDD
6 (V)
Wake-up Timer Mode
IWKUP−VDD
-25°C
IDD
(mA)
25°C
2.0
Ta=25°C
85°C
1.5
fXIN = 8MHz
1.0
0.5
4MHz
0
VDD
6 (V)
2
3
4
5
VDD
6 (V)
RC-WDT in Stop Mode
IRCWDT−VDD
IDD
(µA)
Ta=25°C
20
15
TRCWDT = 80uS
10
5
0
2
Jan. 2001
3
4
5
VDD
6 (V)
Preliminary
15
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
IOL−VOL, VDD=5V
IOH−VOH, VDD=5V
IOL
(mA)
IOH
(mA)
-25°C
25°C
40
-25°C
25°C
-20
85°C
85°C
30
-15
20
-10
10
-5
0
1
VIH1
(V)
2
3
VDD−VIH1
XIN, RESET
2
VDD−VIH2
VIH2
(V)
fXIN=4MHz
Ta=25°C
4
4
3
3
2
2
0
1
VIL1
(V)
2
3
4
5
P
VDD
6 (V)
VDD−VIL1
XIN, RESET
VDD−VIL2
VIL2
(V)
fXIN=4MHz
Ta=25°C
in
4
VDD−VIH3
VIH3
(V)
4
5
VDD
6 (V)
0
2
VIL3
(V)
f X IN =4kH z
Ta=25°C
3
3
2
2
2
1
1
1
3
4
5
VDD
6 (V)
4
0
2
3
4
5
Preliminary
VDD
6 (V)
3
VDD−VIL3
Hysteresis input
3
2
f X IN =4kH z
Ta=25°C
1
4
1
Normal input
3
4
0
VOH
6 (V)
5
2
0
3
4
Hysteresis input
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2
3
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f X IN =4kH z
Ta=25°C
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1
1
16
0
VOL
5 (V)
4
4
5
VDD
6 (V)
Normal input
f X IN =4kH z
Ta=25°C
0
2
3
4
5
VDD
6 (V)
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
8. MEMORY ORGANIZATION
The HMS87C1304A and HMS87C1302A have separate
address spaces for Program memory and Data Memory.
Program memory can only be read, not written to. It can be
up to 4K /8K bytes of Program memory. Data memory can
be read and written to up to 192 bytes including the stack
area.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
PCH
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 00H to 7FH
of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “7FH ” is
used.
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
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The Accumulator can be used as a 16-bit register with Y
Register as shown below.
Y
Y
P
A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
Jan. 2001
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Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
ry
Stack Address (000H ~ 07FH)
15
0
8
7
0
SP
Hardware fixed
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX
#07FH
TXSP
; SP ← 7FH
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is “0” and is cleared by any other result.
Preliminary
17
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
MSB
PSW
N
LSB
V
-
B
H
I
Z
C
RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
BRK FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
dress.
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Overflow flag V]
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
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This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
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This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH ) or -128(80H ). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but these devices have 4K/2K bytes program
memory space only physically implemented. Accessing a
location above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
Figure 8-4 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-5 .
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
As shown in Figure 8-4 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
F000H
LDA
#5
TCALL 0FH
:
:
;1BYTE INSTRUCTION
;INSTEAD OF 3 BYTES
;NORM AL CALL
1
;TCALL ADDRESS AREA
HMS87C1304A
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F800H
PROGRAM
MEMORY
HMS87C1302A
FEFFH
FF00H
FFC0H
FFDFH
FFE0H
FFFFH
TCALL
AREA
in
PCALL
AREA
INTERRUPT
VECTOR AREA
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Figure 8-4 Program Memory Map
P
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
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As for the area from 0FF00H to 0FFFFH, if any area of
them is not going to be used, its service location is available as general purpose Program Memory.
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-6 .
Address
0FFE0H
E2
Vector Area Memory
-
E4
-
E6
Basic Interval Interrupt Vector Area
E8
Watchdog Timer Interrupt Vector Area
EA
A/D Converter Interrupt Vector Area
EC
-
EE
-
F0
-
F2
-
F4
Timer/Counter 1 Interrupt Vector Area
F6
Timer/Counter 0 Interrupt Vector Area
F8
External Interrupt 1 Vector Area
FA
External Interrupt 0 Vector Area
FC
-
FE
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 8-5 Interrupt Vector Area
Jan. 2001
Preliminary
19
HMS87C1304A/HMS87C1302A
Address
HYUNDAI MicroElectronics
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(256 Bytes)
0FFFFH
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
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TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
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Address
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-6 PCALL and TCALL Memory Area
PCALL→
→ rel
4F35
PCALL 35H
TCALL→
→n
4A
TCALL 4
4A
4F
35
~
~
~
~
~
~
0F125H
01001010
~
~
NEXT
þ
Reverse
PC: 11111111 11010110
FH FH
D H 6H
0FF00H
Ã
0FF35H
0FFFFH
NEXT
0FF00H
0FFD6H
25
0FFD7H
F1
À
0FFFFH
20
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
BIT_INT
WDT_INT
AD_INT
NOT_USED
NOT_USED
NOT_USED
NOT_USED
TMR1_INT
TMR0_INT
INT1
INT0
NOT_USED
RESET
ORG
0F000H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
(0FFEO)
(0FFE2)
(0FFE4)
(0FFE6)
(0FFE8)
(0FFEA)
(0FFEC)
(0FFEE)
(0FFF0)
(0FFF2)
(0FFF4)
(0FFF6)
(0FFF8)
(0FFFA)
(0FFFC)
(0FFFE)
Basic Interval Timer
Watchdog Timer
A/D
Timer-1
Timer-0
Int.1
Int.0
Reset
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;********************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET: DI
;Disable All Interrupts
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!007FH)
STA
{X}+
CMPX
#080H
BNE
RAM_CLR
;
LDX
#07FH
;Stack Pointer Initialize
TXSP
;
CALL
INITIAL
;
;
LDM
RA, #0
;Normal Port A
LDM
RAIO,#1000_0010B ;Normal Port Direction
LDM
RB, #0
;Normal Port B
LDM
RBIO,#0000_0010B ;Normal Port Direction
:
:
LDM
PFDR,#0
;Enable Power Fail Detector
:
:
in
P
Jan. 2001
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Preliminary
21
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
8.3 Data Memory
Figure 8-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.
0000H
USER
MEMORY
(including STACK)
007FH
PAGE0
0080H
00BFH
00C0H
00FFH
CONTROL
REGISTERS
Address
Symbol
R/W
RESET
Value
Addressing
mode
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0CAH
0CBH
0CCH
RA
RAIO
RB
RBIO
RC
RCIO
RD
RDIO
RAFUNC
RBFUNC
PUPSEL
R/W
W
R/W
W
R/W
W
R/W
W
W
W
W
Undefined
0000_0000
Undefined
0000_0000
Undefined
----_--00
Undefined
----_0000
0000_0000
0000_0000
----_--00
byte, bit1
byte2
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte
byte
byte
0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H
TM0
T0
TDR0
CDR0
TM1
TDR1
T1PPR
T1
CDR1
T1PDR
PWM0HR
R/W
R
W
R
R/W
W
W
R
R
R/W
W
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte, bit
byte
0DEH
BUR
W
1111_1111
byte
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
0ECH
0EDH
0EDH
0EFH
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
WDTR
PFDR
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R
W
R/W
0000_---000-_---0000_---000-_-------_0000
--00_0001
Undefined
0000_0000
-001_0111
0000_0000
0111_1111
----_-100
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte, bit
Figure 8-7 Data Memory Map
User Memory
The HMS87C1304A and HMS87C1302A has 128 × 8 bits
for the user memory (RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
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Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained
in each peripheral section.
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Table 8-1 Control Registers
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
1. “byte, bit” means that register can be addressed by not only bit
but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
Example; To write at CKCTLR
LDM
22
CKCTLR,#09H ;Divide ratio ÷16
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Note: Several names are given at same address. Refer to
below table.
When read
When write
Addr.
Timer
Mode
Capture
Mode
PWM
Mode
Timer
Mode
PWM
Mode
D1H
T0
CDR0
-
TDR0
-
TDR1
T1PPR
-
T1PDR
D3H
D4H
ECH
T1
CDR1
BITR
T1PDR
CKCTLR
Table 8-2 Various Register Name in Same Address
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save.
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Preliminary
23
HMS87C1304A/HMS87C1302A
Address
Name
Bit 7
HYUNDAI MicroElectronics
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C0H
RA
RA Port Data Register
C1H
RAIO
RA Port Direction Register
C2H
RB
RB Port Data Register
C3H
RBIO
RB Port Direction Register
C4H
RC
RC Port Data Register
C5H
RCIO
RC Port Direction Register
C6H
RD
RD Port Data Register
C7H
RDIO
RD Port Direction Register
CAH
RAFUNC
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
CBH
RBFUNC
TMR2OV
EC1I
PWM1O
PWM0O
INT1I
INT0I
BUZO
AVREFS
CCH
PUPSEL
-
-
-
-
D0H
TM0
-
-
CAP0
T0CK2
D1H
T0/TDR0/
CDR0
D2H
TM1
D3H
TDR1/
T1PPR
Timer1 Data Register / PWM0 Period Register
D4H
T1/CDR1/
T1PDR
Timer1 Register / Capture1 Data Register / PWM0 Duty Register
D5H
PWM0HR
PWM0 High Register
DEH
BUR
BUCK1
BUCK0
E2H
IENH
INT0E
INT1E
E3H
IENL
ADE
WDTE
E4H
IRQH
INT0IF
E5H
IRQL
ADIF
E6H
IEDS
-
EAH
ADCM
-
EBH
ADCR
ADC Result Data Register
ECH
BITR1
Basic Interval Timer Data Register
ECH
CKCTLR1
EDH
WDTR
WDTCL
EFH
PFDR2
-
PUPSEL1 PUPSEL0
T0CK1
T0CK0
ry
T0CN
T0ST
T1CN
T1ST
Timer0 Register / Timer0 Data Register / Capture0 Data Register
POL
-
16BIT
PWM0E
CAP1
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T1CK1
T1CK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
T0E
T1E
-
-
-
-
BITE
-
-
-
-
-
INT1IF
T0IF
T1IF
-
-
-
-
WDTIF
BITIF
-
-
-
-
-
-
-
-
IED1H
IED1L
IED0H
IED0L
-
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
WDTON
BTCL
BTS2
BTS1
BTS0
-
PFDIS
PFDM
PFDS
P
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WAKEUP
RCWDT
7-bit Watchdog Counter Register
-
-
-
Table 8-3 Control Registers of HMS87C1304A and HMS87C1302A
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp,#imm”.
1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
24
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
8.4 Addressing Mode
The HMS87C1304A and HMS87C1302A uses six addressing modes;
(3) Direct Page Addressing → dp
• Register addressing
Example;
• Immediate addressing
C535
In this mode, a address is specified within direct page.
LDA
;A ←RAM[35H]
35H
• Direct page addressing
• Absolute addressing
0035H
data
À
• Indexed addressing
~
~
• Register-indirect addressing
~
~
0F550H
C5
0F551H
35
þ
data → A
(1) Register Addressing
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Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
(4) Absolute Addressing → !abs
In this mode, second byte (operand) is accessed as a data
immediately.
Example:
0435
ADC
#35H
MEMORY
04
P
A+35H+C → A
35
E45535
LDM
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Absolute addressing sets corresponding memory data to
Data, i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
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ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
0735F0
ADC
data
0F035H
35H,#55H
~
~
0F100H
data ← 55H
data
0035H
~
~
~
~
þ
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
À
E4
0F101H
55
0F102H
35
Jan. 2001
À
~
~
þ
0F100H
;A ←ROM[0F035H]
!0F035H
Preliminary
25
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
X indexed direct page, auto increment→
→ {X}+
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
Example; Addressing accesses the address 0135H.
983500
INC
;A ←RAM[035H]
!0035H
LDA, STA
Example; X=35H
DB
data
0035H
~
~
LDA
{X}+
Ã
À
~
~
data+1 → data
0F100H
98
þ
0F101H
35
address: 0035
0F102H
00
35H
À
data
~
~
data → A
~
~
þ
36H → X
DB
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(5) Indexed Addressing
X indexed direct page (no offset) → {X}
X indexed direct page (8 bit offset) → dp+X
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H
D4
LDA
15H
{X}
~
~
À
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Example; X=015H
C645
LDA
45H+X
data → A
~
~
þ
0E550H
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ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
;ACC←RAM[X].
data
in
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
5AH
D4
data
Ã
~
~
26
~
~
0E550H
C6
0E551H
45
Preliminary
À
data → A
þ
45H+15H=5AH
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
E3
Y indexed absolute →!abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
0E30AH
LDA
0FA00H
D5
0F101H
00
0F102H
FA
~
~
0FA55H
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X indexed indirect → [dp+X]
0FA00H+55H=0FA55H
~
~
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusX-register data in Direct
page.
in
À
data
Ã
Direct page indirect → [dp]
data → A
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ADC, AND, CMP, EOR, LDA, OR, SBC, STA
P
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Example; X=10H
1625
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
ADC
[25H+X]
35H
05
36H
E0
0E005H
~
~ À
~
~
0E005H
JMP, CALL
0FA00H
25 + X(10) = 35H
~
~
16
25
Preliminary
þ
data
~
~
Example;
Jan. 2001
þ
35
þ
(6) Indirect Addressing
~
~
3F
!0FA00H+Y
0F100H
À jump to address 0E30AH
NEXT
~
~
Example; Y=55H
D500FA
~
~
à A + data + C → A
27
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example;
Example; Y=10H
1725
ADC
JMP
1F25E0
JMP
[!0C025H]
[25H]+Y
PROGRAM MEMORY
25H
05
0E025H
25
26H
E0
0E026H
E7
~
~
0E015H
~
~
0FA00H
0E005H + Y(10) = 0E015H
þ
0E725H
~
~
y
r
a
0FA00H
17
in
à A + data + C → A
P
e
r
À
jump to
address 0E30AH
NEXT
~
~
~
~
25
28
~
~
þ
data
~
~
À
~
~
1F
25
E0
il m
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
9. I/O PORTS
The HMS87C1304A and HMS87C1302A has four ports,
RA, RB, RC and RD. These ports pins may be multiplexed
with an alternate function for the peripheral features on the
device. In general, when a initial reset state, all ports are
used as a general purpose input port.
All pins have data direction registers which can set these
ports as output or input. A “1” in the port direction register
defines the corresponding port pin as output. Conversely,
write “0” to the corresponding bit to specify as an input
pin. For example, to use the even numbered bit of RA as
output ports and the odd numbered bits as input ports, write
“55H” to address C1H (RA direction register) during initial
setting as shown in Figure 9-1 .
Reading data register reads the status of the pins whereas
writing to it will write to the port latch.
WRITE “55H” TO PORT RA DIRECTION REGISTER
C0H
RA DATA
C1H
RA DIRECTION
C2H
RB DATA
C3H
RB DIRECTION
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
I
O
I
O
I O
I
BIT
O
7 6 5 4 3 2 1 0 PORT
I: INPUT PORT
O: OUTPUT PORT
Figure 9-1 Example of port I/O assignment
9.1 RA and RAIO registers
RA is an 8-bit bidirectional I/O port (address C0H). Each
port can be set individually as input and output through the
RAIO register (address C1H).
RA7~RA1 ports are multiplexed with Analog Input Port
(AN7~AN1) and RA0 port is multiplexed with Event
Counter Input Port (EC0).
RA Data Register
RA
ADDRESS : C0H
RESET VALUE : Undefined
RA Direction Register
e
r
RAFUNC
Description
0
RA7 (Normal I/O Port)
1
AN7 (ADS2~0=111)
0
RA6 (Normal I/O Port)
1
AN6 (ADS2~0=110)
0
RA5 (Normal I/O Port)
1
AN5 (ADS2~0=101)
0
RA4 (Normal I/O Port)
1
AN4 (ADS2~0=100)
0
RA3 (Normal I/O Port)
1
AN3 (ADS2~0=011)
0
RA2 (Normal I/O Port)
1
AN2 (ADS2~0=010)
0
RA1 (Normal I/O Port)
1
AN1 (ADS2~0=001)
RA7/AN7
RA6/AN6
ADDRESS : CAH
RESET VALUE : 00000000
0 : RB0
1 : AN0
0 : RA1
1 : AN1
0 : RA2
1 : AN2
0 : RA3
1 : AN3
RA3/AN3
RA2/AN2
RA1/AN1
RA0/EC01
Figure 9-2 Registers of Port RA
The control register RAFUNC (address CAH) controls to
Jan. 2001
RAFUNC.7~0
RA4/AN4
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
0 : RA4
1 : AN4
0 : RA5
1 : AN5
0 : RA6
1 : AN6
0 : RA7
1 : AN7
PORT
RA5/AN5
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
RA Function Selection Register
in
ADDRESS : C1H
RESET VALUE : 00000000
P
RAIO
y
r
a
il m
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
INPUT / OUTPUT DATA
select alternate function. After reset, this value is “0”, port
may be used as general I/O ports. To select alternate function such as Analog Input or External Event Counter Input,
write “1” to the corresponding bit of RAFUNC.Regardless
of the direction register RAIO, RAFUNC is selected to use
as alternate functions, port pin can be used as a corresponding alternate features (RA0/EC0 is controlled by RBFUNC)
RA0 (Normal I/O Port)
EC0 (T0CK2~0=111)
1. This port is not an Analog Input port, but Event Counter clock
source input port. ECO is controlled by setting TOCK2~0 =
111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref
port (Refer to Port RB).
Preliminary
29
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
9.2 RB and RBIO registers
RB is a 5-bit bidirectional I/O port (address C2H). Each
pin can be set individually as input and output through the
RBIO register (address C3H). In addition, Port RB is multiplexed with various special features. The control register
RBFUNC (address CBH) controls to select alternate func-
Pull-up Selection Register
RB Data Register
RB
-
-
-
tion. After reset, this value is “0”, port may be used as general I/O ports. To select alternate function such as External
interrupt or Timer compare output, write “1” to the corresponding bit of RBFUNC.
ADDRESS : C2H
RESET VALUE : Undefined
RB4
ADDRESS : CCH
RESET VALUE : ------00
PUPSEL
RB3 RB2 RB1 RB0
-
-
-
-
-
RB1 / INT1 Pull-up
0 : No Pull-up
1 : With Pull-up
INPUT / OUTPUT DATA
ry
PUP1
PUP0
RB0 / INT0 Pull-up
0 : No Pull-up
1 : With Pull-up
Interrupt Edge Selection Register
RB Direction Register
ADDRESS : C3H
RESET VALUE : ---00000
RBIO
-
-
i
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
P
a
n
IEDS
e
r
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-
-
-
ADDRESS : E6H
RESET VALUE : ----0000
IED1H
IED1L
IED0H
INT1
IED0L
INT0
External Interrupt Edge Select
00 : Normal I/O port
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
RB Function Selection Register
RBFUNC
-
-
-
PWM0O
ADDRESS : CBH
RESET VALUE : ---00000
INT1I
INT0I
BUZO
AVREFS
0 : RB0 when ANSEL0 = 0
AN0 when ANSEL0 = 1
1 : AVref
0 : RB1
1 : BUZ Output
0 : RB2
1 : INT0
0 : RB3
1 : INT1
0 : RB4
1 : PWM0 Output or
Compare Output
Figure 9-3 Registers of Port RB
Regardless of the direction register RBIO, RBFUNC is selected to use as alternate functions, port pin can be used as
30
a corresponding alternate features.
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
PORT
RBFUNC.4~0
RB4/
PWM0/
COMP0
0
RB4 (Normal I/O Port)
1
PWM0 Output /
Timer1 Compare Output
0
RB3 (Normal I/O Port)
1
External Interrupt Input 1
0
RB2 (Normal I/O Port)
1
External Interrupt Input 0
0
RB1 (Normal I/O Port)
1
Buzzer Output
01
RB0 (Normal I/O Port)/
AN0 (ANSEL0=1)
12
External Analog Reference
Voltage
RB3/INT1
RB2/INT0
RB1/BUZ
RB0/AN0/
AVref
Description
y
r
a
1. When ANSEL0 = “0”, this port is defined for normal I/O port
(RB0).
When ANSEL0 = “1” and ADS2~0 = “000”, this port
can be used Analog Input Port (AN0).
2. When this bit set to “1”, this port defined for AVref, so it can
not be used Analog Input Port AN0 and Normal I/O
Port RB0.
in
P
Jan. 2001
e
r
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Preliminary
31
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
9.3 RC and RCIO registers
RC is a 2-bit bidirectional I/O port (address C4H). Each
pin can be set individually as input and output through the
ADDRESS : C4H
RESET VALUE : Undefined
RC Data Register
-
RC
-
-
-
-
-
RC1
RC0
RCIO register (address C5H).
RC Direction Register
ADDRESS : C5H
RESET VALUE : ------00
RCIO
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
INPUT / OUTPUT DATA
Figure 9-4 Registers of Port RC
9.4 RD and RDIO registers
RD is a 4-bit bidirectional I/O port (address C6H). Each
pin can be set individually as input and output through the
-
-
ry
RD Direction Register
RD Data Register
RD
-
RDIO register (address C7H).
ADDRESS : C6H
RESET VALUE : Undefined
-
a
n
RDIO
RD3 RD2 RD1 RD0
i
INPUT / OUTPUT DATA
e
r
il m
ADDRESS : C7H
RESET VALUE : -----000
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
Figure 9-5 Registers of Port RD
P
32
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
10. CLOCK GENERATOR
The clock generator produces the basic clock pulses which
provide the system clock to be supplied to the CPU and peripheral hardware. The main system clock oscillator oscillates
with a crystal resonator or a ceramic resonator connected to the
OSCILLATION
CIRCUIT
fxin
Xin and Xout pins. External clocks can be input to the main
system clock oscillator. In this case, input a clock signal to
the Xin pin and open the Xout pin.
CLOCK PULSE
GENERATOR
Internal system clock
PRESCALER
STOP
WAKEUP
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128
÷256
÷512
y
r
a
÷1024 ÷2048
Peripheral clock
in
Figure 10-1 Block Diagram of Clock Pulse Generator
10.1 Oscillation Circuit
il m
XIN and XOUT are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 10-2 .
Xout
C1
C2
R1
P
Xin
e
r
values of external components.
OPEN
External
Clock
Source
Xout
Xin
Vss
Vss
Figure 10-3 External Clock Connections
Recommended: C1, C2 = 30pF±10pF for Crystals
R1 = 1MΩ
Figure 10-2 Oscillator Connections
To drive the device from an external clock source, Xout
should be left unconnected while Xin is driven as shown in
Figure 10-3 . There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified on
the data sheet must be observed.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
Jan. 2001
Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 10-2 to prevent
any effects from wiring capacities.
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal
conductors.
- Do not allow wiring to come near changing high
current.
- Set the potential of the grounding position of the
oscillator capacitor to that of VSS. Do not ground to
any ground pattern where high current is present.
- Do not fetch signals from the oscillator.
In addition, the HMS87C1304A and HMS87C1302A has
an ability for the external RC oscillated operation. It offers
additional cost savings for timing insensitive applica-
Preliminary
33
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
tions. The RC oscillator frequency is a function of the supply voltage, the external resistor (Rext) and capacitor
(Cext) values, and the operating temperature.
The user needs to take into account variation due to tolerance of external R and C components used. Figure 10-4
shows how the RC combination is connected to the
HMS87C1304A or HMS87C1302A.
Figure 10-4 RC Oscillator Connections
The oscillator frequency, divided by 4, is output from the
Xout pin, and can be used for test purpose or to synchroze
other logic.
To set the RC oscillation, it should be programmed
RCOPT bit to "1" to CONFIG (0FF0H). ( Refer to DEVICE CONFIGURATION AREA )
Vdd
Rext
Xin
Cext
fxin÷4
Xout
y
r
a
in
P
34
e
r
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Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
11. Basic Interval Timer
The HMS87C1304A and HMS87C1302A has one 8-bit
Basic Interval Timer that is free-run, can not stop. Block
diagram is shown in Figure 11-1 .The 8-bit Basic interval
timer register (BITR) is increased every internal count
pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of
the oscillator frequency. As the count overflows from FFH
to 00H, this overflow causes to generate the Basic interval
timer interrupt. The BITF is interrupt request flag of Basic
interval timer.
mode. In this mode, all of the block is halted except the oscillator, prescaler (only fxin÷2048) and Timer0.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0” after one machine cycle by hardware.
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction..
If the STOP instruction executed after writing “1” to bit
RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer
If the STOP instruction executed after writing “1” to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
y
r
a
WAKEUP
RCWDT
STOP
BTS[2:0]
÷8
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
fxin
in
BTCL
3
Clear
8
MUX
0
il m
BITIF
BITR (8BIT)
1
Internal RC OSC
To Watchdog Timer
P
e
r
Basic Interval Timer
Interrupt
Figure 11-1 Block Diagram of Basic Interval Timer
Clock Control Register
CKCTLR
-
WAKEUP RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
Basic Interval Timer Clock Selection
Symbol
WAKEUP
Function Description
010 : fxin ÷ 32
RCWDT
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
WDTON
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
BTCL
000 : fxin ÷ 8
001 : fxin ÷ 16
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
011 : fxin ÷ 64
100 : fxin ÷ 128
101 : fxin ÷ 256
110 : fxin ÷ 512
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
111 : fxin ÷ 1024
Figure 11-2 CKCTLR: Clock Control Register
Jan. 2001
Preliminary
35
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
12. TIMER / COUNTER
The HMS87C1304A and HMS87C1302A has two Timer/
Counter registers. Each module can generate an interrupt
to indicate that an event has occurred (i.e. timer match).
Timer 0 and Timer 1 can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter by combining
them.
In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and
most clock consists of 2048 oscillator periods, the count
rate is 1/2 to 1/2048 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).
sponse to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0(Timer 0).
In addition the “capture” function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.
Timer1 is shared with “PWM” function and “Compare
output” function
It has seven operating modes: “8-bit timer/counter”, “16bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit
compare output”, “16-bit compare output” and “10-bit
PWM” which are selected by bit in Timer mode register
TMx as shown in Figure 12-1 and Table 12-1 .
In the “counter” function, the register is increased in re-
ry
Timer 0 Mode Register
TM0
-
-
CAP0
T0CK2
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
T0CK[2:0]
Input clock selection
000 : fxin ÷ 2, 100 : fxin ÷ 128
010 : fxin ÷ 8,
T0CK0
101 : fxin ÷ 512
110 : fxin ÷ 2048
il m
T0ST
e
r
T0CN
a
n
i
T0CN
CAP0
001 : fxin ÷ 4,
T0CK1
T0ST
ADDRESS : D0H
RESET VALUE : --000000
Continue control bit
0 : Stop counting
1 : Start counting continuously
Start control bit
0 : Stop counting
1 : Counter start ( It must be stop before restart )
011 : fxin ÷ 32, 111 : External Event ( EC0 )
Timer 1 Mode Register
TM1
POL
16BIT
P
PWM0E
CAP1
T1CK1
T1CK0
T1CN
T1ST
ADDRESS : D2H
RESET VALUE : 00000000
PWM Output Polarity
0 : Duty active low
1 : Duty active high
T1CK[2:0]
16BIT
16-bit mode selection
0 : 8-bit mode
1 : 16-bit mode
T1CN
Continue control bit
0 : Stop counting
1 : Start counting continuously
PWM0E
PWM enable bit
0 : Disables PWM
1 : Enables PWM
T1ST
Start control bit
0 : Stop counting
1 : Counter start ( It must be stop before restart )
CAP1
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
POL
Input clock selection
00 : fxin
10 : fxin ÷ 8
01 : fxin ÷ 2
11 : using the Timer 0 clock
Figure 12-1 Timer Mode Register (TM0, TM1)
36
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
16BIT
CAP0
CAP1
PWME
T0CK[2:0]
T1CK[1:0]
PWMO
TIMER 0
TIMER1
0
0
0
0
XXX
XX
0
8-bit Timer
8-bit Timer
0
0
1
0
111
XX
0
8-bit Event Counter
8-bit Capture
0
1
0
0
XXX
XX
1
8-bit Capture
8-bit Compare output
0
X1
0
1
XXX
XX
1
8-bit Timer/Counter
10-bit PWM
1
0
0
0
XXX
11
0
16-bit Timer
1
0
0
0
111
11
0
16-bit Event Counter
1
1
X
0
XXX
11
0
16-bit Capture
1
0
0
0
XXX
11
1
16-bit Compare output
Table 12-1 Operating Modes of Timer 0 and Timer 1
1. X: The value “0” or “1” corresponding your operation.
12.1 8-bit Timer/Counter Mode
The HMS87C1304A and HMS87C1302A has four 8-bit
Timer/Counters, Timer 0 and Timer 1 as shown in Figure
12-2 .
The “timer” or “counter” function is selected by mode reg-
TM0
TM1
-
-
CAP0
T0CK2
-
-
0
X
POL
16BIT
PWME
X
0
P
0
T0CK[2:0]
Edge Detector
e
r
CAP1
y
r
a
isters TMx as shown in Figure 12-1 and Table 12-1 . To
use as an 8-bit timer/counter mode, bit CAP0 of TM0 is
cleared to “0” and bits 16BIT of TM1 should be cleared to
“0”(Table 12-1 ).
in
il m
T0CK1
T0CK0
T0CN
T0ST
X
X
X
X
T1CK1
T1CK0
T1CN
T1ST
X
X
X
X
0
fxin
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
÷1
÷2
÷8
ADDRESS : D2H
RESET VALUE : 00000000
X: The value “0” or “1” corresponding your operation.
T0ST
0 : Stop
1 : Start
1
EC0
ADDRESS : D0H
RESET VALUE : --000000
CLEAR
T0 (8-bit)
MUX
TIMER 0
INTERRUPT
T0IF
COMPARATOR
T0CN
TDR0 (8-bit)
T1CK[1:0]
T1ST
0 : Stop
1 : Start
1
MUX
T1 (8-bit)
COMP0 PIN
CLEAR
F/F
T1IF
T1CN
TIMER 1
INTERRUPT
COMPARATOR
TDR1 (8-bit)
Figure 12-2 8-bit Timer / Counter Mode
Jan. 2001
Preliminary
37
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases
from 00H until it matches TDR0 and then reset to 00H. The
match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same
address, when reading it as a Tx, written to TDRx.
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit RA0 of the RA Direction Register RAIO
is set to “0”. The Timer 0 can be used as a counter by pin
EC0 input, but Timer 1 can not.
TDR1
n
n-1
up
-c
ou
nt
~~
7
6
5
y
r
a
4
3
2
1
0
Timer 1 (T1IF)
Interrupt
~~
PCP
~~
9
8
in
TIME
Interrupt period
= PCP x (n+1)
Occur interrupt
Occur interrupt
il m
Occur interrupt
Figure 12-3 Counting Example of Timer Data Registers
P
e
r
disable
~~
clear & start
enable
t
TDR1
up
-c
ou
n
stop
~~
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
T1ST
Start & Stop
T1ST = 0
Occur interrupt
T1ST = 1
T1CN
Control count
T1CN = 0
T1CN = 1
Figure 12-4 Timer Count Operation
38
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
12.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000 H . The
match output generates Timer 0 interrupt not Timer 1 interrupt.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
-
-
0
X
X
X
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
1
0
0
1
1
X
X
TM0
TM1
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0SL0.
ADDRESS : D0H
RESET VALUE : --000000
ADDRESS : D2H
RESET VALUE : 00000000
X: The value “0” or “1” corresponding your operation.
T0CK[2:0]
0 : Stop
1 : Start
1
EC0
fxin
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
y
r
a
T0ST
Edge Detector
in
T1 (8-bit)
MUX
T0CN
P
e
r
T0 (8-bit)
il m
TDR1 (8-bit)
CLEAR
T0IF
TIMER 0
INTERRUPT
COMPARATOR
F/F
TDR0 (8-bit)
COMP0 PIN
Figure 12-5 16-bit Timer / Counter Mode
12.3 8-bit Compare Output (16-bit)
The HMS87C1304A and HMS87C1302A has a function
of Timer Compare Output. To pulse out, the timer match
can goes to port pin(COMP0) as shown in Figure 12-2 and
Figure 12-5 . Thus, pulse out is generated by the timer
match. These operation is implemented to pin, RB4/
COMP0/PWM.
This pin output the signal having a 50: 50 duty square
wave, and output frequency is same as below equation.
= ------------------------------------------------------------------------------------------ × × ( + )
In this mode, the bit PWMO of RB function register (RBFUNC) should be set to “1”, and the bit PWME of timer1
mode register (TM1) should be set to “0”.
In addition, 16-bit Compare output mode is available, also.
12.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-6 .
As mentioned above, not only Timer 0 but Timer 1 can also
Jan. 2001
be used as a capture mode.
The Timer/Counter register is increased in response internal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
Preliminary
39
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
timer register T0 (T1) increases and matches TDR0
(TDR1).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 12-8 , the pulse width of captured
signal is wider than the timer data value (FF H ) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence.
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.
Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
TM0
TM1
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
-
-
1
X
X
X
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
X
0
0
1
X
X
in
T0CK[2:0]
1
fxin
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
MUX
P
X
ADDRESS : D2H
RESET VALUE : 00000000
X
T0ST
Edge Detector
EC0
y
r
a
T1ST
ADDRESS : D0H
RESET VALUE : --000000
e
r
il m
0 : Stop
1 : Start
T0IF
T0CN
CAPTURE
CLEAR
T0 (8-bit)
TIMER 0
INTERRUPT
COMPARATOR
CDR0 (8-bit)
TDR0 (8-bit)
INT0IF
INT0
INT 0
INTERRUPT
T0ST
0 : Stop
1 : Start
IEDS[1:0]
÷1
÷2
÷8
1
MUX
CLEAR
T1 (8-bit)
T1IF
T1CK[1:0]
T1CN
COMPARATOR
CDR1 (8-bit)
IEDS[3:2]
TIMER 1
INTERRUPT
TDR1 (8-bit)
CAPTURE
INT1IF
INT 1
INTERRUPT
INT1
Figure 12-6 8-bit Capture Mode
40
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
This value is loaded to CDR0
n
T0
n-1
up
-c
ou
nt
~~
~~
9
8
7
6
5
4
~~
3
2
1
0
TIME
Ext. INT0 Pin
Interrupt Request
(INT0F)
y
r
a
Interrupt Interval Period
in
Ext. INT0 Pin
Interrupt Request
(INT0F)
il m
Capture
(Timer Stop)
P
e
r
Delay
Clear & Start
Figure 12-7 Input Capture Operation
Ext. INT0 Pin
Interrupt Request
(INT0F)
Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H
Interrupt Request
(T0F)
FFH
FFH
T0
13H
00H
00H
Figure 12-8 Excess Timer Overflow in Capture Mode
Jan. 2001
Preliminary
41
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
12.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
-
-
1
X
X
X
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
1
0
X
1
1
X
X
TM0
TM1
ADDRESS : D0H
RESET VALUE : --000000
ADDRESS : D2H
RESET VALUE : 00000000
X: The value “0” or “1” corresponding your operation.
T0CK[2:0]
T0ST
Edge Detector
0 : Stop
1 : Start
y
r
a
1
EC0
fxin
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
CLEAR
T0 + T1 (16-bit)
MUX
T0CN
in
T0IF
TIMER 0
INTERRUPT
COMPARATOR
CAPTURE
CDR1
(8-bit)
INT0
IEDS[1:0]
P
e
r
CDR0
(8-bit)
TDR1
(8-bit)
TDR0
(8-bit)
il m
INT0IF
INT 0
INTERRUPT
Figure 12-9 16-bit Capture Mode
12.6 PWM Mode
The HMS87C1304A and HMS87C1302A has a high speed
PWM (Pulse Width Modulation) functions which shared
with Timer1.
In PWM mode, pin RB4/COMP0/PWM0 outputs up to a
10-bit resolution PWM output. This pin should be configure as a PWM output by setting “1” bit PWM0O in RBFUNC register.
The period of the PWM output is determined by the
T1PPR (PWM0 Period Register) and PWM0HR[3:2]
(bit3,2 of PWM0 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM0 Duty Register) and PWM0HR[1:0] (bit1,0 of PWM0 High Register).
And writes duty value to the T1PDR and the
PWM0HR[1:0] same way.
The T1PDR is configure as a double buffering for glitchless PWM output. In Figure 12-10 , the duty data is transferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle)
PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock
PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock
The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM0HR[3:2].
42
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
If it needed more higher frequency of PWM, it should be
reduced resolution.
It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-12 . As it were, the absolute duty time is not
changed in varying frequency. But the changed period value must greater than the duty value.
Frequency
Resolution
T1CK[1:0] =
00(125nS)
T1CK[1:0] =
01(250nS)
T1CK[1:0] =
10(1uS)
10-bit
7.8KHz
3.9KHz
0.98KHZ
9-bit
15.6KHz
7.8KHz
1.95KHz
8-bit
31.2KHz
15.6KHz
3.90KHz
7-bit
62.5KHz
31.2KHz
7.81KHz
Note: If changing the Timer1 to PWM function, it
should be stop the timer clock firstly, and then
set period and duty register value. If user
writes register values while timer is in operation, these register could be set with certain
values.
Table 12-2 PWM Frequency vs. Resolution at 8MHz
Ex)
LDM
LDM
LDM
LDM
LDM
LDM
The bit POL of TM1 decides the polarity of duty cycle.
If the duty value is set same to the period value, the PWM
output is determined by the bit POL (1: High, 0: Low). And
if the duty value is set to “00H”, the PWM output is determined by the bit POL (1: Low, 0: High).
TM1
PWM0HR
y
r
a
in
POL
16B IT
PW M E
CAP1
T 1C K 1
T 1C K 0
T1C N
T1ST
X
0
1
0
X
X
X
X
-
-
-
-
-
-
-
-
P
T1ST
T0 clock source
TM1,#00H
T1PPR,#00H
T1PDR,#00H
PWM0HR,#00H
RBFUNC,#0001_1100B
TM1,#1010_1011B
il m
PW M0HR3 PW M0HR2 PW M0HR1 PW M0HR0
e
r
X
X
X
Period High
ADDRESS : D2H
RESET VALUE : 00000000
ADDRESS : D5H
RESET VALUE : ----0000
Bit Manipulation Not Available
X
Duty High
X: The value “0” or “1” corresponding your operation.
PWM0HR[3:2]
T1PPR(8-bit)
0 : Stop
1 : Start
COMPARATOR
RB4/
PWM0
S Q
CLEAR
1
fxin
÷1
÷2
÷8
MUX
COMPARATOR
T1CK[1:0]
R
T1 (8-bit)
PWM0O
[RBFUNC.4]
POL
T1CN
Slave
T1PDR(8-bit)
PWM0HR[1:0]
Master
T1PDR(8-bit)
Figure 12-10 PWM Mode
Jan. 2001
Preliminary
43
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
~
~
~
~
fxin
02
03
04
05
80
81
3FF
00 01
02
03
~
~
~
~
PWM
POL=1
7F
~
~
~ ~
00 01
~ ~
~ ~
~
~
T1
~
~
PWM
POL=0
Duty Cycle [80H x 125nS = 16uS]
Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz]
T1CK[1:0] = 00 (fxin)
PWM0HR = 0CH
Period
T1PPR (8-bit)
PWM0HR3 PWM0HR2
1
1
FFH
T1PPR = FFH
T1PDR = 80H
Duty
y
r
a
T1PDR (8-bit)
PWM0HR1 PWM0HR0
0
0
80H
in
Figure 12-11 Example of PWM at 8MHz
T 1C K [1:0] = 10 (1uS )
P W M 0H R = 00H
T 1P P R = 0E H
T 1P D R = 05H
T1
e
r
Write T1PPR to 0AH
P
Source
clock
il m
01 02 03 04 05 06 07 08 09
0A 0B 0C 0D 0E
Period changed
01 02 03 04 05 06 07 08 09 0A
01 02 03 04
05
PWM
POL=1
Duty Cycle
[05H x 1uS = 5uS]
Duty Cycle
[05H x 1uS = 5uS]
Period Cycle [0EH x 1uS = 14uS, 71KHz]
Duty Cycle
[05H x 1uS = 5uS]
Period Cycle [0AH x 1uS = 10uS, 100KHz]
Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
44
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
13. Buzzer Output function
The buzzer driver consists of 6-bit binary counter, the
buzzer register BUR and the clock selector. It generates
square-wave which is very wide range frequency (480
Hz~250 KHz at fxin = 4 MHz) by user programmable
counter.
Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%.
The bit 0 to 5 of BUR determines output frequency for
buzzer driving. Frequency calculation is following as
shown below.
Pin RB1 is assigned for output port of Buzzer driver by setting the bit BUZO of RBFUNC to “1”.
The 6-bit buzzer counter is cleared and start the counting
by writing signal to the register BUR. It is increased from
00H until it matches 6-bit register BUR.
BUR
BUCK1
BUCK0
BUR5
Input clock selection
BUR4
BUR3
Oscillator Frequency
( ) = ------------------------------------------------------------------------------------ × Prescaler Ratio × ( + )
The bits BUCK1, BUCK0 of BUR selects the source clock
from prescaler output.
BUR2
BUR1
Buzzer Period Data
00 : fxin ÷ 8
y
r
a
01 : fxin ÷ 16
10 : fxin ÷ 32
11 : fxin ÷ 64
fxin
÷8
÷ 16
÷ 32
÷ 64
BUCK[1:0]
P
e
r
in
il m
COUNTER (6-bit)
MUX
ADDRESS : DEH
RESET VALUE : 11111111
Bit Manipulation Not Available
BUR0
F/F
COMPARATOR
BUR (6-bit)
RB1/BUZ PIN
BUZO
[RBFUNC.1]
Figure 13-1 Buzzer Driver
Jan. 2001
Preliminary
45
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which generates the result via successive approximation.
The analog reference voltage is selected to VDD or AVref
by setting of the bit AVREFS in RBFUNC register. If external analog reference AVref is selected, the bit ANSEL0
should not be set to “1”, because this pin is used to an analog reference of A/D converter.
The A/D module has two registers which are the control
register ADCM and A/D result register ADCR. The
ADCM register, shown in Figure 14-2 , controls the operation of the A/D converter module. The port pins can be
configure as analog inputs or digital I/O.
To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in RAFUNC register.
And selected the corresponding channel to be converted by
setting ADS[2:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 10
uS (at fxin=8 MHz).
y
r
a
ADS[2:0]
in
111
RA7/AN7
ANSEL7
110
RA6/AN6
ANSEL6
101
RA5/AN5
ANSEL5
e
r
100
RA4/AN4
ANSEL4
P
il m
ANSEL3
ADCR(8-bit)
ADDRESS : EBH
RESET VALUE : Undefined
Sample & Hold
S/H
Successive
Approximation
Circuit
011
RA3/AN3
A/D Result Register
A D IF
A/D Interrupt
010
RA2/AN2
ANSEL2
001
RA1/AN1
Resistor
Ladder
Circuit
ANSEL1
000
RB0/AN0/AVref
ANSEL0 (RAFUNC.0)
1
VDD Pin
0
ADEN
AVREFS (RBFUNC.0)
Figure 14-1 A/D Converter Block Diagram
46
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
A/D Control Register
-
ADCM
-
ADEN
ADS2
ADS1
ADS0
ADST
ADDRESS : EAH
RESET VALUE : --000001
ADSF
Reserved
A/D Status bit
0 : A/D Conversion is in process
1 : A/D Conversion is completed
Analog Channel Select
000 : Channel 0 (RB0/AN0)
001 : Channel 1 (RA1/AN1)
010 : Channel 2 (RA2/AN2)
011 : Channel 3 (RA3/AN3)
100 : Channel 4 (RA4/AN4)
101 : Channel 5 (RA5/AN5)
110 : Channel 6 (RA6/AN6)
111 : Channel 7 (RA7/AN7)
A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
A/D Enable bit
1 : A/D Conversion is enable
0 : A/D Converter module shut off
and consumes no operation current
A/D Result Data Register
ADCR7
ADCR
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
y
r
a
ADCR1
ADCR0
ADDRESS : EBH
RESET VALUE : Undefined
in
Figure 14-2 A/D Converter Registers
il m
A/D Converter Cautions
(1) Input range of AN0 to AN7
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
P
e
r
The input voltage of AN0 to AN7 should be within the
specification range. In particular, if a voltage above VDD
(or AVref) or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not
be indeterminate. The conversion values of the other channels
may also be affected.
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to
noise on pins AVref(or VDD)and AN0 to AN7. Since the effect
A/D START (ADST = 1)
increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-4 in order to reduce
noise.
NOP
ADSF = 1
Analog
Input
NO
AN0~AN7
100~1000pF
YES
READ ADCR
Figure 14-3 A/D Converter Operation Flow
Jan. 2001
Figure 14-4 Analog Input Pin Connecting Capacitor
Preliminary
47
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7
The analog input pins AN0 to AN7 also function as input/
output port (PORT RA and RB0) pins. When A/D conversion is performed with any of pins AN0 to AN7 selected,
be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion
resolution.
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
(4) AVref pin input impedance
A series resistor string of approximately 10KΩ is connected between the AVref pin and the VSS pin.
Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
series resistor string between the AVref pin and the VSS pin, and
there will be a large reference voltage error.
y
r
a
in
P
48
e
r
il m
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
15. INTERRUPTS
The External Interrupts INT0 and INT1 can each be transition-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
by the hardware when the service routine is vectored to
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to “0”). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
y
r
a
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Internal bus line
IENH
IRQH
External Int. 0
INT0IF
IEDS
External Int. 1
INT1IF
Timer 0
T0IF
Timer 1
T1IF
A/D Converter
ADIF
WDT
7
6
5
4
P
WDTIF
BIT
BITIF
IRQL
7
e
r
in
Interrupt Enable
Register (Higher byte)
il m
6
5
IENL
Release STOP
To CPU
Priority Control
The HMS87C1304A and HMS87C1302A interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge
Selection Register (IEDS), priority circuit and Master enable flag(“I” flag of PSW). The configuration of interrupt
circuit is shown in Figure 15-1 and Interrupt priority is
shown in Table 15-1 .
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 15-1 Block Diagram of Interrupt Function
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Jan. 2001
Interrupt enable registers are shown in Figure 15-2 . These
registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
Preliminary
49
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Reset/Interrupt
Symbol
Priority
Vector Addr.
Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
A/D Converter
Watch Dog Timer
Basic Interval Timer
RESET
INT0
INT1
Timer 0
Timer 1
A/D C
WDT
BIT
1
2
3
4
5
6
7
FFFEH
FFFAH
FFF8H
FFF6H
FFF4H
FFEAH
FFE8H
FFE6H
Table 15-1 Interrupt Priority
Interrupt Enable Register High
IENH
INT0E
INT1E
T0E
T1E
-
-
-
-
-
-
-
-
ry
Interrupt Enable Register Low
IENL
ADE
WDTE
BITE
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
Interrupt Request Register High
IRQH
INT0IF
INT1IF
T0IF
Interrupt Request Register Low
IRQL
ADIF
WDTIF
P
BITIF
T1IF
e
r
-
a
n
i
0 : Disable
1 : Enable
il m
ADDRESS : E2H
RESET VALUE : 0000----
-
ADDRESS : E3H
RESET VALUE : 000-----
-
-
-
-
ADDRESS : E4H
RESET VALUE : 0000----
-
-
-
-
ADDRESS : E5H
RESET VALUE : 000-----
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and disable any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and
written.
15.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 f OSC (2
50
µs at fXIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
[RETI].
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
e
r
V.L.
in
Internal Read
Internal Write
y
r
a
V.L.
il m
Interrupt Processing Step
ADL
V.H.
ADH
New PC
OP code
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
P
Figure 15-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
0FFE6H
0FFE7H
012H
0E3H
be set to “1” by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
Entry Address
0E312H
0E313H
Saving/Restoring General-purpose Register
0EH
2EH
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to
“1” even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
area for saving registers.
The following method is used to save/restore the generalpurpose registers.
When nested interrupt service is required, the I-flag should
Jan. 2001
Preliminary
51
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Example: Register save using push and pop instructions
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
main task
acceptance of
interrupt
interrupt
service task
saving
registers
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
restoring
registers
interrupt return
General-purpose register save/restore using push and pop
instructions;
15.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.
15.3 Multi Interrupt
P
e
r
52
i
il m
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence determines by hardware which request is serviced.
a
n
BRK or
TCALL0
Each processing step is determined by B-flag as shown in
Figure 15-4 .
ry
B-FLAG
=0
=1
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
Figure 15-4 Execution of BRK/TCALL0
However, multiple processing through software for special
features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
Main Program
service
HMS87C1304A/HMS87C1302A
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
TIMER 1
service
enable INT0
disable other
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
INT0
service
EI
Occur
TIMER1 interrupt
Occur
INT0
:
:
:
LDM
LDM
POP
POP
POP
RETI
enable INT0
enable other
P
Jan. 2001
e
r
;Enable INT0 only
;Disable other
;Enable Interrupt
IENH,#0F0H ;Enable all interrupts
IENL,#0E0H
Y
X
A
y
r
a
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Figure 15-5 Execution of Multi Interrupt
A
X
Y
IENH,#80H
IENL,#0
in
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Preliminary
53
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
15.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6H) as shown in Figure 15-6 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0 pin
INT0 INTERRUPT
INT1IF
edge selection
INT1 pin
INT0IF
INT1 INTERRUPT
Example: To use as an INT0 and INT1
:
:
;**** Set port as an input port RB2
LDM
RBIO,#1111_1011B
;
;**** Set port as an interrupt port
LDM
RBFUNC,#04H
;
;**** Set Falling-edge Detection
LDM
IEDS,#0000_0001B
:
:
:
Response Time
y
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IEDS
[0E6H]
Figure 15-6 External Interrupt Block Diagram
Ext. Interrupt Edge Selection
Register
W
W W
W
W
W
W
INT1 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
P
shows interrupt response timings.
INT0 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
max. 12 fOSC
Interrupt Interrupt
goes
latched
active
e
r
W
in
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ADDRESS : 0E6H
RESET VALUE : 00000000
IEDS
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
8 fOSC
Interrupt
processing
Interrupt
routine
Figure 15-7 Interrupt Response Timing Diagram
54
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
16. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or
other causes and return the operation to the normal condition.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by entering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
WDT interrupt or reset the CPU in accordance with the bit
WDTON.
Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to “1”, maximum error of timer is depend on
prescaler ratio of Basic Interval Timer.
Clock Control Register
-
CKCTLR
WAKEUP RCWDT
Watchdog Timer Register
P
0
X
WDTCL
WDTR
e
r
WDTON
1
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
:
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH
WDTR,#0FFH
; enable the RC-osc WDT
; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The RC oscillation period is vary with temperature, V DD
and process variations from part to part (approximately,
40~120uS). The following equation shows the RC oscillated watchdog timer time-out.
T R C W D T = C L K R C ×28×[W D T R .6~ 0]+ (C L K R C ×28)/2
y
r
a
w here, C LK R C = 40~ 120uS
In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
in
il m
TWDT = [WDTR.6~0] × Interval of BIT
BTCL
BTS2
BTS1
BTS0
X
X
X
X
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
ADDRESS : EDH
RESET VALUE : 01111111
Bit Manipulation Not Available
7-bit Watchdog Counter Register
WAKEUP
RCWDT
STOP
BTS[2:0]
fxin
÷8
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
WDTR (8-bit)
3
BTCL
WDTCL
WDTON
Clear
8
MUX
Internal RC OSC
0
1
BITR (8-bit)
7-bit Counter
CPU RESET
OFD
1
0
Overflow Detection
BITIF
Basic Interval Timer
Interrupt
Watchdog Timer
Interrupt Request
Figure 16-1 Block Diagram of Watchdog Timer
Jan. 2001
Preliminary
55
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
17. Power Saving Mode
For applications where power consumption is a critical
factor, device provides three kinds of power saving functions, STOP mode, Wake-up Timer mode and internal RCoscillated watchdog timer mode.
The power saving function is activated by execution of
STOP instruction after setting the corresponding bit
(WAKEUP, RCWDT) of CKCTLR.
Note: Before executing STOP instruction, clear all interrupt request flag. Because if the interrupt request flag is set before STOP instruction, the MCU
runs as if it doesn’t perform STOP instruction, even
though the STOP instruction is completed. So insert
two lines to clear all interrupt request flags (IRQH,
IRQL) before STOP instruction as shown each example.
Table 17-1 shows the status of each Power Saving Mode
Peripheral
STOP
Wake-up Timer
Internal RC-WDT
RAM
Retain
Retain
Retain
Control Registers
Retain
Retain
Retain
I/O Ports
Retain
Retain
Retain
CPU
Stop
Stop
Stop
Timer0
Stop
Operation
Stop
Oscillation
Stop
Oscillation
Stop
Prescaler
Stop
÷ 2048 only
Stop
Internal RC oscillator
Stop
Stop
Oscillation
Entering Condition
CKCTLR[6,5]
00
1X
01
Power Saving Release
Source
RESET, INT0, INT1
e
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in
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RESET, INT0, INT1,
Timer0
RESET, INT0, INT1,
RC-WDT
Table 17-1 Power Saving Mode
17.1 Stop Mode
P
In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port direction registers. Oscillator stops and the systems internal
operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
to ensure that VDD is not reduced before the Stop mode is
invoked, and that VDD is restored to its normal operating
level, before the Stop mode is terminated.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP
instruction should be written
• The program counter stop the address of the
instruction to be executed after the instruction
“STOP” which starts the STOP operating mode.
The Stop mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT
of CKCTLR to “00”. (This register should be written
by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be undesired operation)
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however,
56
Ex)
LDM CKCTLR,#0000_1110B
LDM IRQH,#0
LDM IRQL,#0
STOP
NOP
NOP
In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (VDD/VSS), however, when the input level gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
To minimize the current consumption during Stop mode,
the user should turn-off output drivers that are sourcing or
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should be
either as VSS or at VDD (or as close to rail as possible).
An intermediate voltage on an input pin causes the input
buffer to draw a significant amount of current.
Release the STOP mode
The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their values.
STOP
INSTRUCTION
STOP Mode
Interrupt Request
After releasing STOP mode, instruction execution is divided into two ways by I-flag(bit2 of PSW).
If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to )
When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal operation. shows the timing diagram. When release the Stop
mode, the Basic interval timer is activated on wake-up. It
is increased from 00H until FFH. The count overflow is set
to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to
have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.
P
By reset, exit from Stop mode is shown in .
e
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Corresponding Interrupt
Enable Bit (IENH, IENL)
il m
=1
a
n
i
=0
IEXX
STOP Mode Release
Master Interrupt
Enable Bit PSW[2]
I-FLAG
=0
=1
Interrupt Service Routine
Next
INSTRUCTION
Figure 17-1 STOP Releasing Flow by Interrupts
Minimizing Current Consumption in Stop Mode
The Stop mode is designed to reduce power consumption.
~
~
~
~
Internal
Clock
~
~
External
Interrupt
~
~
STOP Instruction Execution
Clear Basic Interval Timer
~
~
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
01
~
~
BIT
Counter
~
~
~
~ ~
~
Oscillator
(XIN pin)
Normal Operation
STOP Mode
Stabilization Time
tST > 20mS
Normal Operation
Figure 17-2 Timing of STOP Mode Release by External Interrupt
Jan. 2001
Preliminary
57
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
STOP Mode
~
~
~~
~ ~
~
~
Oscillator
(XIN pin)
~
~
~ ~
~
~
Internal
Clock
RESET
~
~
Internal
RESET
~
~
STOP Instruction Execution
Stabilization Time
tST = 64mS @4MHz
Time can not be controlled by software
Figure 17-3 Timing of STOP Mode Release by RESET
17.2 Wake-up Timer Mode
In the Wake-up Timer mode, the on-chip oscillator is not
stopped. Except the Prescaler (only 2048 divided ratio) and
Timer0, all functions are stopped, but the on-chip RAM
and Control registers are held. The port pins out the values
held by their respective port data register, port direction
registers.
In addition, the clock source of timer0 should be selected to 2048 divided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as
16-bit timer with timer1 (refer to timer function). The
period of wake-up function is varied by setting the timer data register 0, TDR0.
The Wake-up Timer mode is activated by execution of
STOP instruction after setting the bit WAKEUP of
CKCTLR to “1”. (This register should be written by
byte operation. If this register is set by bit manipulation
instruction, for example “set1” or “clr1” instruction, it
may be undesired operation)
Release the Wake-up Timer mode
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex) LDM TDR0,#0FFH
LDM TM0,#0001_1011B
LDM CKCTLR,#0100_1110B
LDM IRQH,#0
LDM IRQL,#0
STOP
NOP
NOP
If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vector to interrupt service routine (refer to ).
P
in
The exit from Wake-up Timer mode is hardware reset,
Timer0 overflow or external interrupt. Reset re-defines all
the Control registers but does not change the on-chip
RAM. External interrupts and Timer0 overflow allow both
on-chip RAM and Control registers to retain their values.
il m
When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is
not required to normal operation. Because this mode do not
stop the on-chip oscillator shown as .
~
~
~
~ ~
~
Oscillator
(XIN pin)
CPU
Clock
STOP Instruction
Execution
~
~
Interrupt
Request
e
r
y
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a
Normal Operation
Wake-up Timer Mode
(stop the CPU clock)
Normal Operation
Do not need Stabilization Time
Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt
58
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
17.3 Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction registers.
The Internal RC-Oscillated Watchdog Timer mode is
activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to
“01”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example “set1” or “clr1” instruction, it may be
undesired operation)
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex)
LDM
LDM
LDM
LDM
STOP
NOP
NOP
If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine (refer to ).
When exit from Internal RC-Oscillated Watchdog Timer
mode by external interrupt, the oscillation stabilization
time is required for normal operation. shows the timing diagram. When release the Internal RC-Oscillated Watchdog
Timer mode, the basic interval timer is activated on wakeup. It is increased from 00H until FFH. The count overflow
is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio
to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized.
The exit from Internal RC-Oscillated Watchdog Timer
mode is hardware reset or external interrupt. Reset re-de-
By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in .
~
~
e
r
in
il m
Release the Internal RC-Oscillated Watchdog Timer mode
~
~
~
~
P
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to “0” and
the bit WDTE of IENH is set to “1”, the device will execute the watchdog timer interrupt service routine.() However, if the bit WDTON of CKCTLR is set to “1”, the
device will generate the internal RESET signal and execute the reset processing. ()
y
r
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WDTR,#1111_1111B
CKCTLR,#0010_1110B
IRQH,#0
IRQL,#0
Oscillator
(XIN pin)
fines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.
Internal
RC Clock
~
~
~
~
Internal
Clock
~
~
External
Interrupt
(or WDT Interrupt)
~
~
STOP Instruction Execution
~
~
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~
~
BIT
Counter
Clear Basic Interval Timer
Normal Operation
RCWDT Mode
Stabilization Time
tST > 20mS
Normal Operation
Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt
Jan. 2001
Preliminary
59
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
RCWDT Mode
~
~
~
~
~
~
Oscillator
(XIN pin)
Internal
RC Clock
~
~
~
~
Internal
Clock
~
~
~
~
RESET
RESET by WDT
~
~
Internal
RESET
~
~
STOP Instruction Execution
Stabilization Time
tST = 64mS @4MHz
Time can not be controlled by software
Figure 17-6 Internal RCWDT Mode Releasing by RESET.
ry
INPUT PIN
a
n
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i
O
i
GND
VDD
X
e
r
il m
VDD
OPEN
i=0
O
i
Very weak current flows
X
i=0
OPEN
Weak pull-up current flows
P
GND
O
O
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 17-7 Application Example of Unused Input Por
t
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
X
ON
O
OFF
i
VDD
GND
L
OFF
ON
i
GND
ON
OFF
VDD
L
X
i=0
GND
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
O
In the left case, much current flows from port to GND.
Figure 17-8 Application Example of Unused input Port
60
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
18. RESET
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, while the
oscillator running. After reset, 64ms (at 4 MHz) add with
7 oscillator periods are required to start execution as shown
in Figure 18-1 .
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
Initial state of each register is shown as Table 8-1 .
1
?
?
4
5
6
7
~
~
?
?
~
~ ~
~
?
?
?
FFFE FFFF Start
ry
?
~
~
DATA
BUS
3
~
~
RESET
ADDRESS
BUS
2
~
~
Oscillator
(XIN pin)
a
n
FE
ADL
ADH
OP
MAIN PROGRAM
Stabilizing Time
tST = 64mS at 4MHz
RESET Process Step
i
Figure 18-1 Timing Diagram after RESET
P
Jan. 2001
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Preliminary
61
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
19. POWER FAIL PROCESSOR
The HMS87C1304A and HMS87C1302A has an on-chip
power fail detection circuitry to immunize against power
noise. A configuration register, PFDR, can enable (if clear/
programmed) or disable (if set) the Power-fail Detect circuitry. If VDD falls below 2.5~3.5V(2.0~3.0V) range for
longer than 50 nS, the Power fail situation may reset MCU
according to PFS bit of PFDR. And power fail detect level
is selectable by mask option. On the other hand, in the
OTP, power fail detect level is decided by setting the bit
PFDLEVEL of CONFIG register when program the OTP.
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note: Power fail detect level is decided by mask option
checking the bit PFDLEVEL of MASK ORDER
SHEET (refer to MASK ORDER SHEET)
In thc case of OTP, Power fail detect level is decided by setting the bit PFDLEVEL of CONFIG register
(refer to Figure 20-1 .
As below PFDR register is not implemented on the in-cir-
Power Fail Detector Register
PFDR
-
-
-
-
-
PFDIS
PFDM
ADDRESS : EFH
RESET VALUE : -----100
PFS
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Reserved
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
in
e
r
Disable Flag
0 : Power fail detection enable
il m
1 : Power fail detection disable
Figure 19-1 Power Fail Detector Register
P
RESET VECTOR
PFS =1
YES
NO
RAM CLEAR
INITIALIZE RAM DATA
Skip the
initial routine
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
Figure 19-2 Example S/W of RESET by Power fail
62
Preliminary
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HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
VDD
PFVDDMAX
PFVDDMIN
64mS
Internal
RESET
VDD
When PFDM = 1
64mS
Internal
RESET
PFVDDMAX
PFVDDMIN
t < 64mS
VDD
PFVDDMAX
PFVDDMIN
64mS
Internal
RESET
ry
VDD
System
Clock
a
n
i
When PFDM = 0
VDD
System
Clock
P
e
r
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PFVDDMAX
PFVDDMIN
PFVDDMAX
PFVDDMIN
Figure 19-3 Power Fail Processor Situations
Jan. 2001
Preliminary
63
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
20. DEVICE CONFIGURATION AREA
The Device Configuration Area can be programmed or left
unprogrammed to select device configuration such as security bit.
Customer ID recording locations where the user can store
check-sum or other customer identification numbers.
This area is not accessible during normal execution but is
readable and writable during program / verify.
Ten memory locations (0F50H ~ 0FE0H) are designated as
0F50H
DEVICE
CONFIGURATION
AREA
0FF0H
ID
0F50H
ID
0F60H
ID
0F70H
ID
0F80H
ID
0F90H
ID
0FA0H
ID
0FB0H
ID
0FC0H
ID
0FD0H
ID
0FE0H
CONFIG
0FF0H
Configuration Register
CONFIG
-
-
-
-
-
PFD
LOCK LEVEL
y
r
a
-
ADDRESS : 0FF0H
PFD Level Select
0 : PFD Level High (2.5~3.5V)
1 : PFD Level Low (2.0~3.0V)
SECURITY BIT
0 Allow Code Read Out
1 : Prohibit Code Read Out
in
Figure 20-1 Device Configuration Area
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Preliminary
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HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
A_D4
1
28
A_D3
A_D5
2
27
A_D2
A_D6
3
26
A_D1
A_D7
4
25
A_D0
5
24
CTL0
6
23
CTL1
7
22
VSS
CTL2
8
21
VPP
9
20
10
19
11
18
12
17
13
16
14
15
VDD
NC
EPROM Enable
y
r
a
in
Figure 20-2 Pin Assignment
User Mode
Pin No.
Pin Name
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EPROM MODE
Pin Name
e
r
1
RA4 (AN4)
A_D4
2
RA5 (AN5)
A_D5
3
RA6 (AN6)
P
A_D6
Description
Address Input
Data Input/Output
A4
D4
A13
A5
D5
A14
A6
D6
A15
A7
D7
4
RA7 (AN7)
5
VDD
6
RB0 (AVref/AN0)
CTL0
7
RB1 (INT0)
CTL1
8
RB2 (INT1)
CTL2
RB3~7, RC3~6, RD2
VDD
Connect to VDD (6.0V)
19
XIN
EPROM Enable
High Active, Latch Address in falling edge
20
XOUT
NC
No connection
21
RESET
VPP
Programming Power (0V, 12.75V)
22
VSS
VSS
Connect to VSS (0V)
RC0, 1
VDD
Connect to VDD (6.0V)
9~18
23, 24
A_D7
A12
VDD
Connect to VDD (6.0V)
Read/Write Control
Address/Data Control
Table 20-1 Pin Description in EPROM Mode
Jan. 2001
Preliminary
65
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
25
RA0 (EC0)
A_D0
26
RA1 (AN1)
A_D1
27
RA2 (AN2)
A_D2
28
RA3 (AN3)
A_D3
Address Input
Data Input/Output
A8
A0
D0
A9
A1
D1
A10
A2
D2
A11
A3
D3
Table 20-1 Pin Description in EPROM Mode
y
r
a
in
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HYUNDAI MicroElectronics
THLD1
TSET1
HMS87C1304A/HMS87C1302A
THLD2
TDLY1
0V
VDD1H
TCD1
0V
TCD1
~
~
TCD1
0V
TCD1
HA
LA
LA
~~
VDD1H
ry
VDD
High 8bit
Address
Input
Write Mode
Low 8bit
Address
Input
Verify
DATA
OUT
DATA IN
~
~
DATA
OUT
DATA IN
~
~
~
~
A_D7~
A_D0
~
~
VDD1H
CTL2
~
~ ~
~
CTL0
TVPPR
~ ~
~
~
TVDDS
~
~
VPP
VIHP
~
~
TVPPS
~
~
~
~
EPROM
Enable
CTL1
TDLY2
Low 8bit
Address
Input
Write Mode
Verify
a
n
i
Figure 20-3 Timing Diagram in Program (Write & Verify) Mode
il m
After input a high address,
output data following low address input
TSET1
THLD1
EPROM
Enable
P
TVPPS
VPP
TVDDS
CTL0
0V
VIHP
e
r
TDLY1
Another high address step
TVPPR
VDD2H
CTL1
0V
CTL2
0V
TCD2
VDD2H
A_D7~
A_D0
TCD1
TCD2
TCD1
HA
LA
DATA
LA
DATA
HA
LA
DATA
High 8bit
Address
Input
Low 8bit
Address
Input
DATA
Output
Low 8bit
Address
Input
DATA
Output
High 8bit
Address
Input
Low 8bit
Address
Input
DATA
Output
VDD2H
VDD
Figure 20-4 Timing Diagram in READ Mode
Jan. 2001
Preliminary
67
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Parameter
Symbol
MIN
TYP
MAX
Unit
Programming Supply Current
IVPP
-
-
50
mA
Supply Current in EPROM Mode
IVDDP
-
-
20
mA
VPP Level during Programming
VIHP
11.5
12.0
12.5
V
VDD Level in Program Mode
VDD1H
5
6
6.5
V
VDD Level in Read Mode
VDD2H
-
2.7
-
V
CTL2~0 High Level in EPROM Mode
VIHC
0.8VDD
-
-
V
CTL2~0 Low Level in EPROM Mode
VILC
-
-
0.2VDD
V
A_D7~A_D0 High Level in EPROM Mode
VIHAD
0.9VDD
-
-
V
A_D7~A_D0 Low Level in EPROM Mode
VILAD
-
-
0.1VDD
V
VDD Saturation Time
TVDDS
1
-
-
mS
VPP Setup Time
TVPPR
-
-
1
mS
VPP Saturation Time
TVPPS
1
-
-
mS
EPROM Enable Setup Time after Data Input
TSET1
nS
EPROM Enable Hold Time after TSET1
THLD1
ry
200
500
nS
200
nS
100
nS
TDLY2
200
nS
TCD1
100
nS
TCD2
100
nS
a
n
EPROM Enable Delay Time after THLD1
TDLY1
EPROM Enable Hold Time in Write Mode
i
EPROM Enable Delay Time after THLD2
CTL2,1 Setup Time after Low Address input and Data input
il m
CTL1 Setup Time before Data output in Read and Verify Mode
THLD2
Table 20-2 AC/DC Requirements for Program/Read Mode
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HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
START
Set VDD=VDD1H
Verify OK
NO
Verify blank
Report
Verify failure
Verify for all address
Report
Programming failure
Set VPP=VIHP
NO
YES
YES
Report
Programming OK
First Address Location
Next address location
VDD=Vpp=0v
Report
Programming failure
N=1
y
r
a
END
NO
YES
EPROM Write
100uS program time
Verify pass
YES
Apply 3N program cycle
NO
Last address
YES
in
NO
Verify pass
P
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Figure 20-5 Programming Flow Chart
Jan. 2001
Preliminary
69
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
START
Set VDD=VDD2H
Verify for all address
Set VPP=VIHP
First Address Location
Next address location
NO
Last address
y
r
a
YES
Report Read OK
in
VDD=0V
VPP=0V
il m
END
e
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Figure 20-6 Reading Flow Chart
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Preliminary
Jan. 2001