CX77304-15
PA Module for Dual-band GSM850 PCS1900 / GPRS Applications
The CX77304-15 Power Amplifier Module(PAM) is designed in a compact form factor
for dual-band cellular handsets comprising GSM850 and PCS1900 operation. It also
supports Class 10 General Packet Radio Service (GPRS) multislot operation.
Distinguishing Features
•
•
•
•
The module consists of separate Heterojunction Bipolar Transistor (HBT) PA blocks
for the GSM850 and PCS1900 bands, interface circuitry, and RF input and output
ports internally matched for 50 Ω impedance to reduce the number of external
components. The PA blocks are fabricated on a single Gallium Arsenide (GaAs) die •
and share common power supply pins for current distribution. Extremely low
•
leakage current (2 µA, typical) of the dual PA module maximizes handset standby
time.
•
High efficiency
GSM 55%
PCS 45%
Input/output internally matched
to 50 Ω
Small outline
9.1 mm × 11.6 mm
Low profile
1.5 mm maximum
Low APC current
10 µA, typical
Gold plated, lead-free contacts
The CX77304-15 also contains band-select switching circuitry to select GSM
(logic 0) and PCS (logic 1) as determined from the Band Select (BS) signal. In the •
block diagram shown below, the BS pin selects the PA output (PCS OUT or
Applications
GSM OUT) while the Analog Power Control (APC) controls the level of output power.
A custom CMOS IC provides the internal interface circuitry including a current
amplifier that minimizes the required power control current (IAPC) to 10 µA,
typical. The GaAs die, the Silicon (Si) die, and passive components are mounted
on a multi-layer laminate substrate and the assembly encapsulated with plastic
overmold.
•
Dual-band cellular handsets
encompassing
Class 4 GSM850
PCS1900, and
up to Class 10 GPRS multislot
operation
Functional Block Diagram
HBT
PCS IN
Power Control
Band Select
GSM IN
Match
Match
PCS OUT
Match
GSM OUT
CMOS
Bias
Controller
Match
Data Sheet
© 2001–2003 Skyworks Solutions, Inc., All Rights Reserved.
101749A
September 19, 2003
CX77304-15
Electrical Specifications
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Electrical Specifications
The following tables list the electrical characteristics of the CX77304-15 Power Amplifier. Table 1
lists the absolute maximum ratings and Table 2 shows the recommended operating conditions.
Table 3 shows the electrical characteristics of the CX77304-15 for GSM and PCS modes. A typical
CX77304-15 application diagram appears in Figure 1.
The CX77304-15 is a static-sensitive electronic device and should not be stored or operated near
strong electrostatic fields. Detailed ESD precautions along with information on device dimensions,
pin descriptions, packaging and handling can be found in later sections of this data sheet.
Table 1. Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
Input Power (PIN)
—
15
dBm
Supply Voltage (VCC), Standby, VAPC ≤0.3 V
—
7
V
Control Voltage (VAPC)
–0.5
VCCMAX – 0.2
(See Table 3)
V
Storage Temperature
–55
+100
°C
Table 2. Recommended Operating Conditions
Parameter
Minimum
Typical
Maximum
Unit
Supply Voltage (VCC)
2.8
3.2
4.6V(1)
V
Supply Current (ICC)
0
—
2.5(1)
A
Operating Case Temperature (TCASE)
1-Slot (12.5% duty cycle)
2-Slot (25% duty cycle)
3-Slot (37.5% duty cycle)
4-Slot ( 50% duty cycle)
—
°C
–20
–20
–20
–20
100
90
75
60
NOTE(S):
(1)
2
For charging conditions with VCC > 4.6 V, derate ICC linearly down to 0.5 A max at VCC = 5.5 V.
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CX77304-15
Electrical Specifications
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Table 3. CX77304-15 Electrical Specifications(1) (1 of 3)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
General
Supply voltage
VCC
—
2.8
3.2
4.6
V
Power Control Current
IAPC
—
—
10
100
µA
Leakage Current
Iq
—
—
5
µA
APC Enable Threshold
VAPCTH
200
—
600
mV
APC Enable Switching Delay
tSW
8
µs
VCC = 4.5 V
VAPC = 0.3 V
TCASE = +25 °C
PIN ≤ –60 dBm
—
Time from VAPC ≥ VAPCTH until
POUT ≤ (POUT_FINAL – 3 dB)
5
GSM Mode (f = 824 to 849 MHz and PIN = 6 to 10 dBm)
Frequency range
f
—
824
—
849
MHz
Input power
PIN
—
6
—
10
dBm
Analog power control voltage
VAPC
POUT = 32 dBm
1.2
1.7
2.1
V
Power Added Efficiency
PAE
VCC = 3.2 V
POUT ≥ 34.0 dBm
VAPC ≈ 2.0 V,
pulse width 577 µs,
duty cycle 1:8
TCASE = +25 °C
50
55
—
%
2nd to 13th harmonics
2f0 to 13f0
BW = 3 MHz
5 dBm ≤ POUT ≤ 35 dBm
—
—
–7
dBm
Output power
POUT
VCC = 3.2 V
VAPC ≈ 2.0 V
TCASE = +25 °C
34.0
34.5
—
dBm
POUTMAX LOW VOLTAGE
VCC = 2.8 V
VAPC ≤ 2.6 V
TCASE = –20 °C to +100 °C
(See Table 2 for multislot)
PIN = 6 dBm
32
33
—
dBm
POUTMAX HIGH VOLTAGE
VCC = 4.6 V
VAPC ≤ 2.6 V
TCASE = –20 °C to +100 °C
(See Table 2 for multislot)
PIN = 6 dBm
32
33
—
dBm
Input VSWR
ΓIN
POUT = 5 to 35 dBm,
controlled by VAPC
—
1.5:1
2.2:1
—
Forward isolation
POUTSTANDBY
PIN = 10 dBm
VAPC = 0.3 V
—
–35
–30
dBm
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CX77304-15
Electrical Specifications
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Table 3. CX77304-15 Electrical Specifications(1) (2 of 3)
Parameter
Spurious
Symbol
Spur
Output Power Switching Speed
Test Condition
Min
Typical
Max
Units
No parasitic oscillation with all
combinations of the following
parameters:
VAPC = controlled(2)
PIN = 10.0 dBm
VCC = 2.8 V to 4.6 V
Load VSWR = 6:1, all phase angles
—
—
–36
dBm
± step input of VAPC to RF output
power within 1 dB of final value
starting state: VAPC = 0.6 V
—
—
3 µs
dBm
Load mismatch
Load
All combinations of the following
parameters:
VAPC = controlled(2)
PIN = 10 dBm
VCC = 2.8 V to 4.6 V
Load VSWR = 10:1, all phase
angles
Noise power
PNOISE
At f0 + 20 MHz
T = 25 °C
RBW = 100 kHz
VCC = 3.2 V
PIN = 6 dBm
POUT = 34.0 dBm
—
—
–84
dBm
At f0 + 10 MHz
T = 25 °C
RBW = 100 kHz
VCC = 3.2 V
PIN = 6 dBm
POUT = 34.0 dBm
—
—
–76
dBm
At 1930 to 1990 MHz
RBW = 100 kHz
VCC = 3.2 V
POUT = 34.0 dBm
—
—
–90
dBm
No module damage or permanent
degradation
PCS Mode (f = 1850 to 1910 MHz and PIN = 6 to 10 dBm)
Frequency range
f
—
1850
—
1910
MHz
Input power
PIN
—
6
—
10
dBm
Analog power control voltage
VAPC
POUT = 29.5 dBm
1.35
1.7
2.1
V
Power Added Efficiency
PAE
VCC = 3.2 V
POUT ≥ 32 dBm
VAPC ≈ 2.0 V,
pulse width 577 µs,
duty cycle 1:8
TCASE = +25 °C
42
45
—
%
2nd to 7th harmonics
2f0 to 7f0
BW = 3 MHz
5 dBm ≤ POUT ≤ 32 dBm
—
—
–7
dBm
4
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September 19, 2003
CX77304-15
Electrical Specifications
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Table 3. CX77304-15 Electrical Specifications(1) (3 of 3)
Parameter
Output power
Symbol
Test Condition
Min
Typical
Max
Units
32
32.5
—
dBm
POUT
VCC = 3.2 V
VAPC ≈ 2.0 V
TCASE = +25 °C
POUTMAX LOW VOLTAGE
VCC = 2.8 V
VAPC ≤ 2.6 V
T = 25 °C
(See Table 2 for multislot)
PIN = 6 dBm
30.0
30.5
—
dBm
POUTMAX HIGH VOLTAGE
VCC = 2.8 V
VAPC ≤ 2.6 V
TCASE = –20 °C to +100 °C (See
Table 2 for multislot)
PIN = 6 dBm
29.0
30.5
—
dBm
Input VSWR
ΓIN
POUT = 0 to 32 dBm
controlled by VAPC
—
—
2:1
—
Forward isolation
POUTSTANDBY
PIN = 10 dBm, VAPC = 0.3 V
—
–40
–35
dBm
Switching time
τRISE, τFALL
± step input of VAPC to RF output
power within 1 dB of final value
starting state: VAPC = 0.6 V
—
—
3 µs
dBm
Spurious
Spur
No parasitic oscillation with all
combinations of the following
parameters:
VAPC = controlled(3)
PIN = 10.0 dBm
VCC = 2.8 V to 4.6 V
Load VSWR = 6:1, all phase angles
—
—
–36
dBm
Load mismatch
Load
All combinations of the following
parameters:
VAPC = controlled(3)
PIN = 10 dBm
VCC = 2.8 V to 4.6 V
Load VSWR = 10:1, all phase
angles
Noise power
PNOISE
At f0 + 20 MHz
T = +25 °C
RBW = 100 kHz
VCC = 3.2 V
POUT = 32 dBm
—
—
–77
dBm
At 869 to 894 MHz
RBW = 100 kHz
VCC = 3.2 V
POUT = 32 dBm
—
—
–84
dBm
No module damage or permanent
degradation
NOTE(S):
(1)
Unless specified otherwise: TCASE = –20 to max. operating temperature (see Table 2), RL = 50Ω, pulsed operation with pulse
width ≤ 2308 µs and duty cycle ≤ 4:8, VCC = 2.8 V to 4.6 V.
(2) ICC = 0A to xA, where x = current at POUT = 34.0 dBm, 50 Ω load, and VCC = 3.2 V.
(3) ICC = 0A to xA, where x = current at POUT = 32.0 dBm, 50 Ω load, and VCC = 3.2 V.
101749A
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5
CX77304-15
Electrical Specifications
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Figure 1. Typical CX77304-15 Application
C
V BAT
10 µF
ELECTROLYTIC
10 pF
HBT
PCS IN
APC IN
B
APC from PAC
PCS OUT
Match
2
12
14
CMOS
Bias
Controller
B
BS IN (from Baseband)
CX77304-15
16
GSM OUT
Match
33 pF
Match
4
GSM IN
10
6
VCC
10 pF
Match
C
VCC1
8
VCC2
9
100 pF A
GND
10 nF A
A Place caps at closest proximity to PA module with the
capacitor ground directly connected to the PAM grounds.
B
Optional depending on PAC circuit.
C
Common connect Vbat to all Vcc pins.
101749_003
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CX77304-15
Package Dimensions and Pin Descriptions
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Package Dimensions and Pin Descriptions
Figure 2 is a mechanical diagram of the pad layout for the 16-pin leadless CX77304-15 dual-band
PA module. Figure 3 provides a recommended phone board layout footprint for the PAM to help
the designer attain optimum thermal conductivity, good grounding, and minimum RF discontinuity
for the 50 ohm terminals.
Figure 4 shows the pin configuration and pin numbering convention, which starts with pin 1 in the
upper left, as indicated, and increments counter-clockwise around the package. Table 4 lists the pin
names and descriptions. Figure 5 interprets typical case markings.
Figure 2. CX77304-15 Package Dimensions–16-pin Module (All Views)
Pin 1
R0.381 Typ
2.286
± 0.051
R0.860 Typ
0.762 Typ
0.127 Ref
1.905
± 0.051
9.10
+0.20/
-0.08
2.286
± 0.051
0.737 ± 0.051
TOP VIEW
SIDE VIEW
3.899
± 0.051
1.905
± 0.051
1.02 Typ
BOTTOM VIEW
11.60 +0.20/-0.08
1.50 max.
FRONT VIEW
NOTE(S):
1. All contact points are gold plated, lead free-surfaces.
2. All dimensions are in millimeters.
101749_004
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CX77304-15
Package Dimensions and Pin Descriptions
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Figure 3. Phone Board Layout Footprint for 9.1 mm x 11.6 mm Package
1.42
0.86
PIN 1
1.42
PIN
16
0.86
PIN
16
PIN 1
0.3
1.8
1
9.8
3.20 9.8
5.00
Component
Outline
1.91
1.905
12.3
12.3
Component
Outline
STENCIL APERTURE
STENCIL APERTURE
TOP VIEW
APPROACH 2
TOP VIEW
APPROACH 1
Common Ground Pad
1.42
1.32
0.05 ALL AROUND
0.762
PIN 1
PIN
16
0.86
9.70
PIN 1
PIN
16
4.5
9.8
1.91 TYP
1.905 TYP
4X 0.82
7
12.3
12.20
Component
Outline
0.250
METALLIZATION
Component
Outline
SOLDER MASK OPENING
TOP VIEW
TOP VIEW
Thermal Via Array
o
/ 0.3 mm on 0.8 mm pitch
Additional vias will improve
thermal performance.
NOTE: Thermal vias should be
tented and filled with solder mask,
30–35 µm Cu plating recommended.
101749_006
8
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CX77304-15
Package Dimensions and Pin Descriptions
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
BS
GND
APC
Figure 4. CX77304-15 Pin Configuration—16-Pin Leadless Module (Top View)
16
15
14
13 GND
PCS IN
2
12 PCS OUT
GND
3
11 GND
GSM IN
4
10 GSM OUT
GND
5
7
8
9 GND
VCC
6
GND
1
VCC
GND
Table 4. CX77304-15 Signal Description
Pin
Name
Description
1
GND
Ground
2
PCS IN
RF input to PCS PA (DC coupled)
3
GND
Ground
4
GSM IN
RF input to GSM PA
5
GND
Ground
6
VCC
Power supply for PA driver stages
7
GND
Ground
8
VCC
Power supply for PA output stages
9
GND
Ground
10
GSM OUT
GSM RF output (DC coupled)
11
GND
Ground
12
PCS OUT
PCS RF output (DC coupled)
13
GND
Ground
14
APC
Analog Power Control
15
GND
Ground
16
BS
Band Select
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CX77304-15
Package Dimensions and Pin Descriptions
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Figure 5. Typical Case Markings
Mark Pin 1 Identifier
SKYWORKS
CX77304-NN
KXXXXX.XX
YYWW MEX
Manufacturing Part Number-Revision Number
Lot Number
YY = Manufacture Year
WW = Week Package Sealed
MEX = Country Code
101749_008
10
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101749A
September 19, 2003
CX77304-15
Package and Handling Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Package and Handling Information
Because of its sensitivity to moisture absorption, this device package is baked and vacuum packed
prior to shipment. Instructions on the shipping container label must be followed regarding exposure
to moisture after the container seal is broken, otherwise, problems related to moisture absorption
may occur when the part is subjected to high temperature during solder assembly.
The SKY77304-15 is capable of withstanding an MSL 3/240 °C solder reflow. Care must be taken
when attaching this product, whether it is done manually or in a production solder reflow
environment. If the part is attached in a reflow oven, the temperature ramp rate should not exceed
5 °C per second; maximum temperature should not exceed 240 °C. If the part is manually attached,
precaution should be taken to insure that the part is not subjected to temperatures exceeding 240 °C
for more than 10 seconds. For details on attachment techniques, precautions, and handling
procedures recommended by Skyworks, please refer to Application Note: PCB Design and SMT
Assembly/Rework, Document Number 101752. Additional information on standard SMT reflow
profiles can also be found in the JEDEC Standard J-STD-020B.
Production quantities of this product are shipped in the standard tape-and-reel format. For
packaging details, refer to Application Note: Tape and Reel, Document Number 101568.
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CX77304-15
Electrostatic Discharge Sensitivity
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Electrostatic Discharge Sensitivity
The CX77304-15 is a Class I device. Figure 6 lists the Electrostatic Discharge (ESD) immunity
level for each pin of the CX77304-15 product. The numbers in Figure 6 specify the ESD threshold
levels for each pin where the I-V curve between the pin and ground starts to show degradation.
The ESD testing was performed in compliance with MIL-STD-883E Method 3015.7 using the
Human Body Model. If ESD damage threshold magnitude is found to consistently exceed 2000
volts on a given pin, this so is indicated. If ESD damage threshold below 2000 volts is measured
for either polarity, numbers are indicated that represent worst case values observed in product
characterization.
Figure 6. ESD Sensitivity Areas (Top View)
GND
1
PCS IN
> +2000 V
< –2000 V
> +2000 V
< –2000 V
BS
GND
> +2000 V
< –2000 V
APC
16
15
14
13
GND
2
12
PCS OUT
> +2000 V
< –2000 V
GND
3
11
GND
GSM IN
+ 1800 V
– 1950 V
4
10
GSM OUT
> +2000 V
< –2000 V
GND
5
9
GND
6
VCC
> +2000 V
< –2000 V
7
8
GND
VCC
> +2000 V
< –2000 V
101749_007
Various failure criteria can be utilized when performing ESD testing. Many vendors employ
relaxed ESD failure standards which fail devices only after “the pin fails the electrical specification
limits” or “the pin becomes completely non-functional”. Skyworks employs most stringent criteria,
fails devices as soon as the pin begins to show any degradation on a curve tracer.
To avoid ESD damage, both latent and visible, it is very important that the product assembly and
test areas follow the Class-1 ESD handling precautions listed in Table 5.
Table 5. Precautions for Handling GaAs IC-based Products to Avoid Induced Damage
12
Personnel Grounding
Wrist Straps
Conductive Smocks, Gloves and Finger Cots
Antistatic ID Badges
Facility
Relative Humidity Control and Air Ionizers
Dissipative Floors (less than 109 Ω to GND)
Protective Workstation
Dissipative Table Tops
Protective Test Equipment (Properly Grounded)
Grounded Tip Soldering Irons
Conductive Solder Suckers
Static Sensors
Protective Packaging & Transportation
Bags and Pouches (Faraday Shield)
Protective Tote Boxes (Conductive Static Shielding)
Protective Trays
Grounded Carts
Protective Work Order Holders
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CX77304-15
Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Technical Information
CMOS Bias Controller Characteristics
The CMOS die within the PAM performs several functions that are important to the overall module
performance. Some of these functions must be considered for development of the power ramping
features in a 3GPP compliant transmitter power control loop1. Power ramping considerations will
be discussed later in this section.
The four main functions that will be described in this section are Standby Mode Control, Band
Select, Voltage Clamp, and Current Buffer. The functional block diagram is shown in Figure 7.
Figure 7. Functional Block Diagram
Band
Select
(pin16)
vodcs
APC input
(pin14)
Supply
(pin6)
cpdcs
cpgsm
vogsm
CComp
CComp
Combinational
Logic
Voltage Clamp
Bandgap
Reference
CMOS bias controller
PCS1900
bias out
Ground
Cbypass
Cbypass
GSM850
bias out
RF
Isolation
RF
Isolation
Dual Band GaAs Power Amplifier Die
101749_011
1.
Please refer to 3GPP TS 05.05, Digital Cellular Communications System (Phase 2+); Radio Transmission and Reception. All GSM
specifications are now the responsibility of 3GPP. The standards are available at http://www.3GPP.org/specs/specs.htm
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CX77304-15
Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Standby Mode Control
The Combinational Logic cell includes enable circuitry that monitors the APC ramping voltage
from the power amplifier controller (PAC) circuit in the GSM transmitter. Typical handset designs
directly connect the PA VCC to the battery at all times, and for some PA manufacturers this requires
a control signal to set the device in or out of standby mode. The Skyworks PAM does not require a
Transmit Enable input because it contains a standby detection circuit that senses the VAPC to enable
or disable the PA. This feature helps minimize battery discharge when the PA is in standby mode.
When VAPC is below the enable threshold voltage, the PA goes into a standby mode, which reduces
battery current (ICC) to 6 µA, typical, under nominal conditions.
For voltages less than 700 mV at the APC input (pin 14), the PA bias is held at ground. As the APC
input exceeds the enable threshold, the bias will activate. After an 8 µs delay, the amplifier internal
bias will ramp quickly to match the ramp voltage applied to the APC input. In order for the internal
bias to precisely follow the APC ramping voltage, it is critical that a ramp pedestal is set to the
APC input at or above the enable threshold level with a timing at least 8 µs prior to ramp-up. This
will be discussed in more detail in the following section, “Power Ramping Considerations for
3GPP Compliance”.
Band Select
The Combinational Logic cell also includes a simple gate arrangement that selects the desired
operational band by activating the appropriate current buffer. The voltage threshold level at the
Band Select input (pin 16) will determine the active path of the bias output to the GaAs die.
Voltage Clamp
The Voltage Clamp circuit will limit the maximum bias voltage output applied to the bases of the
HBT devices on the GaAs die. This provides protection against electrical overstress (EOS) of the
active devices during high voltage and/or load mismatch conditions. Figure 8 shows the typical
transfer function of the APC input to buffer output under resistively loaded conditions. Notice the
enable function near 600 mV, and the clamp acting at 2.15 V, corresponding to a supply voltage of
4.0 V.
Figure 8. Base Bias Voltage vs. APC Input, VCC = 4.0 V
2.5
Base Bias (volts)
2.0
1.5
clamping
occurs
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
APC input (volts)
101749_013a
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CX77304-15
Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Due to output impedance effects, the bias of the GaAs devices increases as the supply voltage
increases. The Voltage Clamp is designed to gradually decrease in level as the battery voltage
increases. The performance of the clamp circuit is enhanced by the band gap reference that
provides a supply-, process-, and temperature-independent reference voltage. The transfer function
relative to VBAT is shown in Figure 9. For battery voltages below 3.4 V, the base bias voltage is
limited by the common mode range of the buffer amplifier. For battery voltages above 3.4 V, the
clamp limits the base bias.
Figure 9. Base Bias Clamp Voltage vs. Supply Voltage
2.6
2.5
clamp
Base Bias Clamp (Volts)
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
3.00
3.25
3.50
3.75
4.00
4.25
4.50
Vcc (Volts)
101749_013b
Current Buffer
The output buffer amplifier performs a vital function in the CMOS device by transferring the APC
input voltage ramp to the base of the GaAs power devices. This allows the APC input to be a high
impedance port, sinking only 10 µA, typical, assuring no loading effects on the PAC circuit. The
buffers are designed to source the high GaAs base currents required, while allowing a settling time
of less than 8 µs for a 1.5 V ramp.
Power Ramping Considerations for 3GPP Compliance
These are the primary variables in the power control loop that the system designer must control:
•
•
•
•
•
software control of the DSP / DAC
software control of the transmitter timing signals
ramp profile attributes - pedestal, number of steps, duration of steps
layout of circuit / parasitics
RC time constants within the PAC circuit design
All of these variables will directly influence the ability of a GSM transmitter power control loop to
comply with 3GPP specifications.
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Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Although there is a specific time mask template in which the transmitter power is allowed to ramp
up, the method is very critical. The 3GPP system specification for switching transients results in a
requirement to limit the edge rate of output power transitions of the mobile. Switching transients
are caused by the transition from minimum output power to the desired output power, and vice
versa. The spectrum generated by this transition is due to the ramping waveform amplitude
modulation imposed on the carrier. Sharper transitions tend to produce more spectral "splatter"
than smooth transitions. If the transmit output power is ramped up too slowly, the radio will violate
the time mask specification. In this condition, the radio may not successfully initiate or maintain a
phone call. If the transmit output power is ramped up too quickly, this will cause RF "splatter" at
certain frequency offsets from the carrier as dictated by the 3GPP specification. This splatter,
known as Output RF Spectrum (ORFS) due to Switching Transients, will increase the system noise
level, which may knock out other users on the system. The main difficulty with TDMA power
control is allowing the transmitter to ramp the output power up and down gradually so switching
transients are not compromised while meeting the time mask template at all output power levels in
all operational bands. The transmitter has 28 µs to ramp up power from an off state to the desired
power level.
The GSM transmitter power control loop generally involves feedback around the GaAs PA, which
limits the bandwidth of signals that can be applied to the PA bias input. Since the PA is within the
feedback loop, its own small-signal frequency response must exhibit a bandwidth 5 to 10 times that
of the power control loop. As discussed in the previous section, the PA bias is held at ground for
inputs less than 700mV. As the APC input exceeds the enable threshold, the bias will activate. After
an 8 µs delay, the amplifier internal bias will quickly ramp to match the ramp voltage applied to the
VAPC input. Since the bias must be wide band relative to the power control loop, the ramp will
exhibit a fast edge rate. If the APC input increases beyond 1V before the 8 µs switching delay is
allowed to occur after the bias is enabled, the PA will have significant RF output as the internal bias
approaches the applied bias. During this ramp, the internal power control is running "open loop"
and the edge rates are defined by the frequency response of the PA bias rather than that of the
power control loop. This open loop condition will result in switching transients that are directly
correlated to the PA bias bandwidth.
Application of an initial APC voltage, which enables the bias at least 8 µs before the VAPC voltage
is ramped, will ensure that the internal bias of the PAM will directly follow the applied VAPC. As a
result, the power control loop will define all edge transitions rather than the PA internal bandwidth
defining the transition. Figures 10 and 11 show the relationship of the internal bias relative to the
applied APC in two cases. One case has ramping starting from ground; the other case has ramping
starting with an initial enable pedestal of 700 mV. It is evident that the pedestal level is critical to
ensure a predictable and well behaved power control loop.
To enable the CMOS driver in the PAM prior to ramp-up, a PAC output pedestal level to the APC
input of the PAM (pin 14) should be set to about 700 mV. This pedestal level should have a duration
of at least 8 µs directly prior to the start of ramp up.
Figure 12 shows typical signals and timings measured in a GSM transmitter power control loop.
This particular example is at GSM Power Level 5, Channel 62. The oscilloscope traces are
TxVCO_enable, PAC_enable, DAC Ramp, and VAPC (pin 14).
NOTE:
When the TxVCO is enabled, the pedestal becomes set at the APC input of the PAM, then
the PAC is enabled, and finally the DAC ramp begins.
The device specifications for enable threshold level and switching delay are shown in Table 3.
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CX77304-15
Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Figure 10. PAM Internal Bias Performance – No Pedestal Applied
1.6
1.4
Bias Voltage (V)
1.2
7 µs
1.0
0.8
Vapc In (V)
Internal bias (V)
Enable threshold
550 mV
0.6
0.4
0.2
0.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
Time (µs)
101749_013c
Figure 11. PAM Internal Bias Performance – Pedestal Applied
1.6
1.4
Bias Voltage (V)
1.2
1.0
Switching delay
7 µs
Vapc In (V)
0.8
Internal Bias (V)
0.6
Enable threshold
550 mV
0.4
0.2
0.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
Time (µs)
101749_013d
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Technical Information
PA Module for Dual-Band GSM850 PCS1900 / GPRS Applications
Figure 12. GSM Transmitter - Typical Ramp-up Signals
T
1
DAC Ramp
2
TxVCO_enable
VAPC Pedestal
PAC_enable
3
VAPC
4
Ch1
200 mV
Ch2
1.00 V
Ch3
1.00 V
Ch4
500 mV
BW M
10.0 µs
A
Ch2
500 mV
100956_012
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Ordering Information
Model Number
Manufacturing
Part Number
Package
Operating Temperature
CX77304-15
CX77304-15
9.1 x 11.6 x 1.5 mm
–20 °C to +100 °C
Level
Date
Description
Revision History
Revision
A
September 19, 2003
Initial Release
References
Application Note: Tape and Reel, Document Number 101568
Application Note: PCB Design and SMT Assembly/Rework, Document Number 101752
JEDEC Standard J-STD-020B
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