Active Receive Mixer 400 MHz to 1.2 GHz AD8344 APPLICATIONS 12 11 COMM EXRB 10 9 8 COMM RFCM 14 7 IFOP RFIN 15 6 IFOM 5 COMM BIAS 2 3 4 LOIN COMM 1 LOCM VPMX 16 04826-0-001 COMM 13 PWDN VPDC Broadband RF port: 400 MHz to 1.2 GHz Conversion gain: 4.5 dB Noise figure: 10.5 dB Input IP3: 24 dBm Input P1dB: 8.5 dBm LO drive: 0 dBm External control of mixer bias for low power operation Single-ended, 50 Ω RF and LO input ports Single-supply operation: 5 V @ 84 mA Power-down mode Exposed paddle LFCSP: 3 mm × 3 mm FUNCTIONAL BLOCK DIAGRAM VPLO FEATURES Figure 1. Cellular base station receivers ISM receivers Radio links RF Instrumentation GENERAL DESCRIPTION The AD8344 is a high performance, broadband active mixer. It is well suited for demanding receive-channel applications that require wide bandwidth on all ports and very low intermodulation distortion and noise figure. The AD8344 provides a typical conversion gain of 4.5 dB at 890 MHz. The integrated LO driver supports a 50 Ω input impedance with a low LO drive level, helping to minimize external component count. The single-ended 50 Ω broadband RF port allows for easy interfacing to both active devices and passive filters. The RF input accepts input signals as large as 1.7 V p-p or 8.5 dBm (re: 50 Ω) at P1dB. The open-collector differential outputs provide excellent balance and can be used with a differential filter or IF amplifier, such as the AD8369 or AD8351. These outputs may also be converted to a single-ended signal through the use of a matching network or a transformer (balun). When centered on the VPOS supply voltage, each of the differential outputs may swing 2.5 V p-p. The AD8344 is fabricated on an Analog Devices proprietary, high performance SiGe IC process. The AD8344 is available in a 16-lead LFCSP package. It operates over a −40°C to +85°C temperature range. An evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8344 TABLE OF CONTENTS Specifications..................................................................................... 3 IF Port .......................................................................................... 14 AC Performance ............................................................................... 4 LO Considerations ..................................................................... 15 Absolute Maximum Ratings............................................................ 5 Bias Resistor Selection ............................................................... 16 ESD Caution.................................................................................. 5 Conversion Gain and IF Loading............................................. 16 Pin Configuration and Function Descriptions............................. 6 Low IF Frequency Operation.................................................... 17 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 18 Circuit Description......................................................................... 13 Outline Dimensions ....................................................................... 20 AC Interfaces................................................................................... 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 6/04—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8344 SPECIFICATIONS VS = 5 V, TA = 25°C, fRF = 890 MHz, fLO = 1090 MHz, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 2.43 kΩ, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss DC Bias Level OUTPUT INTERFACE Output Impedance DC Bias Voltage Power Range LO INTERFACE LO Power Return Loss DC Bias Voltage POWER-DOWN INTERFACE PWDN Threshold PWDN Response Time PWDN Input Bias Current POWER SUPPLY Positive Supply Voltage Quiescent Current VPDC VPMX, IFOP, IFOM VPLO Total Quiescent Current Power-Down Current Conditions (Pin 15, RFIN and Pin 14, RFCM) Min 4.75 −10 9||1 VS Internally generated; port must be ac-coupled 0 10 VS − 1.6 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled VS − 1.4 0.4 0.01 −80 100 4.75 Supply current for bias cells Supply current for mixer, RBIAS = 2.43 kΩ Supply current for LO limiting amplifier 73 Device disabled Rev. 0 | Page 3 of 20 Max 10 2.6 Internally generated; port must be ac-coupled Differential impedance, f = 200 MHz Externally generated Via a 4:1 balun Typ VS 5 44 35 84 500 Unit dB V 5.25 13 +4 kΩ||pF V dBm dBm dB V V µs µs µA µA 5.25 95 V mA mA mA mA µA AD8344 AC PERFORMANCE VS = 5 V, TA = 25°C, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 2.43 kΩ, unless otherwise noted. Table 2. Parameter RF Frequency Range LO Frequency Range IF Frequency Range Conversion Gain SSB Noise Figure Input Third-Order Intercept Input Second-Order Intercept Input 1 dB Compression Point LO to IF Output Feedthrough LO to RF Input Leakage RF to IF Output Feedthrough IF/2 Spurious Conditions Min 400 470 70 High Side LO fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz fRF1 = 450 MHz, fRF2 = 451 MHz, fLO = 550 MHz, fIF = 100 MHz, each RF tone = −10 dBm fRF1 = 890 MHz, fRF2 = 891 MHz, fLO = 1090 MHz, fIF = 200 MHz, each RF tone = −10 dBm fRF1 = 450 MHz, fRF2 = 500 MHz, fLO = 550 MHz, fIF = 100 MHz fRF1 = 890 MHz, fRF2 = 940 MHz, fLO = 1090 MHz, fIF = 200 MHz fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz LO Power = 0 dBm, fRF = 890 MHz, fLO = 1090 MHz LO Power = 0 dBm, fRF = 890 MHz, fLO = 1090 MHz RF Power = −10 dBm, fRF = 890 MHz, fLO = 1090 MHz RF Power = −10 dBm, fRF = 890 MHz, fLO = 1090 MHz Rev. 0 | Page 4 of 20 Typ Max 1200 1600 400 9.25 4.5 7.75 10.5 14 Unit MHz MHz MHz dB dB dB dB dBm 24 dBm 36 51 2.5 8.5 −23 −48 −32 −66 dBm dBm dBm dBm dBc dBc dBc dBm AD8344 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VS RF Input Level LO Input Level PWDN Pin IFOP, IFOM Bias Voltage Minimum Resistor from EXRB to COMM Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V 12 dBm 12 dBm VS + 0.5 V 5.5 V 2.4 kΩ 580 mW 77°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 AD8344 12 11 10 COMM EXRB PWDN VPDC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 9 8 COMM RFCM 14 7 IFOP RFIN 15 6 IFOM 5 COMM 1 2 3 4 VPLO LOCM LOIN COMM VPMX 16 04826-0-002 COMM 13 Figure 2. 16-Lead LFCSP Table 4. Pin Function Descriptions Pin No. 1 2 3 4, 5, 8, 9, 13 6, 7 10 Mnemonic VPLO LOCM LOIN COMM IFOM, IFOP EXRB 11 12 14 15 16 PWDN VPDC RFCM RFIN VPMX Function Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V. AC Ground for Limiting LO Amplifier, AC-Coupled to Ground. LO Input. Nominal input level 0 dBm, input level range −10 dBm to +4 dBm, re: 50 Ω, ac-coupled. Device Common (DC Ground). Differential IF Outputs; Open Collectors, Each Requires DC Bias of 5.00 V (Nominal). Mixer Bias Voltage, Connect Resistor from EXRB to Ground, Typical Value of 2.43 kΩ Sets Mixer Current to Nominal Value. Minimum resistor value from EXRB to ground = 2.4 kΩ. Connect to Ground for Normal Operation. Connect pin to VS for disable mode. Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V. AC Ground for RF Input, AC-Coupled to Ground. RF Input. Must be ac-coupled. Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V. Rev. 0 | Page 6 of 20 AD8344 TYPICAL PERFORMANCE CHARACTERISTICS 12 10 IF = 70MHz IF = 100MHz IF = 200MHz IF = 400MHz 10 RF = 450MHz 9 8 7 GAIN (dB) GAIN (dB) 8 6 4 6 5 RF = 890MHz 4 3 2 04826-0-010 –2 400 500 600 700 800 900 1000 RF FREQUENCY (MHz) 1100 04826-0-011 2 0 1 0 80 1200 Figure 3. Conversion Gain vs. RF Frequency 120 160 200 240 280 IF FREQUENCY (MHz) 360 400 Figure 6. Conversion Gain vs. IF Frequency 6.0 45 NORMAL (MEAN = 4.47, STD DEV = 0.18) GAIN PERCENTAGE 5.5 40 5.0 4.5 35 4.0 30 PERCENTAGE GAIN (dB) 320 3.5 3.0 2.5 2.0 25 20 15 1.5 04826-0-022 0.5 0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 LO LEVEL (dBm) 0 1 2 3 5 0 3.6 4 7.0 VS = 4.75V VS = 5.0V VS = 5.25V 6.0 GAIN (dB) 5.5 5.0 4.5 4.0 3.5 04826-0-018 3.0 2.5 2.0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 3.8 4.0 4.2 4.4 4.6 GAIN (dB) 4.8 5.0 5.2 5.4 Figure 7. Conversion Gain Distribution, FRF = 890 MHz, FIF = 200 MHz Figure 4. Conversion Gain vs. LO Power, FRF = 890 MHz, FIF = 200 MHz 6.5 04826-0-031 10 1.0 80 Figure 5. Conversion Gain vs. Temperature, FRF = 890 MHz, FLO = 1090 MHz Rev. 0 | Page 7 of 20 AD8344 28 30 IF = 70MHz IF = 100MHz IF = 200MHz IF = 400MHz 26 28 26 20 18 16 22 20 18 16 14 RF = 450MHz 500 600 700 800 900 1000 RF FREQUENCY (MHz) 1100 04826-0-013 04826-0-012 14 12 10 400 RF = 890MHz 24 22 INPUT IP3 (dBm) INPUT IP3 (dBm) 24 12 10 1200 80 Figure 8. Input IP3 vs. RF Frequency (RF Tone Spacing = 1 MHz) 120 160 200 240 280 IF FREQUENCY (MHz) 320 360 400 Figure 11. Input IP3 vs. IF Frequency (RF Tone Spacing = 1 MHz) 25.0 35 NORMAL (MEAN = 24.023, STD DEV = 0.24) IP3 PERCENTAGE 24.5 30 24.0 25 23.0 PERCENTAGE INPUT IP3 (dBm) 23.5 22.5 22.0 21.5 20 15 10 04826-0-023 21.0 20.0 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 LO LEVEL (dBm) 0 1 2 3 5 0 23.0 4 Figure 9. Input IP3 vs. LO Power, FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz VS = 4.75V VS = 5.0V VS = 5.25V 28 26 25 24 23 22 04826-0-019 INPUT IP3 (dBm) 27 21 20 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 23.2 23.4 23.6 23.8 24.0 24.2 INPUT IP3 (dBm) 24.4 24.6 24.8 Figure 12. Input IP3 Distribution, FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz 30 29 04826-0-032 20.5 80 Figure 10. Input IP3 vs. Temperature, FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz Rev. 0 | Page 8 of 20 25.0 AD8344 50 60 58 48 56 46 52 INPUT IP2 (dBm) 44 42 40 38 36 50 48 46 44 RF = 450MHz 42 40 38 IF = 70 IF = 100 IF = 200 IF = 400 32 30 400 500 600 700 800 900 1000 RF FREQUENCY (MHz) 1100 36 04826-0-033 34 04826-0-015 INPUT IP2 (dBm) RF = 890MHz 54 34 32 30 80 1200 Figure 13. Input IP2 vs. RF Frequency (RF Tone Spacing = 50 MHz) 120 160 200 240 280 IF FREQUENCY (MHz) 320 360 400 Figure 16. Input IP2 vs. IF Frequency (RF Tone Spacing = 50 MHz) 60 35 NORMAL (MEAN = 48.96, STD DEV = 01.17) IIP2 PERCENTAGE 58 56 30 54 25 50 PERCENTAGE INPUT IP2 (dBm) 52 48 46 44 42 40 20 15 10 38 04826-0-034 36 32 30 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 LO LEVEL (dBm) 0 1 2 3 5 0 44 4 4.75V 5.0V 5.25V 50 48 46 44 04826-0-037 INPUT IP2 (dBm) 52 42 40 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 45 46 47 48 49 50 51 INPUT IP2 (dBm) 52 53 Figure 17. Input IP2 Distribution, FRF = 890 MHz, FLO = 1090 MHz (RF Tone Spacing = 50 MHz) Figure 14. Input IP2 vs. LO Power, FRF = 890 MHz, FLO = 1090 MHz (RF Tone Spacing = 50 MHz) 54 04826-0-035 34 80 Figure 15. Input IP2 vs. Temperature, FRF = 890 MHz, FLO = 1090 MHz (RF Tone Spacing = 50 MHz) Rev. 0 | Page 9 of 20 54 55 AD8344 10 12 IF = 70MHz IF = 100MHz IF = 200MHz IF = 400MHz 9 RF = 890MHz 8 7 8 INPUT P1dB (dBm) INPUT P1dB (dBm) 10 6 4 6 5 4 3 RF = 450MHz 04826-0-016 500 600 700 800 900 1000 RF FREQUENCY (MHz) 1100 1 0 80 1200 Figure 18. Input P1dB vs. RF Frequency 55 8.6 50 8.4 45 200 240 280 IF FREQUENCY (MHz) 320 360 400 NORMAL (MEAN = 8.50, STD DEV = 0.38) INPUT P1dB PERCENTAGE 40 8.2 PERCENTAGE INPUT P1dB (dBm) 60 8.8 8.0 7.8 7.6 35 30 25 20 15 04826-0-024 7.4 7.2 –8 –7 –6 –5 –4 –3 –2 –1 LO LEVEL (dBm) 0 1 2 3 VS = 4.75V VS = 5.0V VS = 5.25V 9.0 8.5 8.0 7.5 7.0 6.5 04826-0-020 6.0 5.5 5.0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 5 7.5 8.0 8.5 9.0 INPUT P1dB (dBm) 9.5 10.0 Figure 22. Input P1dB Distribution, FRF = 890 MHz, FLO = 1090 MHz 10.0 9.5 10 0 7.0 4 Figure 19. Input P1dB vs. LO Power, FRF = 890 MHz, FLO = 1090 MHz INPUT P1dB (dBm) 160 Figure 21. Input P1dB vs. IF Frequency 9.0 7.0 –10 –9 120 04826-0-036 0 400 04826-0-017 2 2 80 Figure 20. Input P1dB vs. Temperature, FRF = 890 MHz, FLO = 1090 MHz Rev. 0 | Page 10 of 20 AD8344 25 INPUT IP3 95 12 85 CURRENT 80 15 75 70 10 65 NOISE FIGURE 10 INPUT P1dB (dBm) SUPPLY CURRENT (mA) 90 20 8 6 4 2 04826-0-026 60 5 55 0 2.4 2.6 2.8 3.0 3.2 3.4 RBIAS (kΩ) 3.6 50 4.0 3.8 04826-0-025 NF AND IP3 (dBm) 14 100 0 –2 2.4 Figure 23. Noise Figure, Input IP3 and Supply Current vs. RBIAS, FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz 2.6 2.8 3.0 3.2 3.4 RBIAS (kΩ) 3.6 3.8 4.0 Figure 26. Input P1dB vs. RBIAS, FRF = 890 MHz, FLO = 1090 MHz 14 11.0 10.5 13 890MHz NOISE FIGURE SSB (dBm) 12 11 10 9 8 500 600 700 800 900 RF FREQUENCY (MHz) 1000 1100 8.5 8.0 7.5 6.5 6.0 70 1200 100 150 200 250 300 IF FREQUENCY (MHz) 350 400 Figure 27. Noise Figure vs. IF Frequency 100 13.0 95 VS = 4.75V VS = 5.0V VS = 5.25V 90 12.5 CURRENT (mA) NOISE FIGURE SSB (dBm) Figure 24. Noise Figure vs. RF Frequency 13.5 12.0 11.5 11.0 85 80 75 70 04826-0-029 10.5 10.0 –15 450MHz –13 –11 –9 –7 –5 –3 LO POWER (dBm) –1 1 3 5 Figure 25. Noise Figure vs. LO Power, FRF = 890 MHz, FLO = 1090 MHz 04826-0-021 6 400 9.0 04826-0-028 7 9.5 7.0 IF = 70 IF = 100 IF = 200 IF = 400 04826-0-027 NOISE FIGURE SSB (dBm) 10.0 65 60 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 Figure 28. Total Supply Current vs. Temperature Rev. 0 | Page 11 of 20 70 80 AD8344 90 90 60 120 60 120 150 150 30 30 1.6GHz 400MHz 180 0 180 0 400MHz 300 270 240 Figure 32. LOIN Return Loss vs. LO Frequency 0 0 –5 –5 –10 –10 FEEDTHROUGH (dBc) –15 –20 –25 –30 –15 –20 –25 –30 04826-0-053 –35 –40 500 600 700 800 900 1000 RF FREQUENCY (MHz) 1100 04826-0-054 FEEDTHROUGH (dBc) 300 270 Figure 29. RFIN Return Loss vs. RF Frequency –45 400 330 210 04826-0-051 240 330 04826-0-052 1.2GHz 210 –35 –40 400 1200 600 800 1000 1200 LO FREQUENCY (MHz) 1400 1600 Figure 33. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm Figure 30. RF to IF Feedthrough vs. RF Frequency, FLO = 1090 MHz, RF Power = −10 dBm 0 14000 3.0 12000 2.5 10000 2.0 8000 1.5 6000 1.0 4000 0.5 –10 –30 –40 –50 CAPACITANCE (pF) RESISTANCE (Ω) LEAKAGE (dBc) –20 –70 –80 400 600 800 1000 1200 LO FREQUENCY (MHz) 1400 2000 70 1600 Figure 31. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm 0 120 170 220 270 FREQUENCY (MHz) 320 370 Figure 34. IF Port Output Resistance and Capacitance vs. IF Frequency Rev. 0 | Page 12 of 20 04826-0-030 04826-0-055 –60 AD8344 CIRCUIT DESCRIPTION The AD8344 also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts down the AD8344. Power consumption when the part is disabled is less than 10 mW. VPMX RFIN RFCM EXTERNAL BIAS RESISTOR PWDN BIAS IFOP SE TO DIFF IFOM LO INPUT VPLO Figure 35. AD8344 Simplified Schematic As shown in Figure 36, the IF output pins, IFOP and IFOM, are directly connected to the open collectors of the NPN transistors in the mixer core so the differential and single-ended impedances looking into this port are relatively high, on the order of several kΩ. A connection between the supply voltage and these output pins is required for proper mixer core operation. IFOP IFOM LOIN RFIN RFCM COMM 04826-0-003 The RF voltage to RF current conversion is done via an inductively degenerated differential pair. When one side of the differential pair is ac grounded, the other input can be driven single-ended. The RF inputs can also be driven differentially. The voltage-to-current converter then drives the emitters of a four-transistor switching core. This switching core is driven by an amplified version of the local oscillator signal connected to the LO input. There are three limiting gain stages between the external LO signal and the switching core. The first stage converts the single-ended LO drive to a well balanced differential drive. The differential drive then passes through two more gain stages, which ensures a limited signal drives the switching core. This affords the user a lower LO drive requirement, while maintaining excellent distortion and compression performance. The output signal of these three LO gain stages drives the four transistors within the mixer core to commutate at the rate of the local oscillator frequency. The output of the mixer core is taken directly from these open collectors. The open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 200 Ω load was presented to the part via a 4:1 impedance transformer. VPDC 04826-0-003 The AD8344 is a down converting mixer optimized for operation within the input frequency range of 400 MHz to 1.2 GHz. It has a single-ended, 50 Ω RF input, as well as a single-ended, 50 Ω local oscillator (LO) input. The IF outputs are differential open collectors. The mixer current can be adjusted by the value of an external resistor to optimize performance for gain compression and intermodulation or for low power operation. Figure 35 shows the basic blocks of the mixer, which includes the LO buffer, RF voltage-to-current converter, bias cell, and mixing core. Figure 36. Mixer Core Simplified Schematic The AD8344 has three pins for the supply voltage: VPDC, VPMX, and VPLO. These pins are separated to minimize or eliminate possible parasitic coupling paths within the AD8344 that could cause spurious signals or reduced interport isolation. Consequently, each of these pins should be well bypassed and decoupled as close to the AD8344 as possible. The bias for the mixer is set with an external resistor from the EXRB pin to ground. The value of this resistor directly affects the dynamic range of the mixer. The external resistor should not be lower than 2.4 kΩ. Permanent damage to the part will result if values below 2.4 kΩ are used. Rev. 0 | Page 13 of 20 AD8344 90 AC INTERFACES The AD8344 is designed to operate using RF frequencies in the 400 MHz to 1200 MHz frequency range, with high-side LO injection within the 470 MHz to 1600 MHz range. It is essential to ac-couple RF and LO ports to prevent dc offsets from skewing the mixer core in an asymmetrical manner, potentially degrading linear input swing and impacting distortion and input compression characteristics. The AD8344 RFIN port presents a 50 Ω impedance relative to RFCM. In order to ensure a good impedance match, the RFIN ac-coupling capacitor should be large enough in value so that the presented reactance is negligible at the intended RF frequency. Additionally, the RFCM bypassing capacitor should be sufficiently large to provide a low impedance return path to board ground. Low inductance ceramic grade capacitors of no more than 330 pF are sufficient for most applications. Similarly the LOIN port provides a 50 Ω load impedance with common-mode decoupling on LOCM. Again, common grade ceramic capacitors will provide sufficient signal coupling and bypassing of the LO interface. 60 120 150 30 10MHz 180 0 210 330 500MHz 240 300 270 04826-0-040 The AD8344 is a high-side downconverter. It is designed to downconvert radio frequencies (RF) to lower intermediate frequencies (IF) using a high-side local oscillator (LO). The LO is injected into the mixer core at a frequency greater than the desired input RF frequency. The difference between the LO and RF frequencies, fLO − fRF, is the IF frequency, fIF. In addition to the desired RF signal, an RF image will be downconverted to the same IF frequency. The image frequency is at fLO + fIF. The conversion gain of the AD8344 decreases with increasing input frequency. By choosing to use a high-side LO the image frequency at fLO + fIF is translated with less conversion gain than the desired RF signal at fLO − fIF. Additionally, any wideband noise present at the image frequency will be downconverted with less conversion gain than would be the case if a low-side LO was applied. In general, a high-side LO should be used with the AD8344 to ensure optimal noise performance and image rejection. Figure 37. IF Port Reflection Coefficient from 10 MHz to 500 MHz IF PORT The IF port uses an open collector differential output interface. The NPN open collectors can be modeled as high impedance current sources. The stray capacitance associated with the IC package presents a slightly capacitive source impedance as in Figure 37. In general, the IFOP and IFOM output ports can be modeled as current sources with an impedance of ~10 kΩ in parallel with ~1 pF of shunt capacitance. Circuit board traces connecting the IF outputs to the load should be narrow and short to prevent excessive capacitive loading. In order to maintain the specified conversion gain of the mixer, the IF output ports should be loaded into 200 Ω. It is not necessary to attempt to provide a conjugate match to the IF port output source impedance. If the IF signal needs to be delivered to a remote load, more than a few centimeters away, it may be necessary to use an appropriate buffer amplifier to present a real 200 Ω loading impedance at the IF output interface. The buffer amplifier should have the appropriate source impedance to match the characteristic impedance of the selected transmission line. An example is provided in Figure 38, where the AD8351 differential amplifier is used to drive a pair of 75 Ω transmission lines. The gain of the buffer can be independently set by choosing an appropriate gain resistor, RG. +VS AD8344 +VS COMM 8 RFC IFOP 7 200Ω RG IFOM 6 + AD8351 – Tx LINE ZO = 75Ω ZL Tx LINE ZO = 75Ω +VS ZL = 200Ω 04826-0-041 RFC COMM 5 Figure 38. AD8351 Used as Transmission Line Driver and Impedance Buffer Rev. 0 | Page 14 of 20 AD8344 90 The high input impedance of the AD8351 allows for a shunt differential termination to provide the desired 200 Ω load to the AD8344 IF output port. • Chris Bowick, RF Circuit Design, Newnes, Reprint Edition, 1997. • David M. Pozar, Microwave Engineering, Wiley Text Books, Second Edition, 1997. • Guillermo Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, Prentice Hall, Second Edition, 1996. +VS AD8344 COMM 8 4:1 IFOP 7 IF OUT ZO = 50Ω COMM 5 ZL = 200Ω 04826-0-042 IFOM 6 Figure 39. Biasing the IF Port Open Collector Outputs Using a Center-Tapped Impedance Transformer 150 30 50MHz REAL CHOKES 180 0 50MHz 500MHz 210 IDEAL CHOKES 330 500MHz 240 300 04826-0-044 It is necessary to bias the open collector outputs using one of the schemes presented in Figure 39 and Figure 40. Figure 39 illustrates the application of a center-tapped impedance transformer. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 Ω load impedance, a 4-to-1 impedance ratio transformer should be used to transform the 50 Ω load into a 200 Ω differential load at the IF output pins. Figure 40 illustrates a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF frequency of operation as to not load down the output current before reaching the intended load. Additionally, the dc current handling capability of the selected choke inductors needs to be at least 45 mA. The self resonant frequency of the selected choke should be higher than the intended IF frequency. A variety of suitable choke inductors are commercially available from manufacturers such as Murata and Coilcraft. An impedance transforming network may be required to transform the final load impedance to 200 Ω at the IF outputs. There are several good reference books that explain general impedance matching procedures, including: 60 120 270 Figure 41. IF Port Loading Effects due to Finite-Q Pull-Up Inductors (Murata BLM18HD601SN1D Chokes) LO CONSIDERATIONS The LO signal needs to have adequate phase noise characteristics and reasonable low second harmonic content to prevent degradation of the noise figure performance of the AD8344. A LO plagued with poor phase noise can result in reciprocal mixing, a mechanism that causes spectral spreading of the downconverted signal, limiting the sensitivity of the mixer at frequencies close-in to any large input signals. The internal LO buffer provides enough gain to hard limit the input LO and provide fast switching of the mixer core. Odd harmonic content present on the LO drive signal should not impact mixer performance; however, even-order harmonics cause the mixer core to commutate in an unbalanced manner, potentially degrading noise performance. Simple lumped element low-pass filtering can be applied to help reject the harmonic content of a given local oscillator, as illustrated in Figure 42. The filter depicted is a common 3-pole Chebyshev, designed to maintain a 1-to-1 source-to-load impedance ratio with no more than 0.5 dB of ripple in the pass band. Other filter structures can be effective as long as the second harmonic of the LO is filtered to negligible levels, e.g., ~30 dB below the fundamental. The measured frequency response of the Chebyshev filter for a 1200 MHz −3 dB cutoff frequency is presented in Figure 43. +VS AD8344 AD8344 LOCM LOIN COMM COMM 8 2 RS RFC 3 4 IF OUT+ IFOP 7 ZL = 200Ω IFOM 6 IMPEDANCE TRANSFORMING NETWORK L2 LO SOURCE ZL C1 C3 IF OUT– RL RFC 1.864 C1 = 2πfcRL L2 = 1.28RL 2πfc C3 = fC - FILTER CUTOFF FREQUENCY Figure 40. Biasing the IF Port Open Collector Outputs Using Pull-Up Choke Inductors 1.834 2πfcRL 04826-0-045 +VS FOR RS = RL 04826-0-043 COMM 5 Figure 42. Using a Low-Pass Filter to Reduce LO Second Harmonic Rev. 0 | Page 15 of 20 AD8344 0 125 85 124 81 123 77 IDEAL LPF –20 SFDR (dBc) RESPONSE (dB) –15 –25 –30 122 +VS 73 REAL LPF RBIAS –35 6.8nH 121 –45 4.7pF –50 0.1 04826-0-046 –40 4.7pF 1 FREQUENCY (GHz) 120 2.4 10 10 69 9 AD8344 2.6 2.8 3.0 3.2 3.4 RBIAS (kΩ) 3.6 3.8 65 4.0 Figure 44. Impact of RBIAS Resistor Selection vs. Spurious-Free Dynamic Range and Power Consumption, FRF = 890 MHz and FLO = 1090 MHz BIAS RESISTOR SELECTION An external bias resistor is used to set the dc current in the mixer core. This provides the ability to reduce power consumption at the expense of decreased dynamic range. Figure 44 shows the spurious-free dynamic range (SFDR) of the mixer for a 1 Hz noise bandwidth versus the RBIAS resistor value. SFDR was calculated using NF and IIP3 data collected at 900 MHz. By definition, 2 3 11 VPDC PWDN EXRB COMM Figure 43. Measured and Ideal LO Filter Frequency Response SFDR = 12 04826-0-047 –10 SUPPLY CURRENT (mA) –5 (IIP3 − NF − kT − 10log(B)) where IIP3 is the input third-order intercept in dBm. NF is the noise figure in dB. kT is the thermal noise power density and is −173.86 dBm/Hz at 298°K. B is the noise bandwidth in Hz. In order to calculate the anticipated SFDR for a given application, it is necessary to factor in the actual noise bandwidth. For instance, if the IF noise bandwidth was 5 MHz, the anticipated SFDR using a 2.43 kΩ RBIAS would be 6.66 log10 (5 MHz) less than the 1 Hz data in Figure 44 or ~80 dBc. Using a 2.43 kΩ bias resistor will set the quiescent power dissipation to ~415 mW for a 5 V supply. If the RBIAS resistor value was raised to 3.9 kΩ, the SFDR for the same 5 MHz bandwidth would be reduced to ~77.5 dBc and the power dissipation would be reduced to ~335 mW. In low power portable applications it may be advantageous to reduce power consumption by using a larger value of RBIAS, assuming reduced dynamic range performance is acceptable. CONVERSION GAIN AND IF LOADING The AD8344 is optimized for driving a 200 Ω differential load. Although the device is capable of driving a wide variety of loads, in order to maintain optimum distortion and noise performance, it is advised that the presented load at the IF outputs is reasonably close to 200 Ω. Figure 45 illustrates the effect of IF loading on conversion gain. The mixer outputs behave like Norton equivalent sources, where the conversion gain is the effective transconductance of the mixer multiplied by the loading impedance. The linear differential voltage conversion gain of the mixer can be modeled as Av = −0.46 × RLOAD × gm 1 + j × g m × 37.70 × f RF where RLOAD is the differential loading impedance. gm is the mixer transconductance and is equal to 4070/RBIAS. fRF is the frequency of the signal applied to the RF port in GHz. Large impedance loads cause the conversion gain to increase, resulting in a decrease in input linearity and allowable signal swing. In order to maintain positive conversion gain and preserve spurious-free dynamic range performance, the differential load presented at the IF port should remain within a range of ~100 Ω to 250 Ω. Rev. 0 | Page 16 of 20 15 10 MEASURED 5 –5 10 100 IF LOADING (Ω) 12 12 9 9 6 6 3 3 0 10 1000 Figure 45. Conversion Gain vs. IF Loading 15 20 25 30 35 IF FREQUENCY (MHz) 40 45 0 50 Figure 46. Conversion Gain, Input IP3, and P1dB vs. IF Frequency, FRF = 450 MHz The AD8344 may be used down to arbitrarily low IF frequencies. The conversion gain, noise, and linearity characteristics remain quite flat as IF frequency is reduced, as indicated in Figure 46 and Figure 47. Larger value pull-up inductors need to be used at the lower IF frequencies. A 1 µH choke inductor would present a common-mode loading impedance of 63 Ω at an IF frequency of 10 MHz, severely loading down the mixer outputs, reducing conversion gain, and sacrificing output power. At low IF frequencies, choke inductors of several hundred µH should be used for biasing the IF outputs. CONVERSION GAIN (dB) LOW IF FREQUENCY OPERATION 8 28.0 7 24.5 6 21.0 5 17.5 4 14.0 3 10.5 2 10 15 20 25 30 35 IF FREQUENCY (MHz) 40 45 Figure 47. Conversion Gain, Input IP3, and P1dB vs. IF Frequency, FRF = 890 MHz Rev. 0 | Page 17 of 20 7.0 50 INPUT IP3 AND P1dB (dBm) 0 15 04826-0-050 MODELED 15 04826-0-049 CONVERSION GAIN (dB) 20 04826-0-048 20LOG–CONVERSION GAIN (dB) 25 INPUT IP3 AND P1dB (dBm) AD8344 AD8344 EVALUATION BOARD An evaluation board is available for the AD8344. The evaluation board is configured for single-ended signaling at the IF output port via a balun transformer. The schematic for the evaluation board is presented in Figure 48. Table 5. Evaluation Boards Configuration Options Component R1, R2, R7, C2, C4, C5, C6, C12, C13, C14, C15 Function Supply Decoupling. Jumpers or power supply decoupling resistors and filter capacitors. R3, R4 R6, C11 Jumpers in Single-Ended IF Output Circuit. RBIAS resistor that sets the bias current for the mixer core. The capacitor provides ac bypass for R6. Jumper for pull down of the PWDN pin. Jumper. RF Input AC Coupling. Provides dc block for RF input. RF Common AC Coupling. Provides dc block for RF input common connection. LO Input AC Coupling. Provides dc block for the LO input. LO Common AC Coupling. Provides dc block for LO input common connection. Power Down. The part is on when the PWDN is connected to ground via SW1. The part is disabled when PWDN is connected to the positive supply (VS) via SW1. IF Output Balun Transformer. Converts differential, high impedance IF output to single-ended. When loaded with 50 Ω, this balun presents a 200 Ω load to the mixers collectors. The center tap of the primary is used to supply the bias voltage (VS) to the IF output pins. IF Output Interface—IFOP, IFOM. These positions can be used to modify the impedance presented to the IF outputs. R8 R9 C3 C1 C8 C7 SW1 T1 R11, Z3, Z4 R12, Z1, Z2 Rev. 0 | Page 18 of 20 Default Conditions R1, R2, R7 = 0 Ω (Size 0603) C4, C6, C13, C14 = 100 pF (Size 0603) C2, C5, C12, C15 = 0.1 µF (Size 0603) 0 Ω (Size 0603) R6 = 2.43 kΩ (Size 0603) C11 = 100 pF (Size 0603) R8 = 10 kΩ (Size 0603) R9 = 0 Ω (Size 0603) C3 = 100 pF (Size 0402) C1 = 100 pF (Size 0402) C8 = 100 pF (Size 0402) C7 = 100 pF (Size 0402) T1 = TC4-1W, 4:1 (Mini-Circuits) R11 = 0 Ω (Size 0603) Z3, Z4 = Open R12 = 0 Ω (Size 0603) Z1, Z2 = Open AD8344 POWER DOWN SW1 C11 100pF COMMON R8 10kΩ COMM COMM RFCM IFOP C1 100pF C3 100pF AD8344 RF INPUT IFOM RFIN R1 0Ω R2 0Ω C5 0.1µF C6 100pF C7 100pF Z2 OPEN R3 0Ω R11 0Ω Z3 OPEN IF OUTPUT T1 TC4-1W R4 0Ω Z4 OPEN COMM LOIN LOCM C4 100pF VPLO C2 0.1µF COMM VPMX VPOS Z1 OPEN R10 0Ω C14 100pF C15 0.1µF C8 100pF LO INPUT VPOS 04826-0-005 PWDN VPDC C13 100pF EXRB R9 0Ω VPOS C12 0.1µF R6 2.43kΩ COMM R7 0Ω 04826-0-007 04826-0-008 Figure 48. Evaluation Board Schematic—Single-Ended IF Output Figure 49. Single-Ended Evaluation Board, Component Side Layout Figure 50. Single-Ended Evaluation Board, Component Side Silkscreen Rev. 0 | Page 19 of 20 AD8344 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 2.75 BSC SQ TOP VIEW 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 16 1 1.65 1.50 SQ* 1.35 BOTTOM VIEW 0.50 BSC 1.00 0.85 0.80 PIN 1 INDICATOR 13 12 0.45 PIN 1 INDICATOR 0.50 0.40 0.30 9 8 5 4 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body (CP-16-3) Dimensions in millimeters ORDERING GUIDE Models AD8344ACPZ-REEL71 AD8344ACPZ-WP1, 2 AD8344-EVAL 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package (LFCSP) 16-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board Z = Pb-free part. WP = Waffle pack. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04826–0–6/04(0) Rev. 0 | Page 20 of 20 Package Option CP-16-3 CP-16-3 Branding JHA JHA