LM139JAN Low Power Low Offset Voltage Quad Comparators General Description Features The LM139 consists of four independent precision voltage comparators with an offset voltage specification as low as 2 mV max for all four comparators. These were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The LM139 was designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, they will directly interface with MOS logic — where the low power drain of the LM139 is a distinct advantage over standard comparators. n Wide supply voltage range 5V to 36 VDC or ± 2.5V to ± 18 VDC n Very low supply current drain (0.8 mA) — independent of supply voltage n Low input biasing current: 25 nA ± 5 nA n Low input offset current: ± 3 mV n Offset voltage: n Input common-mode voltage range includes GND n Differential input voltage range equal to the power supply voltage n Low output saturation voltage: 250 mV at 4 mA n Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems Advantages n n n n n n High precision comparators Reduced VOS drift over temperature Eliminates need for dual supplies Allows sensing near GND Compatible with all forms of logic Power drain suitable for battery operation Ordering Information NS Part Number JAN Part Number NS Package Number JL139BCA JM38510/11201BCA J14A 14LD CERDIP JL139SCA JM38510/11201SCA J14A 14LD CERDIP JL139BZA JM38510/11201BZA WG14A 14LD Ceramic SOIC JL139SZA JM38510/11201SZA WG14A 14LD Ceramic SOIC JL139BDA JM38510/11201BDA W14B 14LD CERPACK JL139SDA JM38510/11201SDA W14B 14LD CERPACK © 2005 National Semiconductor Corporation DS201295 Package Description www.national.com LM139JAN Low Power Low Offset Voltage Quad Comparators February 2005 LM139JAN Connection Diagrams Dual-In-Line Package 20129502 See NS Package NumberJ14A 20129527 See NS Package Number W14B, WG14A www.national.com 2 LM139JAN Schematic Diagram 20129501 3 www.national.com LM139JAN Absolute Maximum Ratings (Note 1) Supply Voltage, V+ 36 VDC or ± 18 VDC Differential Input Voltage (Note 7) 36 VDC Output Voltage 36 VDC Input Voltage −0.3 VDC to +36 VDC Input Current (VIN < −0.3 VDC) (Note 3) Power Dissipation 50 mA (Notes 4, 12) CERDIP 400 mW @ TA = 125˚C CERPACK 350 mW @ TA = 125˚C 350 mW @ TA = 125˚C SOIC Output Short-Circuit to GND, (Note 2) Continuous −65˚C ≤ TA ≤ +150˚C Storage Temperature Range Maximum Junction Temperature (TJ) Lead Temperature +175˚C (Soldering, 10 seconds) 260˚C −55˚C ≤ TA ≤ +125˚C Operating Temperature Range Thermal Resistance θJA CERDIP (Still Air) 103˚C/W CERDIP (500LF / Min Air flow) 65˚C/W CERPACK (Still Air) 183˚C/W CERPACK (500LF / Min Air flow) 120˚C/W SOIC (Still Air) 183˚C/W SOIC (500LF / Min Air flow) 120˚C/W θJC CERDIP 23˚C/W CERPACK 23˚C/W SOIC 23˚C/W Package Weight (typical) CERDIP 2,190mg CERPACK 460mg SOIC 410mg ESD rating (Note 11) 600V Quality Conformance Inspection Mil-Std-883, Method 5005 — Group A Subgroup Description 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 www.national.com Temp (˚C) 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 4 LM139JAN LM139 JAN Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. Symbol VIO Parameters Input Offset Voltage −VCC = 0V Conditions Notes +VCC = 30V, VO = 15V +VCC = 2V, -VCC = -28V, VO = -13V +VCC = 5V, VO = 1.4V +VCC = 2V, -VCC = -3V, VO = -1.6V IIO +/-IIB CMRR Input Offset Current Input Bias Current Input Voltage Common Mode Rejection Min Max Unit Subgroups -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 1, 2 +VCC = 30V, RS = 20KΩ, VO = 15V (Note 8) -25 25 nA (Note 8) -75 75 nA 3 +VCC = 2V, -VCC = -28V, RS = 20KΩ, VO = -13V (Note 8) -25 25 nA 1, 2 (Note 8) -75 75 nA 3 +VCC = 5V, RS = 20KΩ, VO = 1.4V (Note 8) -25 25 nA 1, 2 (Note 8) -75 75 nA 3 +VCC = 2V, -VCC = -3V, RS = 20KΩ, VO = -1.6V (Note 8) -25 25 nA 1, 2 (Note 8) -75 75 nA 3 +VCC = 30V, RS = 20KΩ, VO = 15V (Note 8) -100 +0.1 nA 1, 2 (Note 8) -200 +0.1 nA 3 +VCC = 2V, -VCC = -28V, RS = 20KΩ, VO = -13V (Note 8) -100 +0.1 nA 1, 2 (Note 8) -200 +0.1 nA 3 +VCC = 5V, RS = 20KΩ, VO = 1.4V (Note 8) -100 +0.1 nA 1, 2 (Note 8) -200 +0.1 nA 3 +VCC = 2V, -VCC = -3V, RS = 20KΩ, VO = -1.6V (Note 8) -100 +0.1 nA 1, 2 (Note 8) -200 +0.1 nA 3 +VCC = 30V 76 dB 1, 2, 3 +VCC = 5V 70 dB 1, 2, 3 1.0 µA 1, 2, 3 ICEX Output Leakage +VCC = 30V, VO = +30V +IIL Input Leakage Current +VCC = 36V, V + i = 34V, V − i = 0V -500 500 nA 1, 2, 3 -IIL Input Leakage Current +VCC = 36V, V + i = 0V, V − i = 34V -500 500 nA 1, 2, 3 VOL Logical "0" Output Voltage +VCC = 4.5V, IO = 4mA 0.4 V 1 0.7 V 2, 3 1.5 V 1 2.0 V 2, 3 2.0 mA 1, 2 3.0 mA 3 3.0 mA 1, 2 +VCC = 4.5V, IO = 8mA ICC Power Supply Current +VCC = 5V, VID = 15mV +VCC = 30V, VID = 15mV Delta VIO / Delta T Temperature Coefficient of Input Offset Voltage Delta IIO / Delta T Temperature Coefficient of Input Offset Current AVS Open Loop Voltage Gain VIO 4.0 mA 3 25 µV/˚C 2 -25 25 µV/˚C 3 -300 300 pA/˚C 2 400 pA/˚C 3 25˚C ≤ TA ≤ 125˚C (Note 9) -55˚C ≤ TA ≤ 25˚C (Note 9) 25˚C ≤ TA ≤ 125˚C (Note 9) -55˚C ≤ TA ≤ 25˚C (Note 9) -400 +VCC=15V, RL=15KΩ, 1V ≤ VO ≤ 11V (Note 10) 50 V/mV 4 (Note 10) 25 V/mV 5, 6 Tempco Screen -25 4.0 5 mV www.national.com LM139JAN LM139 JAN Electrical Characteristics (Continued) DC Parameters (Continued) The following conditions apply, unless otherwise specified. Symbol Parameters −VCC = 0V Conditions Notes Min Max Unit Subgroups CMRR Tempco Screen 70 dB IIO Tempco Screen 13 nA IIB Tempco Screen 12 nA Max Unit Subgroups +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 5mV 5.0 µS 7, 8B 7.0 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.2 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 5mV 2.5 µS 7, 8B 3.0 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.0 µS 8A AC Parameters Symbol tRLH tRHL CS VLAT Parameters Response Time: Low-to-High Response Time: High-to-Low Channel Separation Voltage Latch (Logical "1" Input) www.national.com Conditions Notes Min +VCC = 20V, -VCC = -10V, A to B 80 dB 7 +VCC = 20V, -VCC = -10V, A to C 80 dB 7 +VCC = 20V, -VCC = -10V, A to D 80 dB 7 +VCC = 20V, -VCC = -10V, B to A 80 dB 7 +VCC = 20V, -VCC = -10V, B to C 80 dB 7 +VCC = 20V, -VCC = -10V, B to D 80 dB 7 +VCC = 20V, -VCC = -10V, C to A 80 dB 7 +VCC = 20V, -VCC = -10V, C to B 80 dB 7 +VCC = 20V, -VCC = -10V, C to D 80 dB 7 +VCC = 20V, -VCC = -10V, D to A 80 dB 7 +VCC = 20V, -VCC = -10V, D to B 80 dB 7 +VCC = 20V, -VCC = -10V, D to C 80 dB 7 V 9 +VCC = 5V, VI = 10V, IO = 4mA 6 0.4 JAN Electrical Characteristics DC Parameters LM139JAN LM139 (Continued) Drift Values The following conditions apply, unless otherwise specified. −VCC = 0V Delta calculations performed on JAN S product at Group B, Subgroup 5. Min Max Unit Subgroups VCC = 30V,VO = 15V -1.0 1.0 mV 1 VCC = 30V,RS = 20KΩ, VO = 15V -15 15 nA 1 Symbol Parameters Conditions VIO Input Offset Voltage +/- IBias Input Bias Current Notes Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at 25˚)C. Note 4: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤ 100mW), provided the output transistors are allowed to saturate. Note 5: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so no loading change exists on the reference or input lines. Note 6: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20mA independent of the magnitude of V+ Note 7: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power supply, if used) (at 25˚C). Note 8: S/S RS = 20KΩ, tested at RS = 10KΩ as equivalent test. Note 9: Calculated parameter; for Delta VIO / Delta T use VIO test at +VCC = 30V, −VCC = 0V, VO = 15V; and for Delta IIO / Delta T use IIB test at +VCC = 30V, −VCC = 0V, VO = 15V Note 10: Datalog of K = V/mV. Note 11: Human Body model, 1.5 KΩ in series with 100 pF Note 12: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. 7 www.national.com LM139JAN Typical Performance Characteristics Supply Current Input Current 20129534 20129535 Response Time for Various Input Overdrives — Negative Transition Output Saturation Voltage 20129537 20129536 Response Time for Various Input Overdrives — Positive Transition 20129538 www.national.com 8 Driving CMOS The LM139 is a high gain, wide bandwidth device which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator changes states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All pins of any unused comparators should be tied to the negative supply. 20129504 Driving TTL The bias network of the LM139 establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 5 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device. Protection should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25˚C). An input clamp diode can be used as shown in the applications section. The output of the LM139 is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM139 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16 mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60Ω RSAT of the output transistor. The low offset voltage of the output transistor (1 mV) allows the output to clamp essentially to ground level for small load currents. Typical Applications LM139JAN Application Hints 20129505 AND Gate 20129508 OR Gate (V+ = 5.0 VDC) Basic Comparator 20129503 20129509 9 www.national.com LM139JAN Typical Applications (V+= 15 VDC) One-Shot Multivibrator 20129510 Bi-Stable Multivibrator 20129511 www.national.com 10 LM139JAN Typical Applications (V+= 15 VDC) (Continued) One-Shot Multivibrator with Input Lock Out 20129512 Pulse Generator 20129517 11 www.national.com LM139JAN Typical Applications (V+= 15 VDC) (Continued) Large Fan-In AND Gate ORing the Outputs 20129513 20129515 www.national.com 12 LM139JAN Typical Applications (V+= 15 VDC) (Continued) Time Delay Generator 20129514 Non-Inverting Comparator with Hysteresis Inverting Comparator with Hysteresis 20129518 20129519 13 www.national.com LM139JAN Typical Applications (V+= 15 VDC) (Continued) Squarewave Oscillator Basic Comparator 20129521 20129516 Limit Comparator Comparing Input Voltages of Opposite Polarity 20129520 20129524 www.national.com 14 LM139JAN Typical Applications (V+= 15 VDC) (Continued) Output Strobing Crystal Controlled Oscillator 20129522 * Or open-collector logic gate without pull-up resistor 20129525 Transducer Amplifier Zero Crossing Detector (Single Power Supply) 20129530 20129528 15 www.national.com www.national.com 16 250 mVDC ≤ VC ≤ +50 VDC 700 Hz ≤ fO ≤ 100 kHz V+ = +30 VDC Typical Applications (V+= 15 VDC) (Continued) Two-Decade High-Frequency VCO 20129523 LM139JAN LM139JAN Split-Supply Applications (V+ = +15 VDC and V− = −15 VDC) MOS Clock Driver 20129531 Zero Crossing Detector Comparator With a Negative Reference 20129532 20129533 17 www.national.com LM139JAN Revision History Section Date Released 02/15/05 www.national.com Revision A Section Originator Changes New Release to corporate format L. Lytle 1 MDS datasheet converted into Corp. datasheet format. MJLM139-X rev 0D0. MDS datasheet will be archived. 18 LM139JAN Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) NS Package Number J14A Ceramic Flat Package (W) NS Package Number W14B 19 www.national.com LM139JAN Low Power Low Offset Voltage Quad Comparators Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Ceramic SOIC (WG) NS Package Number WG14A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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