TI1 DS80PCI800 2.5 gbps / 5.0 gbps / 8.0 gbps 8 channel pci express repeater with equalization and de-emphasis Datasheet

DS80PCI800
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express
Repeater with Equalization and De-Emphasis
General Description
The DS80PCI800 is a low power, 8 channel repeater with 4stage input equalization, and output de-emphasis driver to
enhance the reach of PCI express serial links in board-toboard or cable interconnects. Ideal for higher density x8 and
x16 PCI express configurations, the DS80PCI800 automatically detects and adapts to Gen-1, Gen-2 and Gen-3 data
rates for easy system upgrade.
Each channel supports seamless detection and management
of the new Gen-3 transmit equalizer coefficients (FIR tap)
handshake protocol and PCIe control signals such as transmit
idle, beacon etc. without external system intervention. An automatic receive detection circuitry controls the input termination impedance based upon endpoint insertion (hot-plug
events). These features guarantee PCIe interoperability at
both the electrical and system level, while reducing design
complexity.
Powered by National’s SiGe BiCMOS process, DS80PCI800
offers programmable transmit de-emphasis (up to 12 dB),
transmit VOD (up to 1300 mVp-p) and receive equalization
(up to 36 dB) to enable longer distance transmission in lossy
copper cables (10m+), or backplanes (40”+) with multiple
connectors. The receiver is capable of opening an input eye
that is completely closed due to inter-symbol interference (ISI)
introduced by the interconnect medium.
The programmable settings can be applied easily via pins,
software (SMBus/I2C) or loaded via an external EEPROM.
When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software
driver.
With a low power consumption and control to turn-off unused
channels, the DS80PCI800 is part of National's PowerWise
family of energy efficient devices.
Features
■ Comprehensive family, proven system inter-operability
■
■
■
■
■
■
■
■
■
■
■
■
DS80PCI102 : x1 PCIe Gen-1/2/3
DS80PCI402 : x4 PCIe Gen-1/2/3
DS80PCI800 : x8/x16 PCIe Gen-1/2/3
Automatic rate detect and adaptation to Gen-1/2/3 speeds
Seamless support for Gen-3 transmit FIR handshake
Rate adaptive receive EQ (up to 36 dB), transmit deemphasis (up to 12 dB) only Gen-1/2
Adjustable Transmit VOD: 0.8 to 1.3 Vp-p (pin mode)
0.2 UI of residual deterministic jitter at 8 Gbps after 40” of
FR4 or 10m 30awg PCIe Cable
Low power dissipation with ability to turnoff unused
channels: 65 mW/channel
Automatic receiver detect (hot-plug)
Multiple configuration modes: Pins/SMbus/DirectEEPROM load
Flow-thru pinout: 54-pin LLP (10 mm x 5.5 mm, 0.5 mm
pitch)
Single supply voltage: 2.5V or 3.3V (selectable)
3 kV HBM ESD rating
−40 to 85°C operating temperature range
Typical Application
30133380
© 2012 Texas Instruments Incorporated
301333 SNLS334E
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DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater with Equalization
and De-Emphasis
March 22, 2012
DS80PCI800
Block Diagram - Detail View Of
Channel (1 Of 8)
30133386
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2
DS80PCI800
Pin Diagram
30133392
DS80PCI800 Pin Diagram 54 lead
Ordering Information
NSID
Qty
Spec
Package
DS80PCI800SQ
Tape & Reel Supplied As 2,000 Units
NOPB
SQA54A
DS80PCI800SQE
Tape & Reel Supplied As 250 Units
NOPB
SQA54A
3
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DS80PCI800
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Description
I
Inverting and non-inverting differential inputs to bank B
equalizer. A gated on-chip 50Ω termination resistor connects
INB_n+ to VDD and INB_n- to VDD when enabled.
10, 11, 12, 13, I
15, 16, 17, 18
Inverting and non-inverting differential inputs to bank B
equalizer. A gated on-chip 50Ω termination resistor connects
INA_n+ to VDD and INA_n- to VDD when enabled.
Differential High Speed I/O's
INB_0+, INB_0-,
INB_1+, INB_1-,
1, 2, 3, 4,
5, 6, 7, 8,
INB_2+, INB_2-,
INB_3+, INB_3-,
INA_0+, INA_0-,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3OUTB_0+, OUTB_0-, 45, 44, 43, 42, O
OUTB_1+, OUTB_1-, 40, 39, 38, 37
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
Inverting and non-inverting 50Ω driver bank A outputs with deemphasis. Compatible with AC coupled CML inputs.
OUTA_0+, OUTA_0-, 35, 34, 33, 32, O
OUTA_1+, OUTA_1-, 31, 30, 29, 28
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
Inverting and non-inverting 50Ω driver bank A outputs with deemphasis. Compatible with AC coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB
48
I, FLOAT,
LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS
O, OPEN
Drain
ENSMB Master or Slave mode
SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master
mode).
SDA
49
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or
open drain (pull-down only) output.
AD0-AD3
54, 53, 47, 46 I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs.
READ_EN
26
I, LVCMOS
When using an External EEPROM, a transition from high to
low starts the load from the external EEPROM
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the
input pins. The pins are active only when ENSMB is deasserted (low). The 8 channels are organized into two banks.
Bank A is controlled with the EQA[1:0] pins and bank B is
controlled with the EQB[1:0] pins. When ENSMB goes high
the SMBus registers provide independent control of each
channel. The EQB[1:0] pins are converted to SMBUS AD2/
AD3 inputs. See Table 2: Equalizer Settings.
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
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20, 19,
46, 47
4
Pin Number
I/O, Type
Pin Description
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis
of the output driver when in Gen1/2 mode. The pins are only
active when ENSMB is de-asserted (low). The 8 channels are
organized into two banks. Bank A is controlled with the DEMA
[1:0] pins and bank B is controlled with the DEMB[1:0] pins.
When ENSMB goes high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are
converted to SMBUS SCL/SDA and DEMB[1:0] pins are
converted to AD0, AD1 inputs.
See Table 3: Output Voltage and De-emphasis Settings.
RATE
21
I, 4-LEVEL,
LVCMOS
RATE control pin selects GEN 1,2 and GEN 3 operating
modes.
Tie 1kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold.
See Table 5: Signal Detect Threshold Level.
DS80PCI800
Pin Name
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function.
Depending on the input level, a 50Ω or >50kΩ termination to
the power rail is enabled.
See Table 4: RX-Detect Settings.
RESERVED
23
I, FLOAT
Float (leave pin open) = Normal Operation
VDD_SEL
25
I, FLOAT
Controls the internal regulator
FLOAT = 2.5V mode
Tie GND = 3.3V mode
PRSNT
52
I, LVCMOS
Cable Present Detect input. high when a cable is not present
per PCIe Cabling Spec. 1.0. Puts part into low power mode.
When LOW (normal operation) part is enabled.
See Table 4: RX-Detect Settings.
27
O, LVCMOS
Valid Register Load Status Output
Outputs
ALL_DONE
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
Power
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating
VDD
9, 14, 36, 41,
51
Power
Power supply pins CML/analog
2.5V mode, connect to 2.5V supply
3.3V mode, connect 0.1uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad)
Notes:
LVCMOS inputs without the “FLOAT” conditions must be driven to a logic low or high at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
5
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DS80PCI800
ESD Rating
HBM, STD - JESD22-A114F
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
Thermal Resistance
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD - 2.5V mode)
Supply Voltage (VIN - 3.3V mode)
LVCMOS Input/Output Voltage
CML Input Voltage
CML Input Current
Junction Temperature
Storage Temperature
Lead Temperature Range Soldering
(4 sec.)
SQA54A Package
Derate SQA54A Package
Symbol
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
-40°C to +125°C
+260°C
θJC
Conditions
Power Dissipation
11.5°C/W
19.1°C/W
θJA, No Airflow, 4 layer JEDEC
For soldering specifications: see product folder at
www.national.com/ms/MS/MS-SOLDERING.pdf
Supply Voltage (2.5V mode)
Supply Voltgae (3.3V mode)
Ambient Temperature
SMBus (SDA, SCL)
Supply Noise up to 50 MHz
(Note 4)
52.6mW/°C above
+25°C
Parameter
3 kV
200 V
1000 V
Min
Min
2.375
3.0
-40
Typ
2.5
3.3
25
Max
2.625
3.6
+85
3.6
100
Units
V
V
°C
V
mVp-p
Typ
Max
Units
VDD = 2.5 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
500
700
mW
VIN = 3.3 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
660
900
mW
2.0
3.6
V
0
0.8
V
Power
PD
LVCMOS / LVTTL DC Specifications
Vih
High Level Input
Voltage
Vil
Low Level Input Voltage
Voh
High Level Output
Voltage
(ALL_DONE pin)
Ioh= −4mA
Vol
Low Level Output
Voltage
(ALL_DONE pin)
Iol= 4mA
Iih
Input High Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
2.0
Input High Current
with internal resistors
(4–level input pin)
Iil
Input Low Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 0 V
Input Low Current
with internal resistors
(4–level input pin)
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6
V
0.4
V
-15
+15
uA
+20
+150
uA
-15
+15
uA
-160
-40
uA
Parameter
Conditions
Min
Typ
Max
Units
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RLrx-cm
RX Differential return
loss
RX Common mode
return loss
0.05 - 1.25 GHz
-16
dB
1.25 - 2.5 GHz
-16
dB
2.5 - 4.0 GHz
-14
dB
0.05 - 2.5 GHz
-12
dB
2.5 - 4.0 GHz
-8
dB
Zrx-dc
RX DC common mode Tested at VDD = 2.5 V
impedance
40
50
60
Ω
Zrx-diff-dc
RX DC differntial mode Tested at VDD = 2.5 V
impedance
80
100
120
Ω
Vrx-diff-dc
Differential RX peak to Tested at pins
peak voltage (VID)
0.6
1.0
1.2
V
Zrx-high-impdc-pos
DC Input common
mode impedance for
V>0
VID = 0 to 200mV,
ENSMB = 0, RXDET = 0,
VDD = 2.5 V
50
KΩ
Vrx-signal-detdiff-pp
Signal detect assert
level for active data
signal
SD_TH = float,
0101 pattern at 8 Gbps
180
mVp-p
Vrx-idle-detdiff-pp
Signal detect de-assert SD_TH = float,
level for electrical idle 0101 pattern at 8 Gbps
110
mVp-p
7
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DS80PCI800
Symbol
DS80PCI800
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
1.0
1.2
Vp-p
High Speed Outputs
Vtx-diff-pp
Output Voltage
Differential Swing
Differential measurement
with OUT_n+ and OUT_n-,
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0,
(Note 7)
Vtx-de-ratio_3.5
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R,
GEN 1, 2 modes only
-3.5
dB
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R,
GEN 1, 2 modes only
-6
dB
TTX-HF-DJ-DD
TX Dj > 1.5 MHz
0.15
UI
TTX-HF-DJ-DD
TX RMS jitter < 1.5 MHz
3.0
ps RMS
TTX-RISE-FALL
TX rise/fall time
20% to 80% of differential
output voltage
TRF-MISMATCH
TX rise/fall mismatch
20% to 80% of differential
output voltage
0.01
RLTX-DIFF
TX Differential return
loss
0.05 - 1.25 GHz
-16
dB
1.25 - 2.5 GHz
-12
dB
2.5 - 4 GHz
-11
dB
0.05 - 2.5 GHz
-12
dB
-8
dB
100
Ω
35
45
ps
0.1
UI
RLTX-CM
TX Common mode
return loss
ZTX-DIFF-DC
DC differential TX
impedance
VTX-CM-AC-PP
TX AC common mode
voltage
ITX-SHORT
TX short circuit current Total current the transmitter
limit
can supply when shorted to
VDD or GND
VTX-CM-DC-
Absolute delta of DC
common mode voltage
during L0 and electrical
idle
100
mV
Absolute delta of DC
common mode voltgae
between TX+ and TX-
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINEDELTA
2.5 - 4 GHz
VOD = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0
100
20
mVpp
mA
TTX-IDLE-DATA
Max time to transition to VID = 1.0 Vp-p, 8 Gbps
differential DATA signal
after IDLE
3.5
ns
TTX-DATA-IDLE
Max time to transition to VID = 1.0 Vp-p, 8 Gbps
IDLE after differential
DATA signal
6.2
ns
TPLHD/PHLD
High to Low
EQ = 00, (Note 6)
and Low to High
Differential Propagation
Delay
200
ps
TLSK
Lane to lane skew
T = 25C, VDD = 2.5V
25
ps
TPPSK
Part to part propagation T = 25C, VDD = 2.5V
delay skew
40
ps
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8
Parameter
Conditions
Min
Typ
Max
Units
Equalization
DJE1
Residual deterministic 35” 4mils FR4,
jitter at 8 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.14
UI
DJE2
Residual deterministic 35” 4mils FR4,
jitter at 5 Gbps
VID = 0.8 Vp-p,
PRBS15,EQ = 1F'h,
DEM = 0 dB
0.1
UI
DJE3
Residual deterministic 35” 4mils FR4,
jitter at 2.5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.05
UI
DJE4
Residual deterministic 10 meters 30 awg cable,
jitter at 8 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.16
UI
DJE5
Residual deterministic 10 meters 30 awg cable,
jitter at 5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.1
UI
DJE6
Residual deterministic 10 meters 30 awg cable,
jitter at 2.5 Gbps
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.05
UI
De-emphasis (GEN 1,2 mode only)
DJD1
Residual deterministic 10” 4mils FR4,
jitter at 2.5 Gbps and VID = 0.8 Vp-p,
5.0 Gbps
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −3.5 dB
0.1
UI
DJD2
Residual deterministic 20” 4mils FR4,
jitter at 2.5 Gbps and VID = 0.8 Vp-p,
5.0 Gbps
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −9 dB
0.1
UI
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVp-p sine wave) under typical conditions.
Note 5: Guaranteed by device characterization.
Note 6: Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.
Note 7: In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by
DEMA/B[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS80PCI800 repeater in GEN3 mode is designed to be transparent,
so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake negotiation link training.
9
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DS80PCI800
Symbol
DS80PCI800
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
RTERM
External Termination Resistance Pullup VDD = 3.3V,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 8, Note 9, Note 10)
10%
Pullup VDD = 2.5V,
(Note 8, Note 9, Note 10)
2.1
(Note 8)
4
mA
2.375
3.6
V
-200
+200
µA
-15
(Note 8, Note 9)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
280
400
400
kHz
520
kHz
TBUF
Bus Free Time Between Stop and
Start Condition
1.3
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
0.6
µs
TSU:STA
Repeated Start Condition Setup
Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
THIGH
Clock High Period
(Note 11)
tF
Clock/Data Fall Time
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(Note 11, Note 12)
1.3
0.6
µs
50
µs
(Note 11)
300
ns
(Note 11)
300
ns
500
ms
Note 8: Recommended value.
Note 9: Recommended maximum capacitance load per bus segment is 400pF.
Note 10: Maximum termination voltage should be identical to the device supply voltage.
Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Note 12: Guaranteed by Design. Parameter not tested in production.
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10
DS80PCI800
Timing Diagrams
30133302
FIGURE 1. CML Output and Rise and FALL Transition Time
30133303
FIGURE 2. Propagation Delay Timing Diagram
30133304
FIGURE 3. Transmit IDLE-DATA and DATA-IDLE Response Time
30133305
FIGURE 4. SMBus Timing Parameters
11
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DS80PCI800
Each input has a total of 256 possible equalization settings.
The tables show the 16 setting when the device is in pin mode.
When using SMBus mode, the equalization, VOD and deEmphasis levels are set by registers.
The input control pins have been enhanced to have 4 different
levels and provide a wider range of control settings when ENSMB=0.
Functional Descriptions
The DS80PCI800 is a low power 8 channel repeater optimized for PCI Express Gen 1/2 and 3. The DS80PCI800
compensates for lossy FR-4 printed circuit board backplanes
and balanced cables. The DS80PCI800 operates in 3 modes:
Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB
= 1) and SMBus Master Mode (ENSMB = float) to load register
informations from external EEPROM; please refer to SMBUS
Master Mode for additional information.
Pin Control Mode:
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side independently.
When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below. The RXDET pins
provides automatic and manual control for input termination
(50Ω or >50KΩ). RATE setting is also pin controllable with pin
selections (Gen 1/2, auto detect and Gen 3). The receiver
electrical idle detect threshold is also adjustable via the
SD_TH pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable
features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon
assertion of ENSMB, the EQx and DEMx functions revert to
register control immediately. The EQx and DEMx pins are
converted to AD0-AD3 SMBus address inputs. The other external control pins (RATE, RXDET and SD_TH) remain active
unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until
ENSMB is driven low (pin mode). On power-up and when
ENSMB is driven low all registers are reset to their default
state. If PRSNT is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible via the pin controls were
chosen to meet the needs of most PCIe applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus registers.
Table 1: 4–Level Control Pin
Settings
Pin Setting
Description
Voltage at Pin
0
Tie 1kΩ to GND
0.03 x VDD
R
Tie 20kΩ to GND
1/3 x VDD
Float
Float (leave pin open) 2/3 x VDD
1
Tie 1kΩ to VDD
0.98 x VDD
Note: The above required resistor value is for a single
device. When there are multiple devices connected to the
pull-up / pull-down resistor, the value must scale with the
number of devices. If 4 devices are connected to a single
pull-up or pull-down, the 1kΩ resistor value should be
250Ω. For the 20kΩ to GND, this should also scale to 5kΩ.
3.3V or 2.5V Supply Mode Operation
The DS80PCI800 has an optional internal voltage regulator
to provide the 2.5V supply to the device. In 3.3V mode operation, the VIN pin = 3.3V is used to supply power to the device.
The internal regulator will provide the 2.5V to the VDD pins of
the device and a 0.1 uF cap is needed at each of the 5 VDD
pins for power supply de-coupling (total capacitance should
be ≤0.5 uF), and the VDD pins should be left open. The
VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5V mode operation, the VIN pin should be left open
and 2.5V supply must be applied to the 5 VDD pins to power
the device. The VDD_SEL pin must be left open (no connect)
to disable the internal regulator.
30133306
FIGURE 5. 3.3V or 2.5V Supply Connection Diagram
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12
When using the DS80PCI800 in CPU systems, there are specific signal integrity settings to ensure signal integrity margin.
The settings were achieved with completing extensive testing. Please contact your field representative for more information regarding the testing completed to achieve these
settings.
For tuning the in the downstream direction (from CPU to EP).
• EQ: use the guidelines outlined in table 2.
Table 2: Equalizer Settings
Level
EQA1
EQB1
EQA0
EQB0
EQ – 8 bits [7:0]
dB at
1.25 GHz
dB at
2.5 GHz
dB at
4 GHz
1
2
Suggested Use
0
0
0000 0000 = 0x00
2.1
3.7
4.9
FR4 < 5 inch trace
0
R
0000 0001 = 0x01
3.4
5.8
7.9
FR4 5 inch 5–mil trace
3
0
Float
0000 0010 = 0x02
4.8
7.7
9.9
FR4 5 inch 4–mil trace
4
0
1
0000 0011 = 0x03
5.9
8.9
11.0
FR4 10 inch 5–mil trace
5
R
0
0000 0111 = 0x07
7.2
11.2
14.3
FR4 10 inch 4–mil trace
6
R
R
0001 0101 = 0x15
6.1
11.4
14.6
FR4 15 inch 4–mil trace
7
R
Float
0000 1011 = 0x0B
8.8
13.5
17.0
FR4 20 inch 4–mil trace
8
R
1
0000 1111 = 0x0F
10.2
15.0
18.5
FR4 25 to 30 inch 4–mil trace
9
Float
0
0101 0101 = 0x55
7.5
12.8
18.0
FR4 30 inch 4–mil trace
10
Float
R
0001 1111 = 0x1F
11.4
17.4
22.0
FR4 35 inch 4–mil trace
11
Float
Float
0010 1111 = 0x2F
13.0
19.7
24.4
10m, 30awg cable
12
Float
1
0011 1111 = 0x3F
14.2
21.1
25.8
10m – 12m cable
13
1
0
1010 1010 = 0xAA
13.8
21.7
27.4
14
1
R
0111 1111 = 0x7F
15.6
23.5
29.0
15
1
Float
1011 1111 = 0xBF
17.2
25.8
31.4
16
1
1
1111 1111 = 0xFF
18.4
27.3
32.7
13
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DS80PCI800
• De-Emphasis: use the guidelines outlined in table 3.
• VOD: use the guidelines outlined in table 3.
For tuning in the upstream direction (from EP to CPU).
• EQ: use the guidelines outlined in table 2.
• De-Emphasis:
— For trace lengths < 15” set to -3.5 dB
— For trace lengths > 15” set to -6 dB
• VOD: set to 900 mV
System Information
DS80PCI800
Table 3: Output Voltage and De-emphasis Settings
Level
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB
(see note below)
Inner Amplitude
Vp-p
Suggested Use
1
0
0
0.8
0
0.8
FR4 <5 inch 4–mil trace
2
0
R
0.9
0
0.9
FR4 <5 inch 4–mil trace
3
0
Float
0.9
- 3.5
0.6
FR4 10 inch 4–mil trace
4
0
1
1.0
0
1.0
FR4 <5 inch 4–mil trace
5
R
0
1.0
- 3.5
0.7
FR4 10 inch 4–mil trace
6
R
R
1.0
-6
0.5
FR4 15 inch 4–mil trace
7
R
Float
1.1
0
1.1
FR4 <5 inch 4–mil trace
8
R
1
1.1
- 3.5
0.7
FR4 10 inch 4–mil trace
9
Float
0
1.1
-6
0.6
FR4 15 inch 4–mil trace
10
Float
R
1.2
0
1.2
FR4 <5 inch 4–mil trace
11
Float
Float
1.2
- 3.5
0.8
FR4 10 inch 4–mil trace
12
Float
1
1.2
-6
0.6
FR4 15 inch 4–mil trace
13
1
0
1.3
0
1.3
FR4 <5 inch 4–mil trace
14
1
R
1.3
- 3.5
0.9
FR4 10 inch 4–mil trace
15
1
Float
1.3
-6
0.7
FR4 15 inch 4–mil trace
16
1
1
1.3
-9
0.5
FR4 20 inch 4–mil trace
Note: The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are also available in GEN 3 mode when RATE = 1 (tied to VDD).
Table 4: RX-Detect Settings
PRSNT#
RXDET
SMBus REG
bit[3:2]
0
0
00
High Impedance
0
Tie 20kΩ
to GND
01
High Impedance High Z until receiver Auto RX-Detect, outputs test every 12
is detected
msec for 600 msec then stops; termination
50 Ω
is high-z until detection; once detected
input termination is 50 Ω
0
Float
(Default)
10
0
1
11
1
X
Input Termination Termination sensed Comments
on output pins
X
Manual RX-Detect, input is high
impedance mode
Reset function by pulsing PRSNT# high for
5 usec then low again
High Impedance High Z until recevier Auto RX-Detect, outputs test every 12
is detected
msec until detection occurs; termination is
50 Ω
high-z until detection; once detected input
termination is 50 Ω
50 Ω
X
Manual RX-Detect, input is 50 Ω
High Impedance
X
Power down mode, input is high
impedance, output drivers are disabled
Used to reset RX-Detect State Machine
when held high for 5 usec
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14
DS80PCI800
Table 5: Signal Detect Threshold Level
SD_TH
SMBus REG bit [3:2] and [1:0]
Assert Level (typ)
De-assert Level (typ)
0
10
210 mVp-p
150 mVp-p
R
01
160 mVp-p
100 mVp-p
F (default)
00
180 mVp-p
110 mVp-p
1
11
190 mVp-p
130 mVp-p
Note: VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
SMBUS Master Mode
The DS80PCI800 devices support reading directly from an external EEPROM device by implementing SMBus Master mode. When
using the SMBus master mode, the DS80PCI800 will read directly from specific location in the external EEPROM. When designing
a system for using the external EEPROM, the user needs to follow these specific guidelines.
•
•
•
Set ENSMB = Float — enable the SMBUS master mode.
The external EEPROM device address byte must be 0xA0'h and capable of 400 kHz operation at 2.5V and 3.3V supply.
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS80PCI800 devices to the SDA and SCL bus, use these guidelines to configure the devices.
•
•
•
Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM. Example below is for 4
device.
U1: AD[3:0] = 0000 = 0xB0'h,
U2: AD[3:0] = 0001 = 0xB2'h,
U3: AD[3:0] = 0010 = 0xB4'h,
U4: AD[3:0] = 0011 = 0xB6'h
Use a pull-up resistor on SDA and SCL; value = 2k ohms
Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence so that they do
not compete for the EEPROM at the same time.
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE# of U1 to READEN# of U2
3. Tie ALL_DONE# of U2 to READEN# of U3
4. Tie ALL_DONE# of U3 to READEN# of U4
5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS80PCI800 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from
the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration
data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS80PCI800
address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS80PCI800 device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
15
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16
CRC EN
Description
Value
0
ch1_idle_tha_1
Description
14
1
ch1_RES_0
13
Description
Value
1
ch1_BST_3
Value
0
Description
12
Value
ch1_Idle_auto
Description
11
0
ch0_DEM_2
10
Description
Value
1
ch0_Sel_scp
Value
0
Description
9
Value
ch0_BST_7
Description
8
0
RD_delay_sel_3
Description
Value
0
Value
7
Ovrd_IDLE
Description
6
0
RES
5
Description
Value
0
lpbk_1
Value
0
4
Description
PWDN_ch7
Value
0
3
Description
Max EEPROM
Burst size[7]
Value
0
2
Description
RES
Value
0
Description
1
Value
0
Bit 7
EEPROM Address
Byte
0
ch1_idle_tha_0
1
ch1_VOD_2
1
ch1_BST_2
0
ch1_Idle_sel
1
ch0_DEM_1
0
ch0_Sel_mode
0
ch0_BST_6
0
RD_delay_sel_2
0
Ovrd_RX_DET
0
RES
0
lpbk_0
0
PWDN_ch6
0
Max EEPROM
Burst size[6]
0
RES
0
Address Map
Present
Bit 6
0
ch1_idle_thd_1
0
ch1_VOD_1
1
ch1_BST_1
0
ch1_RXDET_1
0
ch0_DEM_0
1
ch0_RES_2
1
ch0_BST_5
0
RD_delay_sel_1
0
Ovrd_RATE
0
RES
0
PWDN_INPUTS
0
PWDN_ch5
0
Max EEPROM
Burst size[5]
0
RES
0
EEPROM > 256
Bytes
Bit 5
0
ch1_idle_thd_0
1
ch1_VOD_0
1
ch1_BST_0
0
ch1_RXDET_0
0
ch0_Slow
0
ch0_RES_1
0
ch0_BST_4
0
RD_delay_sel_0
0
RES
0
RES
0
PWDN_OSC
0
PWDN_ch4
0
Max EEPROM
Burst size[4]
0
RES
0
RES
Bit 4
0
ch2_Idle_auto
0
ch1_DEM_2
1
ch1_Sel_scp
0
ch1_BST_7
0
ch0_idle_tha_1
1
ch0_RES_0
1
ch0_BST_3
0
ch0_Idle_auto
0
RES
0
RES
0
Ovrd_PRSNT
0
PWDN_ch3
0
Max EEPROM
Burst size[3]
0
RES
0
DEVICE COUNT
[3]
Bit 3
Table 6: EEPROM Register Map - Single Device with Default Value
0
ch2_Idle_sel
1
ch1_DEM_1
0
ch1_Sel_mode
0
ch1_BST_6
0
ch0_idle_tha_0
1
ch0_VOD_2
1
ch0_BST_2
0
ch0_Idle_sel
1
rx_delay_sel_2
1
rxdet_btb_en
0
RES
0
PWDN_ch2
0
Max EEPROM
Burst size[2]
0
RES
0
DEVICE COUNT
[2]
Bit 2
0
ch2_RXDET_1
0
ch1_DEM_0
1
ch1_RES_2
1
ch1_BST_5
0
ch0_idle_thd_1
0
ch0_VOD_1
1
ch0_BST_1
0
ch0_RXDET_1
1
rx_delay_sel_1
0
Ovrd_idle_th
0
RES
0
PWDN_ch1
0
Max EEPROM
Burst size[1]
0
RES
0
DEVICE COUNT
[1]
Bit 1
0
ch2_RXDET_0
0
ch1_Slow
0
ch1_RES_1
0
ch1_BST_4
0
ch0_idle_thd_0
1
ch0_VOD_0
1
ch0_BST_0
0
ch0_RXDET_0
1
rx_delay_sel_0
0
Ovrd_RES
0
RES
0
PWDN_ch0
0
Max EEPROM
Burst size[0]
0
RES
0
DEVICE COUNT
[0]
BIt 0
DS80PCI800
0
ch6_Sel_mode
31
Description
Value
0
ch6_BST_6
Value
0
Description
30
Value
ch5_idle_tha_0
Description
29
1
ch5_VOD_2
28
Description
Value
1
Value
ch5_BST_2
Description
27
0
ch5_Idle_sel
26
Description
Value
1
ch4_DEM_1
Value
0
Description
25
Value
ch4_Sel_mode
Description
24
0
ch4_BST_6
23
Description
Value
1
en_fast_idle_s
Value
0
Description
22
Value
ch3_idle_tha_1
Description
21
1
ch3_RES_0
Value
1
Description
20
Value
ch3_BST_3
Description
19
0
ch3_Idle_auto
18
Description
Value
0
ch2_DEM_2
Value
1
Description
17
Value
ch2_Sel_scp
16
Description
ch2_BST_7
0
15
Value
Description
1
ch6_RES_2
1
ch6_BST_5
0
ch5_idle_thd_1
0
ch5_VOD_1
1
ch5_BST_1
0
ch5_RXDET_1
0
ch4_DEM_0
1
ch4_RES_2
1
ch4_BST_5
0
eqsd_mgain_n
0
ch3_idle_tha_0
1
ch3_VOD_2
1
ch3_BST_2
0
ch3_Idle_sel
1
ch2_DEM_1
0
ch2_Sel_mode
0
ch2_BST_6
0
ch6_RES_1
0
ch6_BST_4
0
ch5_idle_thd_0
1
ch5_VOD_0
1
ch5_BST_0
0
ch5_RXDET_0
0
ch4_Slow
0
ch4_RES_1
0
ch4_BST_4
0
eqsd_mgain_s
0
ch3_idle_thd_1
0
ch3_VOD_1
1
ch3_BST_1
0
ch3_RXDET_1
0
ch2_DEM_0
1
ch2_RES_2
1
ch2_BST_5
1
ch6_RES_0
1
ch6_BST_3
0
ch6_Idle_auto
0
ch5_DEM_2
1
ch5_Sel_scp
0
ch5_BST_7
0
ch4_idle_tha_1
1
ch4_RES_0
1
ch4_BST_3
0
ch4_Idle_auto
0
ch3_idle_thd_0
1
ch3_VOD_0
1
ch3_BST_0
0
ch3_RXDET_0
0
ch2_Slow
0
ch2_RES_1
0
ch2_BST_4
1
ch6_VOD_2
1
ch6_BST_2
0
ch6_Idle_sel
1
ch5_DEM_1
0
ch5_Sel_mode
0
ch5_BST_6
0
ch4_idle_tha_0
1
ch4_VOD_2
1
ch4_BST_2
0
ch4_Idle_sel
0
ovrd_fast_idle
0
ch3_DEM_2
1
ch3_Sel_scp
0
ch3_BST_7
0
ch2_idle_tha_1
1
ch2_RES_0
1
ch2_BST_3
0
ch3_DEM_0
1
ch3_RES_2
1
ch3_BST_5
0
ch2_idle_thd_1
0
ch2_VOD_1
1
ch2_BST_1
0
ch3_Slow
0
ch3_RES_1
0
ch3_BST_4
0
ch2_idle_thd_0
1
ch2_VOD_0
1
ch2_BST_0
0
ch6_VOD_1
1
ch6_BST_1
0
ch6_RXDET_1
0
ch5_DEM_0
1
ch5_RES_2
1
ch5_BST_5
0
ch4_idle_thd_1
0
ch4_VOD_1
1
ch4_BST_1
0
ch4_RXDET_1
0
1
ch6_VOD_0
1
ch6_BST_0
0
ch6_RXDET_0
0
ch5_Slow
0
ch5_RES_1
0
ch5_BST_4
0
ch4_idle_thd_0
1
ch4_VOD_0
1
ch4_BST_0
0
ch4_RXDET_0
0
0
ch6_DEM_2
1
ch6_Sel_scp
0
ch6_BST_7
0
ch5_idle_tha_1
1
ch5_RES_0
1
ch5_BST_3
0
ch5_Idle_auto
0
ch4_DEM_2
1
ch4_Sel_scp
0
ch4_BST_7
1
en_high_idle_th_n en_high_idle_th_s en_fast_idle_n
1
ch3_DEM_1
0
ch3_Sel_mode
0
ch3_BST_6
0
ch2_idle_tha_0
1
ch2_VOD_2
1
ch2_BST_2
DS80PCI800
17
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18
0
DEM__ovrd_S2
39
Description
Value
0
DEM_ovrd_N2
Value
0
Description
38
Value
ipp_dac_0
Description
37
0
ch7_idle_tha_0
Value
1
Description
36
Value
ch7_VOD_2
Description
35
1
ch7_BST_2
34
Description
Value
0
ch7_Idle_sel
Value
1
33
ch6_DEM_1
Description
32
Value
Description
1
DEM__ovrd_S1
1
DEM_ovrd_N1
0
RD23_67
0
ch7_idle_thd_1
0
ch7_VOD_1
1
ch7_BST_1
0
ch7_RXDET_1
0
ch6_DEM_0
0
DEM_ovrd_S0
0
DEM_ovrd_N0
0
RD01_45
0
ch7_idle_thd_0
1
ch7_VOD_0
1
ch7_BST_0
0
ch7_RXDET_0
0
ch6_Slow
1
VOD_ovrd_S2
1
VOD_ovrd_N2
0
RD_PD_ovrd
0
iph_dac_ns_1
0
ch7_DEM_2
1
ch7_Sel_scp
0
ch7_BST_7
0
ch6_idle_tha_1
0
VOD_ovrd_S1
0
VOD_ovrd_N1
0
RD_Sel_test
0
iph_dac_ns_0
1
ch7_DEM_1
0
ch7_Sel_mode
0
ch7_BST_6
0
ch6_idle_tha_0
1
VOD_ovrd_S0
1
VOD_ovrd_N0
0
RD_RESET_ovrd
0
ipp_dac_ns_1
0
ch7_DEM_0
1
ch7_RES_2
1
ch7_BST_5
0
ch6_idle_thd_1
0
SPARE0
0
SPARE0
0
PWDB_input_DC
0
ipp_dac_ns_0
0
ch7_Slow
0
ch7_RES_1
0
ch7_BST_4
0
ch6_idle_thd_0
0
SPARE1
0
SPARE1
0
DEM_VOD_ovrd
0
ipp_dac_1
0
ch7_idle_tha_1
1
ch7_RES_0
1
ch7_BST_3
0
ch7_Idle_auto
DS80PCI800
39
27
0x56
VOD CHA2 = 1.0V
40
28
0x00
DEM CHA2 = 0 (0dB)
EEPROM Address EEPROM Comments
Address (Hex)
Data
41
29
0x00
EQ CHA3 = 00
42
2A
0x15
VOD CHA3 = 1.0V
0
43
2B
0x60
DEM CHA3 = 0 (0dB)
44
2C
0x00
45
2D
0x00
46
2E
0x54
47
2F
0x54
End Device 0, 1 - Address
Offset 39
Begin Device 2, 3 Address Offset 3
00
0x43
CRC_EN = 0, Address
Map = 1, >256 bytes = 0,
Device Count[3:0] = 3
1
01
0x00
2
02
0x08
EEPROM Burst Size
3
03
0x00
CRC not used
4
04
0x0B
Device 0 Address
Location
48
30
0x00
5
05
0x00
CRC not used
49
31
0x00
6
06
0x0B
Device 1 Address
Location
50
32
0x04
51
33
0x07
52
34
0x00
53
35
0x00
EQ CHB0 = 00
54
36
0xAB
VOD CHB0 = 1.0V
55
37
0x00
DEM CHB0 = 0 (0dB)
56
38
0x00
EQ CHB1 = 00
57
39
0x0A
VOD CHB1 = 1.0V
58
3A
0xB0
DEM CHB1 = 0 (0dB)
3B
0x00
7
07
0x00
CRC not used
8
08
0x30
Device 2 Address
Location
9
09
0x00
CRC not used
10
0A
0x30
Device 3 Address
Location
11
0B
0x00
Begin Device 0, 1 Address Offset 3
12
0C
0x00
59
13
0D
0x04
60
3C
0x00
EQ CHB2 = 00
0x07
61
3D
0xAB
VOD CHB2 = 1.0V
62
3E
0x00
DEM CHB2 = 0 (0dB)
EQ CHB0 = 00
63
3F
0x00
EQ CHB3 = 00
VOD CHB0 = 1.0V
64
40
0x0A
VOD CHB3 = 1.0V
DEM CHB0 = 0 (0dB)
65
41
0xB0
DEM CHB3 = 0 (0dB)
42
0x01
14
0E
15
0F
0x00
16
10
0x00
17
18
11
12
0xAB
0x00
19
13
0x00
EQ CHB1 = 00
66
20
14
0x0A
VOD CHB1 = 1.0V
67
43
0x80
DEM CHB1 = 0 (0dB)
68
44
0x01
EQ CHA0 = 00
69
45
0x56
VOD CHA0 = 1.0V
EQ CHB2 = 00
70
46
0x00
DEM CHA0 = 0 (0dB)
VOD CHB2 = 1.0V
71
47
0x00
EQ CHA1 = 00
48
0x15
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
21
15
0xB0
22
16
0x00
23
17
0x00
24
18
0xAB
25
19
0x00
DEM CHB2 = 0 (0dB)
72
26
1A
0x00
EQ CHB3 = 00
73
49
0x60
4A
0x00
27
1B
0x0A
VOD CHB3 = 1.0V
74
28
1C
0xB0
DEM CHB3 = 0 (0dB)
75
4B
0x01
EQ CHA2 = 00
29
1D
0x01
76
4C
0x56
VOD CHA2 = 1.0V
0x80
77
4D
0x00
DEM CHA2 = 0 (0dB)
0x01
EQ CHA0 = 00
78
4E
0x00
EQ CHA3 = 00
4F
0x15
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
30
31
1E
1F
32
20
0x56
VOD CHA0 = 1.0V
79
33
21
0x00
DEM CHA0 = 0 (0dB)
80
50
0x60
51
0x00
34
22
0x00
EQ CHA1 = 00
81
35
23
0x15
VOD CHA1 = 1.0V
82
52
0x00
36
24
0x60
DEM CHA1 = 0 (0dB)
83
53
0x54
84
54
0x54
37
25
0x00
End Device 2, 3 - Address
Offset 39
38
26
0x01
EQ CHA2 = 00
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8–channels set to EQ = 00 (min
boost), VOD = 1.0V, DEM = 0 (0dB) and multiple device can point to the same address map.
19
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DS80PCI800
Table 7: Example of EEPROM for 4
Devices using 2 Address Maps
DS80PCI800
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1kΩ to VDD to
enable SMBus slave mode and allow access to the configuration registers.
The DS80PCI800 has the AD[3:0] inputs in SMBus mode.
These pins are the user set SMBUS slave address inputs. The
AD[3:0] pins have internal pull-down. When left floating or
pulled low the AD[3:0] = 0000'b, the device default address
byte is B0'h. Based on the SMBus 2.0 specification, the
DS80PCI800 has a 7-bit slave address. The LSB is set to 0'b
(for a WRITE). The device supports up to 16 address byte,
which can be set with the AD[3:0] inputs. Below are the 16
addresses.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Table 8: Device Slave Address Bytes
AD[3:0] Settings
Address Bytes (HEX)
0000
B0
0001
B2
0010
B4
0011
B6
0100
B8
0101
BA
0110
BC
0111
BE
1000
C0
1001
C2
1010
C4
1011
C6
1100
C8
1101
CA
1110
CC
1111
CE
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see SMBus Register Map Table for more information.
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant.
External pull-up resistor is required on the SDA. The resistor
value can be from 1 kΩ to 5 kΩ depending on the voltage,
loading and speed. The SCL may also require an external
pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
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20
DS80PCI800
Table 9: SMBUS Slave Mode Register Map
Address Register Name
Bit (s) Field
Type Default
Description
0x00
7
Reserved
R/W
Set bit to 0.
6:3
Address Bit
AD[3:0]
R
Observation of AD[3:0] bit
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2
EEPROM Read
Done
R
1: Device completed the read from external
EEPROM.
1
Block Reset
R/W
1: Block bit 0 from resettting the registers; self
clearing.
0
Reset
R/W
SMBus Reset
1: Reset registers to default value; self clearing.
Observation,
Reset
0x00
0x01
PWDN Channels
7:0
PWDN CHx
R/W
0x00
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Note: override PRSNT pin.
0x02
Override
PRSNT Control
7:1
Reserved
R/W
0x00
Set bits to 0.
0
Override PRSNT
0x05
Slave Mode CRC
Bits
7:0
CRC bits
R/W
0x00
CRC bits [7:0]
0x06
Slave CRC Control
7:5
Reserved
R/W
0x10
Set bits to 0.
4
Reserved
Set bit to 1.
3
Slave CRC
1: Disables the slave CRC mode
0: Enables the slave CRC mode
Note: In order to change VOD, DEM and EQ of
the channels in slave mode, set bit to 1 to disable
the CRC.
2:0
Reserved
7
Reserved
6
Override SD_TH
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
Reserved
Set bit to 0.
4
Override IDLE
1: IDLE control by registers
0: IDLE control by signal detect
3
Override RXDET
1: Block RXDET pin control
0: Allow RXDET pin control
2
Override RATE
1: Block RATE pin control
0: Allow RATE pin control
1
Reserved
Set bit to 0.
0
Reserved
Set bit to 0.
0x08
Override
Pin Control
1: Block PRSNT pin control
0: Allow PRSNT pin control
Set bits to 0.
R/W
21
0x00
Set bit to 0.
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DS80PCI800
0x0E
CH0 - CHB0
IDLE, RXDET
R/W
0x00
7:6
Reserved
Set bits to 0.
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
0x0F
CH0 - CHB0
EQ
7:0
EQ Control
R/W
0x2F
IB0 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x10
CH0 - CHB0
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH0 - CHB0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x11
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CH0 - CHB0
DEM
Set bits to 0.
22
0x02
Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
0x15
CH0 - CHB0
IDLE Threshold
CH1 - CHB1
IDLE, RXDET
R/W
0x00
DS80PCI800
0x12
7:4
Reserved
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
Set bits to 0.
R/W
0x00
Set bits to 0.
Set bits to 0.
0x16
CH1 - CHB1
EQ
7:0
EQ Control
R/W
0x2F
IB1 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x17
CH1 - CHB1
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
23
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DS80PCI800
0x18
0x19
0x1C
0x1D
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CH1 - CHB1
DEM
CH1 - CHB1
IDLE Threshold
CH2 - CHB2
IDLE, RXDET
CH2 - CHB2
EQ
0x02
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH1 - CHB1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7:4
Reserved
R/W
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
7:0
EQ Control
R/W
0x00
0x00
Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
Set bits to 0.
Set bits to 0.
Set bits to 0.
R/W
24
0x2F
IB2 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x1F
0x20
CH2 - CHB2
VOD
CH2 - CHB2
DEM
CH2 - CHB2
IDLE Threshold
R/W
0xAD
DS80PCI800
0x1E
7
Short Circuit
Protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH2 - CHB2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7:4
Reserved
R/W
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
25
0x02
0x00
1: Enable the short circuit protection
0: Disable the short circuit protection
Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
Set bits to 0.
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DS80PCI800
0x23
CH3 - CHB3
IDLE, RXDET
R/W
0x00
7:6
Reserved
Set bits to 0.
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
0x24
CH3 - CHB3
EQ
7:0
EQ Control
R/W
0x2F
IB3 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x25
CH3 - CHB3
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH3 - CHB3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x26
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CH3 - CHB3
DEM
Set bits to 0.
26
0x02
Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
0x2B
CH3 - CHB3
IDLE Threshold
CH4 - CHA0
IDLE, RXDET
R/W
0x00
DS80PCI800
0x27
7:4
Reserved
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
Set bits to 0.
R/W
0x00
Set bits to 0.
Set bits to 0.
0x2C
CH4 - CHA0
EQ
7:0
EQ Control
R/W
0x2F
IA0 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x2D
CH4 - CHA0
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
27
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DS80PCI800
0x2E
0x2F
0x32
0x33
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CH4 - CHA0
DEM
CH4 - CHA0
IDLE Threshold
CH5 - CHA1
IDLE, RXDET
CH5 - CHA1
EQ
0x02
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH4 - CHA0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7:4
Reserved
R/W
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
7:0
EQ Control
R/W
0x00
0x00
Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
Set bits to 0.
Set bits to 0.
Set bits to 0.
R/W
28
0x2F
IA1 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x35
0x36
CH5 - CHA1
VOD
CH5 - CHA1
DEM
CH5 - CHA1
IDLE Threshold
R/W
0xAD
DS80PCI800
0x34
7
Short Circuit
Protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH5 - CHA1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7:4
Reserved
R/W
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
29
0x02
0x00
1: Enable the short circuit protection
0: Disable the short circuit protection
Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
Set bits to 0.
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DS80PCI800
0x39
CH6 - CHA2
IDLE, RXDET
R/W
0x00
7:6
Reserved
Set bits to 0.
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
0x3A
CH6 - CHA2
EQ
7:0
EQ Control
R/W
0x2F
IA2 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x3B
CH6 - CHA2
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH6 - CHA2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3C
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CH6 - CHA2
DEM
Set bits to 0.
30
0x02
Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
0x40
CH6 - CHA2
IDLE Threshold
CH7 - CHA3
IDLE, RXDET
R/W
0x00
DS80PCI800
0x3D
7:4
Reserved
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:6
Reserved
5
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
RXDET
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is high-z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once
detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
Reserved
Set bits to 0.
R/W
0x00
Set bits to 0.
Set bits to 0.
0x41
CH7 - CHA3
EQ
7:0
EQ Control
R/W
0x2F
IA3 EQ Control - total of 256 levels.
See Table 2: Equalizer Settings.
0x42
CH7 - CHA3
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
Reserved
Set bits to default value - 101.
2:0
VOD Control
OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
31
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DS80PCI800
0x43
0x44
0x51
www.ti.com
CH7 - CHA3
DEM
CH7 - CHA3
IDLE Threshold
Device ID
0x02
7
RXDET STATUS
R
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH7 - CHA3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
Reserved
R/W
Set bits to 0.
2:0
DEM Control
R/W
OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7:4
Reserved
R/W
3:2
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
7:5
VERSION
4:0
ID
R
0x00
0x45
Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
Set bits to 0.
010'b
00101'b
32
GENERAL RECOMMENDATIONS
The DS80PCI800 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the information
below and Revision 4 of the LVDS Owner's Manual for more
detailed information on high speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and LPDS outputs have been optimized to
work with interconnects using a controlled differential
30133310
FIGURE 6. Typical Routing Options
The graphic shown above depicts different transmission line
topologies which can be used in various combinations to
achieve the optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated
by increasing the swell around each hole and providing for a
low inductance return current path. When the via structure is
associated with thick backplane PCB, further optimization
such as back drilling is often used to reduce the deterimential
high frequency effects of stubs on the signal path.
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS80PCI800.
Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power
supply bypassing design as well. These capacitors can be
either tantalum or an ultra-low ESR ceramic.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS80PCI800 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
33
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DS80PCI800
impedance of 85 - 100Ω. It is preferable to route differential
lines exclusively on one layer of the board, particularly for the
input traces. The use of vias should be avoided if possible. If
vias must be used, they should be used sparingly and must
be placed symmetrically for each side of a given differential
pair. Whenever differential vias are used the layout must also
provide for a low inductance path for the return currents as
well. Route the differential signals away from other signals
and noise sources on the printed circuit board. See AN-1187
for additional information on LLP packages.
Applications Information
DS80PCI800
Typical Performance Curves Characteristics
30133327
FIGURE 7. Power Dissipation (PD) vs. Output Differential Voltage (VOD)
30133328
FIGURE 8. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Supply Voltage (VDD)
30133329
FIGURE 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature
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34
DS80PCI800
Typical Performance Eye Diagrams Characteristics
30133330
FIGURE 10. Test Setup Connections Diagram
30133331
FIGURE 11. TL = 20 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
30133332
FIGURE 12. TL = 35 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = float, R = 1F'h, DEM[1:0] = float, float
35
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DS80PCI800
30133333
FIGURE 13. Test Setup Connections Diagram
30133334
FIGURE 14. TL1 = 20 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
30133335
FIGURE 15. TL1 = 30 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, 1 = 0F'h, DEM[1:0] = float, float
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36
DS80PCI800
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS80PCI800SQ (Tape and Reel 2,000 units)
Order Number DS80PCI800SQE (Tape and Reel 250 units)
NS Package Number SQA54A
(See AN-1187 for PCB Design and Assembly Recommendations)
37
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DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater with Equalization
and De-Emphasis
Notes
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