DATASHEET Dual, Noninverting Power MOSFET Radiation Hardened Drivers HS-4424DRH, HS4424DEH Features The radiation hardened HS-4424 family are noninverting, dual, monolithic high-speed MOSFET drivers designed to convert low voltage control input signals into higher voltage, high current outputs. The HS-4424DRH, HS-4424DEH are fully tested across the 8V to 18V operating range. • Electrically screened to DLA SMD# 5962-99560 The inputs of these devices can be directly driven by the HS-1825ARH PWM device or by our ACS/ACTS and HCS/HCTS type logic devices. The fast rise times and high current outputs allow very quick control of high gate capacitance power MOSFETs in high frequency applications. The high current outputs minimize power losses in MOSFETs by rapidly charging and discharging the gate capacitance. The output stage incorporates a low voltage lockout circuit that puts the outputs into a three-state mode when the supply voltage is below its Undervoltage Lockout (UVLO) threshold voltage. Constructed with Intersil’s dielectrically isolated Rad Hard Silicon Gate (RSG) BiCMOS process, these devices are immune to single event latch-up and have been specifically designed to provide highly reliable performance in harsh radiation environments. TABLE 1. HS4424 PRODUCT FAMILY SPECIFIC UVLO Vth PART NUMBER UVLO (V) HS-4424RH HS-4424EH <10 HS4424BRH HS4424BEH <7.5 HS4424DRH HS4424DEH <8 • QML qualified per MIL-PRF-38535 requirements • Latch-up immune • Radiation environment • High dose rate (50-300rad(Si)/s). . . . . . . . . . . . . 300krad(Si) - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 50krad(Si)* *Limit established by characterization • IPEAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2A (minimum) • Matched rise and fall times (CL = 4300pF). . 75ns (maximum) • Low voltage lockout feature . . . . . . . . . . . . . . . . . . . . . . . . <8V • Wide supply voltage range . . . . . . . . . . . . . . . . . . . . 8V to 18V • Propagation delay . . . . . . . . . . . . . . . . . . . . 250ns (maximum) • Consistent delay times with VCC changes • Low power consumption - 40mW with inputs high - 20mW with inputs low • Low equivalent input capacitance . . . . . . . . . . 3.2pF (typical) • ESD protected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV Applications • Switching power supplies • DC/DC converters • Motor controllers VCC IN A PWM CONTROLLER OUT A IN B OUT B HS-1825ARH HS-4424D GND FIGURE 1. TYPICAL APPLICATION October 15, 2015 FN8747.2 1 UNDERVOLTAGE LOCKOUT (V) 7.7 +8V TO +18V UVLO_f 7.6 UVLO_r 7.5 7.4 7.3 7.2 -55 25 125 TEMPERATURE (°C) FIGURE 2. UNDERVOLTAGE LOCKOUT vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HS-4424DRH, HS4424DEH Pin Configuration HS-4424DRH, HS-4424DEH (16 LD FLATPACK) TOP VIEW NC 1 16 NC IN A 2 15 OUT A NC 3 14 OUT A GND A 4 13 VCC GND B 5 12 VCC NC 6 11 OUT B IN B 7 10 OUT B NC 8 9 NC Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT ESD CIRCUIT 1, 3, 6, 8, 9, 16 NC NA 2 IN A Circuit 2 4 GND A NA Ground Reference A 5 GND B NA Ground Reference B 7 IN B Circuit 2 10, 11 OUT B NA 12, 13 VCC Circuit 1 14, 15 OUT A NA VCC DESCRIPTION No Internal Connection Driver A Input Driver B Input Driver B Output Positive Power Supply Driver A Output VCC 2kΩ IN GND GND FIGURE 3. CIRCUIT 1 Submit Document Feedback 2 FIGURE 4. CIRCUIT 2 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Functional Block Diagram VCC VCC LEVEL Level Shifter SHIFTER IN IN AA OUTAA OUT CONTROL LOGIC Control Logic & AND UVLO UVLO OUTAA OUT 1k 1k GND A GND A VCC VCC LEVEL Level Shifter SHIFTER IN IN BB OUTBB OUT CONTROL LOGIC Control Logic & AND UVLO OUTBB OUT UVLO 1k 1k GND B GND FIGURE 5. BLOCK DIAGRAM Ordering Information SMD NUMBER ORDERING (Note 2) PART NUMBER (Note 1) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F9956005V9A HS0-4424DRH-Q -55 to +125 DIE HS0-4424DRH/SAMPLE HS0-4424DRH/SAMPLE -55 to +125 DIE SAMPLE 5962F9956005VXC HS9-4424DRH-Q -55 to +125 16 Ld Flatpack K16.A HS9-4424DRH/PROTO HS9-4424DRH/PROTO -55 to +125 16 Ld Flatpack K16.A 5962F9956006V9A HS0-4424DEH-Q -55 to +125 DIE 5962F9956006VXC HS9-4424DEH-Q -55 to +125 16 Ld Flatpack K16.A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. Submit Document Feedback 3 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VCC Output Short-circuit Duration (1 output at a time). . . . . . . . . . . . Indefinite ESD Rating Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 5kV Machine Model (Tested per MIL-PRF-883 3015.7) . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 16 Ld Flatpack Package (Notes 3, 4). . . . . 34 5 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+175°C Maximum Lead Temperature (Soldering 10 secs) . . . . . . . . . . . . . .+265°C Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 18V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. PARAMETER VSUPPLY ICCSB LOW DESCRIPTION TEST CONDITIONS Supply Voltage Range 18V Bias Current MIN (Note 5) TYP 8 ICCSB LOW ICCSB HIGH IIL_18 IIH_18 IIL_8 IIH_8 18V Bias Current 8V Bias Current 8V Bias Current Input Current Low Input Current High Input Current Low Input Current High V VS = 18V, Inputs = 0V 3.5 mA VS = 18V, Inputs = 0V 4 mA 4 mA VS, Inputs = 18V 3.5 mA VS, Inputs = 18V 4 mA VS, Inputs = 18V, post radiation 4 mA VS = 8V, Inputs = 0V 3.5 mA VS = 8V, Inputs = 0V 4 mA VS = 8V, Inputs = 0V, post radiation 4 mA VS, Inputs = 8V 3.5 mA VS, Inputs = 8V 4 mA VS, Inputs = 8V, post radiation 4 mA 5 µA VS = 18V, Inputs = 0V -5 VS = 18V, Inputs = 0V -10 10 µA VS = 18V, Inputs = 0V, post radiation -10 10 µA 5 µA 10 µA VS, Inputs = 18V -5 VS, Inputs = 18V -10 VS, Inputs = 18V, post radiation -10 Output Voltage High 4 0.08 µA 5 µA VS = 8V, Inputs = 0V -10 10 µA VS = 8V, Inputs = 0V, post radiation -10 10 µA VS, Inputs = 8V -5 VS, Inputs = 8V -10 VS = 8V, IOUT = 5mA 0.08 10 -5 0.08 -10 VS - 0.75 VS - 0.9 Submit Document Feedback 0.08 VS = 8V, Inputs = 0V VS, Inputs = 8V, post radiation VOH UNIT 18 VS = 18V, Inputs = 0V, post radiation ICCSB HIGH MAX (Note 5) VS - 0.45 5 µA 10 µA 10 µA V V FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS VOL Output Voltage Low VS = 8V, IOUT = 5mA VOH Output Voltage High VS = 8V, IOUT = 50mA VOL Output Voltage Low VS = 8V, IOUT = 50mA MIN (Note 5) TYP MAX (Note 5) UNIT 0.45 0.8 V 0.8 VS - 0.95 VS - 0.75 VS - 1.1 VOH Output Voltage High VS = 12V, IOUT = 5mA VOL Output Voltage Low VS = 12V, IOUT = 5mA VOH Output Voltage High VS = 12V, IOUT = 50mA V 0.75 VS - 0.75 0.95 V 1.1 V VS - 0.45 V VS - 0.75 V 0.45 0.8 0.8 VS - 0.95 VS - 0.75 Output Voltage Low VS = 12V, IOUT = 50mA VOH Output Voltage High VS = 18V, IOUT = 5mA VOL Output Voltage Low VS = 18V, IOUT = 5mA 0.95 1.1 VS - 0.45 Output Voltage High VS = 18V, IOUT = 50mA VOL Output Voltage Low VS = 18V, IOUT = 50mA Input Voltage High Threshold VS = 18V 0.8 V 0.8 V VS - 0.75 V VS - 1.1 V 0.75 0.95 1.1 VIH_18 VIL_18 Input Voltage Low Threshold VS = 18V Input Voltage Threshold Hysteresis VS = 18V VIH_12 Input Voltage High Threshold VS = 12V Input Voltage Low Threshold V V 3.1 V 0.8 V V 100 mV 3 V 3.1 VIL_12 V 3 0.8 VIHYS_18 V V 0.45 VS - 0.95 V V VS - 0.75 VOH V V 0.75 VS - 0.75 V V VS - 1.1 VOL V V V VS = 12V 0.8 V 0.8 V Input Voltage Threshold Hysteresis VS = 12V 100 mV VIH_8 Input Voltage High Threshold VS = 8V 3 V VIL_8 Input Voltage Low Threshold VS = 8V VHYS_12 3.1 VHYS_8 Input Voltage Threshold Hysteresis UVLO_r Rising Undervoltage Lockout VS = 8V V 7.2 Falling Undervoltage Lockout Min_PW Undervoltage Lockout Hysteresis Minimum Input Pulse Width Submit Document Feedback 5 0.8 V mV 7.5 7.1 7.45 6.8 HYS_UVLO V 100 6.9 UVLO_f 0.8 UVLO_r - UVLO_f 100 7.8 V 7.95 V 7.75 V 7.9 V 23 mV 24 mV ns FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. (Continued) PARAMETER DESCRIPTION MIN (Note 5) MAX (Note 5) UNIT VS = 18V, CL = 4300pF 75 ns VS = 18V, CL = 4300pF 95 ns TEST CONDITIONS TYP TRANSIENT RESPONSE tr, tf, Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT Rise Time 10% to 90% of VOUT 95 ns 75 ns VS = 18V, CL = 4300pF 95 ns VS = 18V, CL = 4300pF, post radiation 95 ns VS = 12V, CL = 4300pF 75 ns VS = 12V, CL = 4300pF 95 ns VS = 12V, CL = 4300pF, post radiation 95 ns VS = 12V, CL = 4300pF 75 ns VS = 12V, CL = 4300pF 95 ns VS = 12V, CL = 4300pF, post radiation 95 ns VS = 8V, CL = 4300pF 75 ns VS = 8V, CL = 4300pF 95 ns VS = 8V, CL = 4300pF, post radiation 95 ns VS = 8V, CL = 4300pF 75 ns VS = 8V, CL = 4300pF 95 ns VS = 8V, CL = 4300pF, post radiation 95 ns 50% of Rising Input to 10% of Rising Output VS = 18V, CL = 4300pF 200 ns VS = 18V, CL = 4300pF 300 ns Fall Time 90% to 10% of VOUT tPHL, tPLH, VS = 18V, CL = 4300pF, post radiation VS = 18V, CL = 4300pF 300 ns 50% of Falling Input to 90% of Falling Output VS = 18V, CL = 4300pF VS = 18V, CL = 4300pF, post radiation 200 ns VS = 18V, CL = 4300pF 300 ns VS = 18V, CL = 4300pF, post radiation 300 ns 50% of Rising Input to 10% of Rising Output VS = 12V, CL = 4300pF 250 ns VS = 12V, CL = 4300pF 350 ns 350 ns 50% of Falling Input to 90% of Falling Output VS = 12V, CL = 4300pF VS = 12V, CL = 4300pF, post radiation 250 ns VS = 12V, CL = 4300pF 350 ns VS = 12V, CL = 4300pF, post radiation 350 ns 50% of Rising Input to 10% of Rising Output VS = 8V, CL = 4300pF 300 ns VS = 8V, CL = 4300pF 400 ns 400 ns 50% of Falling Input to 90% of Falling Output VS = 8V, CL = 4300pF VS = 8V, CL = 4300pF, post radiation 300 ns VS = 8V, CL = 4300pF 400 ns VS = 8V, CL = 4300pF, post radiation 400 ns NOTE: 5. Compliance to datasheet limits is assured by one or more methods; production test, characterization and/or design. Submit Document Feedback 6 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Typical Performance Curves Unless otherwise specified, VS = 8V, 12V, 18V, CL = 4300pF, TA = +25°C. 200 ICCSBH_18 2.5 ICCSBH_8 2.0 ICCSBL_18 1.5 ICCSBL_8 1.0 0.5 0 -55 25 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 3.0 150 100 18V_BIAS 8V_BIAS 50 0 1k 125 10k 0.95 VOH_8_5 OUTPUT VOLTAGE TO SUPPLY OR GND (V) OUTPUT VOLTAGE TO SUPPLY OR GND (V) 0.9 VOH_18_5 0.7 0.6 VOL_8_5 0.5 VOL_18_5 0.4 0.3 0.2 0.1 -55 25 VOH_18_50 0.90 0.85 VOH_8_50 0.80 0.75 VOL_8_50 0.70 VOL_18_50 0.65 0.60 0.55 0.50 125 -55 125 FIGURE 8. OUTPUT VOLTAGE vs TEMPERATURE (50mA) 3.0 3.0 VOH +125 2.5 VOH +85 2.0 1.5 VOH +25 VOH -55 1.0 VOL +125 0.5 VOL +25 VOL -55 0 3 6 9 30 60 90 VOL +85 199 349 OUTPUT CURRENT (mA) FIGURE 9. OUTPUT VOLTAGE vs OUTPUT CURRENT Submit Document Feedback 7 498 INPUT VOLTAGE THRESHOLD (V) OUTPUT VOLTAGE TO 8V SUPPLY OR GND (V) 25 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. OUTPUT VOLTAGE vs TEMPERATURE (5mA) 0 1M FIGURE 6. SUPPLY CURRENT vs DUAL SWITCHING AT FREQUENCY FIGURE 5. SUPPLY CURRENT vs TEMPERATURE 0.8 100k FREQUENCY (Hz) TEMPERATURE (°C) 2.8 18V VIH 2.6 12V VIH 2.4 2.2 2.0 8V VIH 1.8 1.6 1.4 12V VIL 8V VIL 18V VIL 1.2 1.0 -55 25 125 TEMPERATURE (°C) FIGURE 10. INPUT VOLTAGE THRESHOLD vs TEMPERATURE AND BIAS VOLTAGE FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Unless otherwise specified, VS = 8V, 12V, 18V, CL = 4300pF, TA = +25°C. (Continued) 0.5 300 0.0 250 PROPAGATION DELAY (ns) INPUT CURRENT (µA) Typical Performance Curves -0.5 IIH_18 -1.0 IIH_8 IIL_8 -1.5 -2.0 IIL_18 -2.5 -3.0 -55 25 TPHL_12 200 150 TPHL_18 TPLH_8 100 TPLH_18 TPLH_12 50 0 125 TPHL_8 -55 25 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 11. INPUT CURRENT vs TEMPERATURE AND BIAS VOLTAGE FIGURE 12. PROPAGATION DELAY vs TEMPERATURE 70 TR_12 RISE/FALL (ns) 65 TR_18 60 OUTPUT 2V/DIV 55 50 TF_12 TF_8 TF_18 45 40 INPUT 5V/DIV TR_8 35 -55 25 125 TEMPERATURE (°C) FIGURE 13. RISE/FALL TIME vs TEMPERATURE OUTPUT 5V/DIV 1µs/DIV FIGURE 14. 1MHz AT 8V BIAS OUTPUT 2V/DIV INPUT 5V/DIV INPUT 5V/DIV 1µs/DIV FIGURE 15. 1MHz AT 18V BIAS Submit Document Feedback 8 100ns/DIV FIGURE 16. 8V RISING/FALLING PROPAGATION TIME FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Typical Performance Curves Unless otherwise specified, VS = 8V, 12V, 18V, CL = 4300pF, TA = +25°C. (Continued) OUTPUT 2V/DIV OUTPUT 5V/DIV INPUT 5V/DIV INPUT 5V/DIV 100ns/DIV 100ns/DIV FIGURE 17. 12V RISING/FALLING PROPAGATION TIME FIGURE 18. 18V RISING/FALLING PROPAGATION TIME 18V BIAS 18V BIAS 12V BIAS 12V BIAS 8V BIAS 8V BIAS 20ns/DIV 20ns/DIV FIGURE 19. RISE TIME FIGURE 20. FALL TIME OUTPUT IMPEDENCE (MΩ) 1000 100 10 1 MAX TEMP = 100°C 0.1 0.01 0 1 2 3 4 5 6 7 VCC (V) FIGURE 21. UVLO OUTPUT HIGH Z vs VCC Submit Document Feedback 9 FIGURE 22. 18V, 1MHz OPERATING IR TEMP FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Post High, Low Dose Rate Radiation Characteristics Unless otherwise specified, VS = 12V, TA = +25°C. This data is typical mean test data post 300kRAD (Si) radiation exposure at a high dose exposure rate of 50 to 300rad(Si)/s and post 50kRAD (Si) radiation exposure at a high dose exposure rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 1.9 0.5 INPUT CURRENT (µA) SUPPLY CURRENT (mA) 0 ICCSB HIGH 1.7 1.5 1.3 1.1 0.9 ICCSB LOW 0.7 0.5 IIHB -0.5 -1.0 -1.5 IILB -2.0 -2.5 IILA -3.0 -3.5 300 0 300 0 krad(Si) krad(Si) FIGURE 24. 18V INPUT CURRENT vs HDR RADIATION 0.360 205 11.49 0.355 200 11.48 0.350 11.47 VOL B 0.345 VOL A 11.46 0.340 11.45 0.335 11.44 0.330 11.43 0.325 VOH B 0.320 11.41 0.315 VOH A 11.40 0 tPHL A 195 tPLH A 190 tPHL B 185 tPLH B 180 175 170 165 0.310 300 krad(Si) PROPAGATION DELAY (ns) 11.50 VOL (V) VOH (V) FIGURE 23. 18V SUPPLY CURRENT vs HDR RADIATION 11.42 IIHA 0 300 krad(Si) FIGURE 25. OUTPUT VOLTAGE vs HDR RADIATION FIGURE 26. PROPAGATION DELAY vs HDR RADIATION 65.0 tf B RISE/FALL TIME (ns) 64.5 tr B 64.0 tf A 63.5 tr A 63.0 62.5 62.0 0 300 krad(Si) FIGURE 27. RISE/FALL TIME vs HDR RADIATION Submit Document Feedback 10 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Post High, Low Dose Rate Radiation Characteristics Unless otherwise specified, VS = 12V, TA = +25°C. This data is typical mean test data post 300kRAD (Si) radiation exposure at a high dose exposure rate of 50 to 300rad(Si)/s and post 50kRAD (Si) radiation exposure at a high dose exposure rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. (Continued) 2.1 0.2 0 ICCSB HIGH 1.7 INPUT CURRENT (µA) SUPPLY CURRENT (mA) 1.9 1.5 1.3 1.1 0.9 ICCSB LOW 0.7 0.5 IIHB -0.2 IIHA -0.4 -0.6 -0.8 -1.0 IILB -1.2 -1.4 0 -1.6 50 IILA 0 50 krad(Si) krad(Si) FIGURE 29. 18V INPUT CURRENT vs LDR RADIATION FIGURE 28. 18V SUPPLY CURRENT vs LDR RADIATION 0.302 11.49 0.300 11.48 0.298 VOH A 11.46 0.296 0.294 11.45 0.292 11.44 0.290 VOH B 11.43 VOL B 0.288 11.42 0.286 11.41 0.284 11.40 VOL (V) VOH (V) 11.47 VOL A 170 PROPAGATION DELAY (ns) 11.50 0.282 50 0 168 tPHL A 166 164 162 tPLH B 160 tPHL B 158 156 154 0 krad(Si) FIGURE 30. OUTPUT VOLTAGE vs LDR RADIATION tPLH A 50 krad(Si) FIGURE 31. PROPAGATION DELAY vs LDR RADIATION 58 RISE/FALL TIME (ns) 56 tr A 54 52 50 tr B tf B 48 46 tf A 44 42 40 0 50 krad(Si) FIGURE 32. RISE/FALL TIME vs LDR RADIATION Submit Document Feedback 11 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Applications Information Power Dissipation and Junction Temperature Functional Description It is possible to exceed the +150°C maximum recommended junction temperature under certain load and power supply conditions. The HS-4424DxH MOSFET drivers are designed for easy implementation with a PWM controller, such as the HS-1825ARH, as the input control signal driver. The HS-4424DxH consist of two independent drivers sharing bias voltage and ground connections at the die level. Undervoltage Lockout and Operating Voltage Range The HS-4424DxH have a guaranteed UVLO of <8V across the operating temperature range. All devices are recommended to operate up to and are characterized and tested at a bias of 18V. The UVLO feature ensures that the internal MOSFET drivers have sufficient gate drive to operate in their saturated mode. When in a UVLO condition the HS-4424DxH outputs are put into a high impedance tri-stated mode. Characterization and testing occurs (as appropriate) at 8V, 12V and 18V and across the -55°C to +125°C operating temperature range. Input Characteristics The HS-4424DxH inputs are designed to be used with low voltage level signals (<1V for a low input level and >3V for a high input level) and also be capable of accepting input voltages up to the VCC level. Output Buffer The HS-4424DxH output buffers are designed to drive >2A of peak output current into high capacitance loads and can be paralleled to increase the output current capability. The output buffer uses a final drive stage comprised of a PNP lower and NPN upper complimentary pair of transistors for the high output current drive. To enhance the pull-up and pull-down of this bipolar pair, they are each paralleled with MOS devices to do so. Submit Document Feedback 12 Calculate power dissipation using Equation 1; (EQ. 1) 2 Pd = V I + 2 C V f Where Pd = Power dissipation V = Supply voltage I = Operating supply current C = Load capacitance f = Operating frequency Calculate junction temperature TJ using Equation 2: T J = Pd Theta JC + T C (EQ. 2) Where TJ = Junction temperature Pd = Power dissipation Theta JC = Junction-to-case thermal resistance TC = Case temperature PCB Layout Guidelines Use a ground plane in the PCB design, connect GND A and GND B pins directly to the ground plane in the same area, preferably close to the IC. Reference all input circuitry including IN A and IN B to a common node and reference all output circuitry including all OUT A and OUT B pins to a common node. Bypass each VCC pin to the ground plane with a 0.047µF ceramic chip capacitor in parallel with a 4.7µF low ESR solid tantalum capacitor. Clamp both OUT pins to VCC, each with a single diode. The 1n5819 (1A, 40V) Schottky diode is recommended. FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Die Characteristics Die Dimensions Assembly Related Information SUBSTRATE POTENTIAL 4890µm x 3370µm (193mils x 133mils) Thickness: 483µm ±25.4µm (19mils ±1mil) Interface Materials Floating (DI) LID POTENTIAL Floating Additional Information GLASSIVATION Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ TOP METALLIZATION WORST CASE CURRENT DENSITY < 2 x 105 A/cm2 TRANSISTOR COUNT Type: AlSiCu Thickness: 16.0kÅ ±2kÅ 125 Weight of Packaged Device BACKSIDE FINISH 0. 591 grams (typical) Silicon Lid Characteristics PROCESS Radiation Hardened Silicon Gate (DI) Finish: Gold Case isolation to any lead: 20 x109Ω (minimum) Metallization Mask Layout GND (5) GND (4) IN A (2) IN B (7) OUT B (10) OUT A (15) OUT B (11) OUT A (14) VCC (12) Submit Document Feedback VCC (13) 13 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 15, 2015 FN8747.2 Added part number HS-4424DEH throughout datasheet. July 1, 2015 FN8747.1 Abs Max ratings on page 4 - removed abs max input current and related text on page 13. ESD Ratings - changed Machine Model from: 1kV to: 200V and Charged Device Model from: 4kV to: 750V Changed over temp limits for UVLO Rising from: MIN/MAX 7.0/7.9 to: 6.9/7.95 and Falling MIN/MAX from: 6.9/7.85 to: 6.8/7.9. Changed over temp 8V, 5mA VOH limit MIN from VS - 0.75 to VS - 0.9. June 8, 2015 FN8747.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 14 FN8747.2 October 15, 2015 HS-4424DRH, HS4424DEH Package Outline Drawing K16.A 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 2, 1/10 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 0.050 (1.27 BSC) PIN NO. 1 ID AREA TOP VIEW 0.022 (0.56) 0.015 (0.38) 0.115 (2.92) 0.045 (1.14) 0.440 (11.18) MAX 0.005 (0.13) MIN 4 0.045 (1.14) 0.026 (0.66) -C- 6 0.285 (7.24) 0.245 (6.22) 0.13 (3.30) MIN SEATING AND BASE PLANE 0.009 (0.23) 0.004 (0.10) -D- 0.370 (9.40) 0.250 (6.35) -H- 0.03 (0.76) MIN LEAD FINISH SIDE VIEW NOTES: 0.006 (0.15) 0.004 (0.10) 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. LEAD FINISH 0.009 (0.23) BASE METAL 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. Measure dimension at all four corners. 0.0015 (0.04) MAX 5. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 0.022 (0.56) 0.015 (0.38) 3 SECTION A-A 2. If a pin one identification mark is used in addition to a tab, the limits of the tab dimension do not apply. 6. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 8. Controlling dimension: INCH. Submit Document Feedback 15 FN8747.2 October 15, 2015