austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Datasheet AS1374 D u a l 2 0 0 m A , L o w - N o i s e , H i g h - P S RR , L o w D r o p o u t R e g u l a t o r s 1 General Description 2 Key Features The AS1374 is a low-noise, low-dropout linear regulator with two separated outputs. Designed to deliver 200mA continuous output current at each output pin, the LDOs can achieve a low 120mV dropout for 200mA load current and are designed and optimized to work with low-cost, small-capacitance ceramic capacitors. Preset Output Voltages: 1.2V to 3.6V (in 50mV steps) An integrated P-channel MOSFET pass transistor allows the devices to maintain extremely low quiescent current (30µA). Stable with 1µF Ceramic Capacitor for any Load The AS1374 uses an advanced architecture to achieve ultra-low output voltage noise of 20µVRMS and a power-supply rejection-ratio of better than 85dB (@ 1kHz). Pull-Down Option in Shutdown (factory set) @ 100Hz to 100kHz al id Output Noise: 20µVRMS Power-Supply Rejection Ratio: 85dB @ 1kHz Guaranteed 200mA output lv Low Dropout: 120mV @ 200mA Load Extremely-Low Quiescent Current: 30µA Two active-High enable pins allows to switch on or off each output independently from each other. am lc s on A te G nt st il Excellent Load/Line Transient Overcurrent and Thermal Protection The AS1374 requires only 1µF output capacitor for stability at any load. 6-bump WLP Package The device is available in a 6-bump WLP package. 3 Applications The devices are ideal for mobile phones, wireless phones, PDAs, handheld computers, mobile phone base stations, Bluetooth portable radios and accessories, wireless LANs, digital cameras, personal audio devices, and any other portable, battery-powered application. Figure 1. AS1374 - Typical Application Circuit Input 2V to 5.5V www.austriamicrosystems.com/LDOs/AS1374 OUT 1 VDD ca Te ch ni C1 1µF 6 EN 1 Output1 1.2V to 3.6V 3 2 AS1374 C2 1µF Output2 1.2V to 3.6V 1 OUT 2 C3 1µF 4 EN 2 5 GND Revision 1.8 1 - 18 AS1374 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments 1 2 al id Figure 2. Pin Assignments (Top View) 3 AS1374 6 lv 5 am lc s on A te G nt st il 4 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number 1 Pin Name OUT 2 2 VDD 3 4 5 Regulated Output Voltage 2. Bypass this pin with a capacitor to GND. See Application Information for capacitor selection. Input Supply OUT 1 Regulated Output Voltage 1. Bypass this pin with a capacitor to GND. See Application Information for capacitor selection. EN 2 Enable 2. Pull this pin to logic low to disable Regulated Output 2 voltage. GND Ground EN 1 Enable 1. Pull this pin to logic low to disable Regulated Output 1 voltage. Te ch ni ca 6 Description www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 2 - 18 AS1374 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Max Units Electrical Parameters VDD to GND -0.3 7 V All other pins to GND -0.3 VDD + 0.3 V Output Short-Circuit Duration Input Current (latch-up immunity) Infinite -100 100 mA Norm: JEDEC 78 kV Norm: MIL 883 E method 3015 Electrostatic Discharge Electrostatic Discharge HBM 2 Comments al id Min am lc s on A te G nt st il Temperature Ranges and Storage Conditions lv Parameter Thermal Resistance JA 201.7 ºC/W Junction Temperature +125 ºC +150 ºC Storage Temperature Range -55 Package Body Temperature 5 ºC 85 % The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. Te ch ni ca Humidity non-condensing +260 Junction-to-ambient thermal resistance is very dependent on application and board-layout. In situations where high maximum power dissipation exists, special attention must be paid to thermal dissipation during board design. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 3 - 18 AS1374 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics VIN = VOUT + 0.5V, VOUT = 2.85V, CIN = COUT = 1µF, Typical values are at TAMB = +25ºC (unless otherwise specified). All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Table 3. Electrical Characteristics Parameter Max Unit TAMB Operating Temperature Range -40 +85 °C VIN Input Voltage Range 2 5.5 V Output Voltage Accuracy IOUT Maximum Output Current IGND Ground Current ILIMIT Current Limit Min IOUT = 1mA, TAMB = +25ºC -1 IOUT = 100µA to 200mA, TAMB = +25ºC -1.5 IOUT = 100µA to 200mA -2.5 Each channel 200 Typ +1 +1.5 mA One channel on, IOUT = 50µA 25 One channel on, IOUT = 200mA 50 1 µA 30 55 µA 300 400 mA 2V VOUT 2.5V, IOUT = 100mA 80 150 mV 90 OUT = short 210 am lc s on A te G nt st il Dropout Voltage % +2.5 lv VOUT Condition al id Symbol Both channels on, IOUT = 0.05mA 30 IQ Quiescent Current Both channels ON, VIN = VOUTNOM - 0.1V, IOUT = 0mA 50 VLNR Line Regulation VIN = (VOUT +0.5V) to 5.5V, IOUT = 1mA 0.02 %/V VLDR Load Regulation IOUT = 1 to 200mA 0.0005 %/mA ISHDN Shutdown Current OUT 1 and OUT 2 disable 0.01 f = 1kHz, IOUT = 10mA 85 f = 10kHz, IOUT = 10mA 65 f = 100kHz, IOUT = 10mA 50 f = 100Hz to 100kHz, ILOAD = 20mA 20 µV 0.01 µA PSRR Ripple Rejection Output Noise Voltage (RMS) Enable Enable Input Bias Current 2 Both channels initially OFF 150 One channel initially OFF 200 ca Enable Exit Delay Enable Logic Low Level 0.4 Enable Logic High Level ni Thermal Protection 2 1.4 µA µA dB µs V V Thermal Shutdown Temperature 160 ºC TSHDN Thermal Shutdown Hysteresis 15 ºC ch TSHDN COUT Output Capacitor Load Capacitor Range 0.47 Maximum ESR Load 10 µF 500 m Te 1. Dropout is defined as VIN - VOUT when VOUT is 100mV below the value of VOUT for VIN = VOUT + 0.5V. 2. Time needed for VOUT to reach 90% of final value. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 4 - 18 AS1374 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VIN = VOUT + 0.5V, VOUT = 2.85V, CIN = COUT = 1µF, TAMB = 25°C (unless otherwise specified). 2.88 2.88 2.87 2.87 2.85 2.84 2.86 2.85 lv 2.86 al id Figure 4. Output Voltage vs. Input Voltage Output Voltage (V) Output Voltage (V) Figure 3. Output Voltage vs. Temperature 2.84 Iload = 1mA CH1 Iload = 10mA 2.83 am lc s on A te G nt st il 2.83 Iload = 100mA CH2 Iload = 200mA 2.82 -45 -30 -15 0 15 30 45 60 75 2.82 3.35 90 3.85 Temperature (°C) 4.35 4.85 5.35 Input Voltage (V) Figure 5. Output Voltage vs. Load Current Figure 6. Output Voltage vs. Input Voltage - Dropout 2.86 2.88 -40°C 2.87 +25°C 2.84 2.86 Output Voltage (V) Output voltage (V) +85°C 2.85 2.84 2.83 2.82 2.82 2.8 2.78 2.76 Iload = 100mA 2.74 2.8 0 25 50 ca 2.81 75 2.72 2.75 100 125 150 175 200 Load Current (mA) 2.9 2.95 3 3.05 ni 100 90 80 PSRR (dB) 100 Te Dropout Voltage (V) 2.85 Figure 8. PSRR vs. Frequency ch 125 2.8 Input Voltage (V) Figure 7. Dropout Voltage vs. Load Current 150 Iload = 200mA 75 50 60 50 40 -40°C 25 70 +25°C 30 +85°C 0 25 50 75 100 125 150 175 200 20 100 Load Current (mA) www.austriamicrosystems.com/LDOs/AS1374 1000 10000 100000 Frequency (Hz) Revision 1.8 5 - 18 AS1374 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. Ground Pin Current vs. Load Current Figure 10. Ground Pin Current vs. Temperature 30 33 31 30 29 28 27 26 25 -40°C 29 28 al id Ground Pin Current (µA) 27 26 +25°C 24 +85°C 23 0 25 50 75 100 125 150 175 25 -45 -30 -15 200 Figure 11. Ground Pin Current vs. Input Voltage; on, no Load one Channel 15 30 45 Figure 12. Ground Pin Current vs. Input Voltage; on, ILOAD = 200mA 50 75 90 one Channel 40 30 20 -40°C 10 +25°C 50 40 30 20 -40°C 10 +25°C +85°C 0 0 1 2 3 4 +85°C 0 3.35 5 3.85 ni Figure 13. Ground Pin Current vs. Input Voltage; both Channels on, no Load 90 90 70 60 Te 50 40 30 20 -40°C +25°C 10 +85°C 0 0 1 2 3 4 5 80 70 60 50 40 30 20 -40°C +25°C 10 0 3.35 Input Voltage (V) www.austriamicrosystems.com/LDOs/AS1374 5.35 100 ch 80 4.85 Figure 14. Ground Pin Current vs. Input Voltage; both Channels on, ILOAD = 200mA Ground Pin Current (µA) 100 4.35 Input Voltage (V) ca Input Voltage (V) Ground Pin Current (µA) 60 60 Ground Pin Current (µA) Ground Pin Current (µA) 60 0 Temperature (°C) am lc s on A te G nt st il Load Current (mA) lv Ground Pin Current (µA) 32 +85°C 3.85 4.35 4.85 5.35 Input Voltage (V) Revision 1.8 6 - 18 AS1374 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 15. Shutdown Current vs. Input Voltage Figure 16. Load Regulation vs. Temperature 60 0 40 30 20 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.0002 -0.0004 -0.0006 -0.0008 0 15 30 45 75 90 Figure 18. Line Regulation vs. Temperature 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -40°C Line Regulation (% / V) 0.15 0.1 0.05 0 -0.05 Iload = 1mA -0.1 Iload = 10mA +25°C +85°C 0 25 50 75 -0.2 -45 -30 -15 100 125 150 175 200 15 30 45 60 75 90 VOUT1 10mV/Div 10mV/Div Figure 20. Load Transient Response near Dropout, IOUT = 200mA IOUT1 IOUT1 100mA/Div Te VOUT2 ch ni Figure 19. Load Transient Response, Crosstalk, between CH1 and CH2, IOUT = 200mA 20µs/Div www.austriamicrosystems.com/LDOs/AS1374 0 Temperature (°C) ca Load Current (mA) Iload = 200mA 20mV/Div -0.2 Iload = 100mA -0.15 100mA/Div -0.15 VOUT1 60 Temperature (°C) Figure 17. Line Regulation vs. Load Current Line Regulation (% / V) CH2 am lc s on A te G nt st il Input Voltage (V) 0.2 CH1 -0.001 -0.0012 -45 -30 -15 5.5 al id +85°C lv +25°C 50 Load Regulation (% / mA) Shutdown Current (nA) -40°C 20µs/Div Revision 1.8 7 - 18 AS1374 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s al id EN1 lv 100µs/Div am lc s on A te G nt st il 100µs/Div 50mA/Div IOUT1 1V/Div VOUT1 500mV/Div VOUT1 IIN 2V/Div 1V/Div 1V/Div 100mA/Div EN1 VOUT1 IIN EN1 Figure 24. Startup of CH1 when CH2 is On 2V/Div Figure 23. Startup of CH1 when CH2 is Off 100mA/Div VOUT1 VIN 2V/Div Figure 22. Shutdown 10mV/Div Figure 21. Line Transient Response 20µs/Div Te ch ni ca 20µs/Div www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 8 - 18 AS1374 Datasheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description 8.1 Output Voltage The AS1374 deliver preset output voltages from 1.2V to 3.6V, in 50mV increments (see Ordering Information on page 17). 8.2 Enable al id Figure 25 shows the block diagram of the AS1374. It identifies the basics of a series linear regulator employing a P-Channel MOSFET as the control element. A stable voltage reference (REF in Figure 25) is compared with an attenuated sample of the output voltage. Any difference between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control element to reduce the difference to a minimum. The error amplifier incorporates additional buffering to drive the relatively large gate capacitance of the series pass Pchannel MOSFET, when additional drive current is required under transient conditions. Input supply variations are absorbed by the series element, and output voltage variations with loading are absorbed by the low output impedance of the regulator. lv The AS1374 feature an active high enable mode to shutdown each output independently. Driving EN 1 low disables Output 1, driving EN 2 low disables Output 2. The disabled Output enters a high-impedance state. am lc s on A te G nt st il Figure 25. AS1374 Block Diagram - EN1 VIN EN2 Enable Logic CH1 Thermal Protection Common Logic + Bandgap Trimmable Reference Overcurrent Protection CH1 GND Overcurrent Protection CH2 Enable Logic CH2 + OUT2 - ni ca AS1374 OUT1 8.3 Current Limit ch The AS1374 include a current limiting circuitry to monitor and control the P-channel MOSFET pass transistor’s gate voltage, thus limiting the device output current to 300mA. Te Note: See Table 3 on page 4 for the recommended min and max current limits. The output can be shorted to ground indefinitely without causing damage to the device. 8.4 Thermal Protection Integrated thermal protection circuitry limits total power dissipation in the AS1374. When the junction temperature (TJ) exceeds +160ºC, the thermal sensor signals the shutdown logic, turning off the P-channel MOSFET pass transistor and allowing the device to cool down. The thermal sensor turns the pass transistor on again after the device’s junction temperature drops by 15ºC, resulting in a pulsed output during continuous thermal-overload conditions. Note: Thermal protection is designed to protect the devices in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of +150ºC. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 9 - 18 AS1374 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information 9.1 Dropout Voltage Dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. At this point, the output voltage change follows the input voltage change. Dropout voltage may be measured at different load currents, but is usually specified at maximum output. As a result, the MOSFET maximum series resistance over temperature is obtained. More generally: (EQ 1) al id VDROPOUT = ILOAD x RSERIES Dropout is probably the most important specification when the regulator is used in a battery application. The dropout performance of the regulator defines the useful “end of life” of the battery before replacement or re-charge is required. am lc s on A te G nt st il lv Figure 26. Graphical Representation of Dropout Voltage VIN VOUT VIN=VOUT(TYP)+0.5V Dropout Voltage VOUT 100mV VIN VOUT ca VIN ni Figure 26 shows the variation of VOUT as VIN is varied for a certain load current. The practical value of dropout is the differential voltage (VOUTVIN) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential. ch 9.2 Efficiency Te Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is directly related to quiescent current and dropout voltage. Efficiency is given by: V LOAD I LOAD Efficiency = ----------------------------------------- 100 % V IN I Q + I LOAD (EQ 2) Where: IQ = quiescent current of LDO www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 10 - 18 AS1374 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.3 Power Dissipation Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current required to bias the internal voltage reference and the internal error amplifier, and is calculated as: PD MAX Seriespass = I LOAD MAX V IN MAX – V OUT MIN Watts (EQ 3) Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as: PD MAX Bias = V IN MAX I Q Watts Total LDO power dissipation is calculated as: PD MAX Total = PD MAX Seriespass + PD MAX Bias Watts 9.4 Junction Temperature al id (EQ 4) (EQ 5) lv Under all operating conditions, the maximum junction temperature should not be allowed to exceed 125°C (unless otherwise specified in the datasheet). Limiting the maximum junction temperature requires knowledge of the heat path from junction to case (JC°C/W fixed by the IC manufacturer), and adjustment of the case to ambient heat path (CA°C/W) by manipulation of the PCB copper area adjacent to the IC position. am lc s on A te G nt st il Figure 27. Package Physical Arrangements CS-WLP Package Package Chip Transfer Layer PCB Te ch ni ca Solder Balls www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 11 - 18 AS1374 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 28. Steady State Heat Flow Equivalent Circuit Package TC°C RJC Ambient TA°C PCB/Heatsink TS°C RCS RSA am lc s on A te G nt st il lv Chip Power al id Junction TJ°C Total Thermal Path Resistance: RJA = RJC + RCS + RSA (EQ 6) TJ = (PD(MAX) x RJA) + TAMB ºC (EQ 7) Junction Temperature (TJ ºC) is determined by: 9.5 Explanation of Steady State Specifications 9.5.1 Line Regulation Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain of the error amplifier. More generally: (EQ 8) ca V OUT Line Regulation = ----------------- and is a pure number V IN In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is available with numerous output voltage trim options. (EQ 9) Load Regulation ch 9.5.2 ni V OUT 100 Line Regulation = ----------------- ------------- % / V V IN V OUT Te Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output resistance of the regulator. More generally: V OUT Load Regulation = ----------------- and is units of ohms () I OUT (EQ 10) In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is available with numerous output voltage trim options. V OUT 100 Load Regulation = ----------------- ------------- % / mA I OUT V OUT www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 (EQ 11) 12 - 18 AS1374 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.5.3 Setting Accuracy Accuracy of the final output voltage is determined by the accuracy of the ratio of R1 and R2, the reference accuracy and the input offset voltage of the error amplifier. When the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification. When the regulator has a SET terminal, the output voltage may be adjusted externally. In this case, the tolerance of the external resistor network must be incorporated into the final accuracy calculation. Generally: R1 R1 V OUT = V SET V SET 1 + --------------------- R2 R2 9.5.4 Total Accuracy al id The reference tolerance is given both at 25°C and over the full operating temperature range. (EQ 12) Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally: 9.6 Explanation of Dynamic Specifications Power Supply Rejection Ratio (PSRR) am lc s on A te G nt st il 9.6.1 (EQ 13) lv Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low quiescent current conditions. Generally: V OUT PSRR = 20Log ----------------- dB using lower case to indicate AC values V IN (EQ 14) Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally. The AS1374 is designed to deliver low noise and high PSRR, with low quiescent currents in battery-powered systems. The power-supply rejection is 85dB at 1kHz and 50dB at 100kHz. When operating from sources other than batteries, improved supply-noise rejection and transient response are achieved by increasing the values of the input and output capacitors. Additional passive LC filtering at the input can provide enhanced rejection at high frequencies. 9.6.2 Output Capacitor ESR The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown either by a plot of stable ESR versus load current, or a maximum value in the datasheet. ca Some ceramic capacitors exhibit large capacitance and ESR variations with variations in temperature. Z5U and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10°C. With X7R or X5R capacitors, a 1µF capacitor should be sufficient at all operating temperatures. Larger output capacitor values (10µF) help to reduce noise and improve load transient-response, stability and power-supply rejection. Input Capacitor ni 9.6.3 ch An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1369 power supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. 9.6.4 Noise Te The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will produce system problems. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 13 - 18 AS1374 Datasheet 9.6.5 Transient Response The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally: V TRANSIENT = I OUTPUT R ESR Units are Volts, Amps, Ohms. (EQ 15) al id Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Do remember to keep the ESR within stability recommendations when reducing ESR by adding multiple parallel output capacitors. After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change. This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of: (EQ 16) lv T V TRANSIENT = I OUTPUT R ESR + ----------------- Units are Volts, Seconds, Farads, Ohms. C LOAD Where: CLOAD is output capacitor T= Propagation Delay of the LDO am lc s on A te G nt st il This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load current step produces 50mV output drop if the LDO response is 1µsec and the load cap is 1µF. There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification discussed above. 9.6.6 Turn On Time This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator min and max limits. Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA). 9.6.7 Thermal Protection Te ch ni ca To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device. Die temperature is measured, and when a 160°C threshold is reached, the device enters shutdown. When the die cools sufficiently, the device will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15°C prevents low frequency oscillation between start-up and shutdown around the temperature threshold. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 14 - 18 AS1374 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The AS1374 is available in a 6-bump WLP package. Top through view am lc s on A te G nt st il lv Bottom view (ball side) al id Figure 29. 6-bump WLP Package Te ch ni ca ASSH XXXX Notes: 1. ccc – Coplanarity 2. All dimensions are in µm. www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 15 - 18 AS1374 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Revision History Revision Date Owner Description Initial revisions 11 Oct, 2011 1.8 12 Dec, 2011 Changes made across the document afe Updated equations in Power Dissipation section Te ch ni ca am lc s on A te G nt st il lv Note: Typos may not be explicitly mentioned under revision history. al id 1.7 www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 16 - 18 AS1374 Datasheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information The devices are available as the standard products shown in Table 4. Table 4. Ordering Information Marking Output Voltage 1 Output Voltage 2 Delivery Form Package AS1374-BWLT-285 ASSH 2.85V 2.85V Tape and Reel 6-bump WLP AS1374-BWLT1833 ASSJ 1.8V 3.3V Tape and Reel 6-bump WLP AS1374-BWLT1818 ASSP 1.8V 1.8V Tape and Reel AS1374-BWLT1218 ASSK 1.2V 1.8V Tape and Reel AS1374-BWLT1214 ASSY 1.2V 1.4V Tape and Reel AS1374-BWLT18285 ASSZ 1.8V 2.85V Tape and Reel AS1374-BWLT1212 ASSW 1.2V 1.2V Tape and Reel 6-bump WLP AS1374-BWLT1827 ASTB 1.8V 2.7V Tape and Reel 6-bump WLP 1 ASTF 1.5V 3.3V Tape and Reel 6-bump WLP ASTG 1.8V 2.0V Tape and Reel 6-bump WLP ASTH 1.8V 2.1V Tape and Reel 6-bump WLP ASTI 2.5V 3.3V Tape and Reel 6-bump WLP ____ tbd tbd Tape and Reel 6-bump WLP 1 AS1374-BWLT1820 1 AS1374-BWLT1821 1 AS1374-BWLT2533 2 AS1374-BWLT 6-bump WLP 6-bump WLP 6-bump WLP lv 6-bump WLP am lc s on A te G nt st il AS1374-BWLT1533 al id Ordering Code 1. On request 2. Non-standard devices from 1.2V to 3.6V are available in 50mV steps. For more information and inquiries contact http://www.austriamicrosystems.com/contact Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support Te ch ni ca For further information and requests, please contact us mailto:[email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 17 - 18 AS1374 Datasheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. ca Contact Information am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Headquarters ni austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria ch Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 Te For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 18 - 18