Vishay IRF820ALPBF Power mosfet Datasheet

IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
500
RDS(on) (Max.) (Ω)
VGS = 10 V
3.0
Qg (Max.) (nC)
17
Qgs (nC)
4.3
Qgd (nC)
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Single
COMPLIANT
• Effective Coss specified
D
• Lead (Pb)-free Available
APPLICATIONS
D2PAK
(TO-263)
I2PAK
(TO-262)
RoHS*
• Fully Characterized Capacitance and Avalanche Voltage
and Current
8.5
Configuration
Available
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
G
• High Speed Power Switching
G
TYPICAL SMPS TOPOLOGIES
D
• Two Transistor Forward
S
S
• Half Bridge and Full Bridge
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
I2PAK (TO-262)
IRF820ASPbF
IRF820ALPbF
SiHF820AS-E3
SiHF820AL-E3
IRF820AS
IRF820AL
SiHF820AS
SiHF820AL
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
VDS
VGS
500
± 30
2.5
1.6
10
0.4
10
140
2.5
5.0
50
3.4
- 55 to + 150
300d
10
1.1
Drain-Source Voltage
Gate-Source Voltage
VGS at 10 V
Continuous Drain Current
Pulsed Drain Currenta, e
Linear Derating Factor
Avalanche Currenta
Single Pulse Avalanche Energyb, e
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
IAR
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
for 10 s
6-32 or M3 screw
UNIT
V
A
W/°C
A
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 45 mH, RG = 25 Ω, IAS = 2.5 A (see fig. 12).
c. ISD ≤ 2.5 A, dI/dt ≤ 270 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Uses IRF820A/SiHF820A data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
WORK-IN-PROGRESS
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IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient (PCB
Mounted, steady-state)a
PARAMETER
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
2.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAd
-
0.60
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 1.5 Ab
VGS = 10 V
VDS = 50 V, ID = 1.5 Ad
µA
-
-
3.0
Ω
1.4
-
-
S
-
340
-
-
53
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
-
2.7
-
VDS = 1.0 V, f = 1.0 MHz
-
490
-
VDS = 400 V, f = 1.0 MHz
-
15
-
VDS = 0 V to 400 Vc, d
-
28
-
-
-
17
ID = 2.5 A, VDS = 400 V,
see fig. 6 and 13b, d
-
-
4.3
pF
nC
Gate-Drain Charge
Qgd
-
-
8.5
Turn-On Delay Time
td(on)
-
8.1
-
-
12
-
-
16
-
-
13
-
-
-
2.5
-
-
10
-
-
1.6
-
330
500
ns
-
760
1140
µC
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 250 V, ID = 2.5 A,
RG = 21 Ω, RD = 97 Ω, see fig. 10b, d
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 2.5 A, VGS = 0 Vb
TJ = 25 °C, IF = 2.5 A, dI/dt = 100 A/µsb, d
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRF820A/SiHF820A data and test conditions.
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Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
1
0.1
4.5V
20μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
TJ = 150 ° C
1
TJ = 25 ° C
0.1
0.01
4.0
Fig. 1 - Typical Output Characteristics
I D , Drain-to-Source Current (A)
1
4.5V
20μs PULSE WIDTH
TJ = 150 ° C
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
5.0
VGS , Gate-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
10
V DS = 50V
20μs PULSE WIDTH
ID = 2.5A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance(pF)
1000
Ciss
100
Coss
10
10
ISD , Reverse Drain Current (A)
10000
TJ = 150 ° C
1
TJ = 25 ° C
Crss
1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
0.8
1.0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
VDS = 400V
VDS = 250V
VDS = 100V
OPERATION IN THIS AREA LIMITED
BY RDS(on)
15
10
5
10
0
4
8
12
16
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
10us
100us
1
FOR TEST CIRCUIT
SEE FIGURE 13
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0.6
100
ID = 2.5A
0
V GS = 0 V
VSD ,Source-to-Drain Voltage (V)
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
20
0.1
0.4
0.1
1ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
RD
VDS
3.0
VGS
ID , Drain Current (A)
D.U.T.
RG
2.5
+
- VDD
10 V
2.0
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1.5
Fig. 10a - Switching Time Test Circuit
1.0
VDS
90 %
0.5
0.0
25
50
75
100
125
10 %
VGS
150
TC , Case Temperature ( ° C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
PDM
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
Fig. 12b - Unclamped Inductive Waveforms
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IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
300
TOP
250
BOTTOM
ID
1.1A
1.6A
2.5A
200
150
100
50
700
V DSav , Avalanche Voltage ( V )
EAS , Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
650
600
550
0
25
50
75
100
125
150
0.0
0.5
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
1.0
1.5
2.0
2.5
IAV , Avalanche Current ( A)
Fig. 12d - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91058.
Document Number: 91058
S-Pending-Rev. A, 02-Jun-08
www.vishay.com
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
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otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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