AD AD7892BR-2 Lc2mos single supply, 12-bit 600 ksps adc Datasheet

a
FEATURES
Fast 12-Bit ADC with 1.47 ␮s Conversion Time
600 kSPS Throughput Rate (AD7892-3)
500 kSPS Throughput Rate (AD7892-1, AD7892-2)
Single Supply Operation
On-Chip Track/Hold Amplifier
Selection of Input Ranges:
ⴞ10 V or ⴞ5 V for AD7892-1
0 V to +2.5 V for AD7892-2
ⴞ2.5 V for AD7892-3
High Speed Serial and Parallel Interface
Low Power, 60 mW typ
Overvoltage Protection on Analog Inputs (AD7892-1
and AD7892-3)
LC2MOS Single Supply,
12-Bit 600 kSPS ADC
AD7892
FUNCTIONAL BLOCK DIAGRAM
REF OUT/REF IN
VDD
2k⍀
+2.5V
AD7892
MODE
REFERENCE
DB0
DB2
DB3/RFS
12-BIT
DB4/SCLK
DB5/SDATA
DB10/LOW
DB11/LOW
ADC
VIN1
SIGNAL
VIN2
SCALING
TRACK/HOLD
CLOCK
CONTROL LOGIC
CS
GENERAL DESCRIPTION
The AD7892 is a high speed, low power, 12-bit A/D converter
that operates from a single +5 V supply. The part contains a
1.47 µs successive approximation ADC, an on-chip track/hold
amplifier, an internal +2.5 V reference and on-chip versatile
interface structures that allow both serial and parallel connection to a microprocessor. The part accepts an analog input range
of ± 10 V or ± 5 V (AD7892-1), 0 V to +2.5 V (AD7892-2) and
± 2.5 V (AD7892-3). Overvoltage protection on the analog inputs
for the AD7892-1 and AD7892-3 allows the input voltage to go
to ± 17 V or ± 7 V respectively without damaging the ports.
The AD7892 offers a choice of two data output formats: a
single, parallel, 12-bit word or serial data. Fast bus access times
and standard control inputs ensure easy parallel interface to
microprocessors and digital signal processors. A high speed
serial interface allows direct connection to the serial ports of
microcontrollers and digital signal processors.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.
RD
EOC CONVST
AGND DGND
STANDBY
The AD7892 is fabricated in Analog Devices’ Linear Compatible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. It is available in a 24-lead, 0.3" wide, plastic or hermetic
DIP or in a 24-lead SOIC.
PRODUCT HIGHLIGHTS
1. The AD7892-3 features a conversion time of 1.47 µs and a
track/hold acquisition time of 200 ns. This allows a throughput rate for the part up to 600 kSPS. The AD7892-1 and
AD7892-2 operate with throughput rates of 500 kSPS.
2. The AD7892 operates from a single +5 V supply and consumes 60 mW typ making it ideal for low power and portable
applications.
3. The part offers a high speed, flexible interface arrangement
with parallel and serial interfaces for easy connection to
microprocessors, microcontrollers and digital signal
processors.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7892* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DESIGN RESOURCES
View a parametric search of comparable parts.
• AD7892 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• Quality And Reliability
• AD7892 Evaluation Board
• Symbols and Footprints
DOCUMENTATION
DISCUSSIONS
Application Notes
View all AD7892 EngineerZone Discussions.
• AN-414: Low Cost, Low Power Devices for HDSL
Applications
SAMPLE AND BUY
Data Sheet
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2
• AD7892: LC MOS Single Supply, 12-Bit 600 kSPS ADC Data
Sheet
• AD7892: Military Data Sheet
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V ⴞ 5%, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T
AD7892–SPECIFICATIONS (Vunless= +5otherwise
noted.)
DD
MIN
to TMAX
A Versions1
B Versions
S Version2
Unit
70
–78
–79
70
–78
–79
70
–78
–79
dB min
dB max
dB max
typ –84 dB
–78
–78
–78
–78
–78
–78
dB max
dB max
fa = 49 kHz, fb = 50 kHz
typ –84 dB
typ –84 dB
fIN = 100 kHz. fSAMPLE = 600 kSPS
70
–78
–79
70
–78
–79
dB min
dB max
dB max
–78
–78
–78
–78
dB max
dB max
12
12
12
Bits
12
± 1.5
±1
12
±1
±1
12
±1
±1
Bits
LSB max
LSB max
±4
±4
±3
±4
±4
±2
±5
±5
±3
LSB max
LSB max
LSB max
±4
±4
±4
±4
±4
±3
±5
±4
±5
±3
±5
±4
LSB max
LSB max
± 10
±5
8
± 10
±5
8
± 10
±5
8
Volts
Volts
kΩ min
Input Applied to VIN1 with VIN2 Grounded
Input Applied to VIN1 and VIN2
Input Applied to VIN1 with VIN2 Grounded
0 to +2.5
10
± 50
0 to +2.5
10
± 50
0 to +2.5
50
± 50
Volts
nA max
mV max
Input Applied to VIN1
± 2.5
2
± 2.5
2
Volts
kΩ min
Input Applied to VIN1
REFERENCE OUTPUT/INPUT
REF IN Input Voltage Range
Input Impedance
Input Capacitance4
REF OUT Output Voltage
REF OUT Error @ +25°C
TMIN to TMAX
REF OUT Temperature Coefficient
REF OUT Output Impedance
2.375/2.625
1.6
10
2.5
± 10
± 20
25
5.5
2.375/2.625
1.6
10
2.5
± 10
± 20
25
5.5
2.375/2.625
1.6
10
2.5
± 10
± 25
25
5.5
V min/V max
kΩ min
pF max
V nom
mV max
mV max
ppm/°C typ
kΩ nom
2.5 V ± 5%
Resistor Connected to Internal Reference Node
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
2.4
0.8
± 10
10
2.4
0.8
± 10
10
2.4
0.8
± 10
10
V min
V max
µA max
pF max
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
Parameter
DYNAMIC PERFORMANCE
AD7892-1, AD7892-2
Signal to (Noise + Distortion) Ratio3
Total Harmonic Distortion3
Peak Harmonic or Spurious Noise3
Intermodulation Distortion3
2nd Order Terms
3rd Order Terms
AD7892-3
Signal to (Noise + Distortion) Ratio3
Total Harmonic Distortion3
Peak Harmonic or Spurious Noise3
Intermodulation Distortion3
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Minimum Resolution for Which No
Missing Codes Are Guaranteed
Relative Accuracy3
Differential Nonlinearity3
AD7892-1
Positive Full-Scale Error3
Negative Full-Scale Error3
Bipolar Zero Error3
AD7892-3
Positive Full-Scale Error3
Negative Full-Scale Error3
Bipolar Zero Error3
AD7892-2
Positive Full-Scale Error3
Unipolar Offset Error3
ANALOG INPUT
AD7892-1
Input Voltage Range
Input Voltage Range
Input Resistance
AD7892-2
Input Voltage Range on VIN1
Input Current
Input Voltage Range on VIN2
AD7892-3
Input Voltage Range on VIN1
Input Resistance
Test Conditions/Comments
fIN = 100 kHz. fSAMPLE = 500 kSPS
fa = 49 kHz, fb = 50 kHz
LSB max
LSB max
LSB max
–2–
REV. C
AD7892
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
Floating-State Leakage Current
Floating-State Capacitance4
Output Coding
AD7892-1 and AD7892-3
AD7892-2
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time3
Conversion Time
Track/Hold Acquisition Time3
POWER REQUIREMENTS
VDD
IDD5
Normal Operation
Standby Mode6
AD7892-2
AD7892-3, AD7892-1
Power Dissipation5
Normal Operation
Standby Mode6
AD7892-2
AD7892-3, AD7892-1
A Versions
1
2
B Versions
S Version
Unit
Test Conditions/Comments
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 200 µA
ISINK = 1.6 mA
± 10
15
± 10
15
± 10
15
µA max
pF max
Two’s Complement
Straight (Natural) Binary
1.68
0.32
µs max
µs max
µs max
µs max
AD7892-3
AD7892-3
AD7892-1 and AD7892-2
AD7892-1 and AD7892-2
+5
+5
V nom
± 5% for Specified Performance
18
18
19
mA max
250
80
250
80
100
µA typ
µA max
typ 15 µA
90
90
95
mW max
VDD = +5 V. Typically 60 mW
1.25
400
1.25
400
500
mW typ
µW max
VDD = +5 V. Typically 75 µW
1.47
0.2
1.6
0.4
1.47
0.2
1.6
0.4
+5
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2
S Version available on AD7892-1 and AD7892-2 only.
3
See Terminology.
4
Sample tested @ +25°C to ensure compliance.
5
These normal mode and standby mode currents are achieved with resistors (in the range 10 kΩ to 100 kΩ) to either DGND or V DD on Pins 8, 9, 16 and 17.
6
A conversion should not be initiated on the part within 30 µs of exiting standby mode.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
AD7892-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V
AD7892-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
AD7892-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
REV. C
–3–
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD7892
TIMING CHARACTERISTICS1, 2 (V
Parameter
tCONV
tACQ
Parallel Interface
t1
t2
t3
t4
t5
t6 3
t7 4
t8
t9
Serial Interface
t10
t113
t12
t13
t143
t153
t16
t174
t17A4
A, B
Versions
DD
= +5 V ⴞ 5%, AGND = DGND = 0 V, REF IN = +2.5 V)
S
Version
Unit
Test Conditions/Comments
Conversion Time for AD7892-3
Conversion Time for AD7892-1, AD7892-2
Acquisition Time for AD7892-3
Acquisition Time for AD7892-1, AD7892-2
1.47
1.6
200
400
320
µs max
µs max
ns min
ns min
35
60
0
0
35
35
5
30
0
200
45
60
0
0
45
40
5
40
0
200
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
CONVST Pulsewidth
EOC Pulsewidth
EOC Falling Edge to CS Falling Edge Setup Time
CS to RD Setup Time
Read Pulsewidth
Data Access Time After Falling Edge of RD
Bus Relinquish Time After Rising Edge of RD
30
25
25
25
5
25
20
0
30
0
30
35
30
25
25
5
30
30
0
30
0
30
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
1.68
CS to RD Hold Time
RD to CONVST Setup Time
Bus Relinquish Time after Rising Edge of SCLK
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 2 and 3.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5
Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min.
Specifications subject to change without notice.
1.6mA
TO
+1.6V
OUTPUT
PIN
50pF
200␮A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. C
AD7892
ORDERING GUIDE
Model
Input
Range
Sample
Rate
AD7892AN-1
AD7892BN-1
AD7892AR-1
AD7892BR-1
AD7892SQ-1
AD7892AN-2
AD7892BN-2
AD7892AR-2
AD7892BR-2
AD7892AN-3
AD7892BN-3
AD7892AR-3
AD7892BR-3
EVAL-AD7892-2CB2
EVAL-AD7892-3CB2
EVAL-CONTROL BOARD3
± 5 V or ± 10 V
± 5 V or ± 10 V
± 5 V or ± 10 V
± 5 V or ± 10 V
± 5 V or ± 10 V
0 V to +2.5 V
0 V to +2.5 V
0 V to +2.5 V
0 V to +2.5 V
± 2.5 V
± 2.5 V
± 2.5 V
± 2.5 V
Evaluation Board
Evaluation Board
Controller Board
500 kSPS
500 kSPS
500 kSPS
500 kSPS
500 kSPS
500 kSPS
500 kSPS
500 kSPS
500 kSPS
600 kSPS
600 kSPS
600 kSPS
600 kSPS
Relative
Accuracy
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
Temperature
Range
Package
Option1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-24
N-24
R-24
R-24
Q-24
N-24
N-24
R-24
R-24
N-24
N-24
R-24
R-24
NOTES
1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
These boards can be used as stand-alone evaluation boards or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators.
REV. C
–5–
AD7892
PIN FUNCTION DESCRIPTION
Pin
No.
Mnemonic
Description
1
VDD
Positive Supply Voltage, +5 V ± 5%.
2
STANDBY
Standby Input. Logic Input. With this input at a logic high, the part is in its normal operating
mode; with this input at a logic low, the part is placed in its standby or power-down mode, which
reduces power consumption to 5 mW typical.
3
VIN2
Analog Input 2. For the AD7892-1, this input either connects to AGND or to VIN1 to determine
the analog input voltage range. With VIN2 connected to AGND on the AD7892-1, the analog input
range at the VIN1 input is ± 10 V. With VIN2 connected to VIN1 on the AD7892-1, the analog input
range to the part is ± 5 V.
For the AD7892-2 and AD7892-3, this input can be left unconnected but must not be connected
to a potential other than AGND.
4
VIN1
Analog Input 1. The analog input voltage to be converted by the AD7892 is applied to this input.
For the AD7892-1, the input voltage range is either ± 5 V or ± 10 V depending on where the VIN2
input is connected. For the AD7892-2, the voltage range on the VIN1 input is 0 V to +2.5 V with
respect to the voltage appearing at the VIN2 input. For the AD7892-3, the voltage range on the VIN1
input is ± 2.5 V.
5
REF OUT/REF IN
Voltage Reference Output/Input. The part can be used with either its own internal reference or with
an external reference source. The on-chip +2.5 V reference is provided at this pin. When using this
internal reference as the reference source for the part, REF OUT should be decoupled to AGND
with a 0.1 µF disc ceramic capacitor. The output impedance of this reference source is typically
5.5 kΩ. When using an external reference source as the reference voltage for the part, the reference
source should be connected to this pin. This overdrives the internal reference and provides the
reference source for the part. The REF IN input is buffered on-chip but must be able to sink or
source current through the resistor to the output of the on-chip reference. The nominal reference
voltage for correct operation of the AD7892 is +2.5 V.
6
AGND
Analog Ground. Ground reference for track/hold, comparator and DAC.
7
MODE
Mode. Control input which determines the interface mode for the AD7892. With this pin at a logic
low, the device is in its serial interface mode; with this pin at a logic high, the device is in its parallel
interface mode.
8
DB11/LOW
Data Bit 11/Test Pin. When the device is in its parallel mode, this pin is Data Bit 11 (MSB), a
three-state TTL-compatible output. When the device is in its serial mode, this is used as a test pin
which must be tied to a logic low for correct operation of the AD7892.
9
DB10/LOW
Data Bit 10/Test Pin. When the device is in its parallel mode, this pin is Data Bit 10, a three-state
TTL-compatible output. When the device is in its serial mode, this is used as a test pin which must
be tied to a logic low for correct operation of the AD7892.
10
DB9
Data Bit 9. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
11
DB8
Data Bit 8. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
12
DB7
Data Bit 7. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
13
DB6
Data Bit 6. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
14
DGND
Digital Ground. Ground reference for digital circuitry.
15
DB5/SDATA
Data Bit 5/Serial Data. When the device is in its parallel mode, this pin is Data Bit 5, a three-state
TTL-compatible output. When the device is in its serial mode, this becomes the serial data output
line. Sixteen bits of serial data are provided with four leading zeros preceding the 12 bits of valid
data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output
coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for
AD7892-2.
–6–
REV. C
AD7892
Pin
No.
Mnemonic
Description
16
DB4/SCLK
Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state
TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,
SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial
data from the AD7892. Serial data is clocked out from the output shift register on the rising edges
of SCLK after RFS goes low.
17
DB3/RFS
Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data
Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the
receive frame synchronization input with RFS provided externally to obtain serial data from the
AD7892.
18
DB2
Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
19
DB1
Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
20
DB0
Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for
AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left
unconnected when the device is in its serial mode.
21
RD
Read. Active low logic input which is used in conjunction with CS low to enable the data outputs.
22
CS
Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs.
23
EOC
End-of-Conversion. Active low logic output indicating converter status. The end of conversion is
signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns.
24
CONVST
Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold
mode and starts conversion.
PIN CONFIGURATION
DIP and SOIC
VDD
1
24 CONVST
STANDBY
2
23 EOC
VIN2
3
22 CS
VIN1
4
21 RD
REF OUT/REF IN
5
AGND
6
MODE
7
DB11/LOW
8
DB10/LOW
9
20 DB0 (LSB)
AD7892
19 DB1
TOP VIEW
18 DB2
(Not to Scale)
17 DB3/RFS
16 DB4/SCLK
DB9 10
REV. C
15 DB5/SDATA
DB8 11
14 DGND
DB7 12
13 DB6
–7–
AD7892
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
Relative Accuracy
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7892-1)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × REF IN – 3/2 LSB (± 10 V range)
or 2 × REF IN – 3/2 LSB (± 5 V range) after the bipolar zero
error has been adjusted out.
Thus for a 12-bit converter, this is 74 dB.
Positive Full-Scale Error (AD7892-2)
Total Harmonic Distortion
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (REF IN – 3/2 LSB) after the unipolar offset error has been adjusted out.
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7892, it is defined
as:
2
2
2
2
V 2 +V 3 +V 4 +V 5 +V 6
THD (dB) = 20 log
V1
2
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Positive Full-Scale Error (AD7892-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (REF IN – 3/2 LSB) after the bipolar
zero error has been adjusted out.
Bipolar Zero Error (AD7892-1, AD7892-3)
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal (AGND – 1/2 LSB).
Unipolar Offset Error (AD7892-2)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal (AGND + 1/2 LSB).
Negative Full-Scale Error (AD7892-1)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal –4 × REF IN + 1/2 LSB (± 10 V
range) or –2 × REF IN + 1/2 LSB (± 5 V range) after bipolar
zero error has been adjusted out.
Intermodulation Distortion
Negative Full-Scale Error (AD7892-3)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal – REF IN + 1/2 LSB after bipolar
zero error has been adjusted out.
The AD7892 is tested using two input frequencies away from
the bottom end of the input bandwidth. In this case, the second
and third order terms are of different significance. The second
order terms are usually distanced in frequency from the original
sine waves while the third order terms are usually at a frequency
close to the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification where it
is the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within ±1/2 LSB,
after the end of conversion (the point at which the track/hold
returns to track mode). It also applies to situations where there
is a step input change on the input voltage applied to the VIN
input of the AD7892. It means that the user must wait for the
duration of the track/hold acquisition time after the end of conversion or after a step input change to VIN before starting another
conversion, to ensure that the part operates to specification.
–8–
REV. C
AD7892
CIRCUIT DESCRIPTION
The AD7892 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, reference, A/D
converter and versatile interface logic functions on a single chip.
The signal scaling on the AD7892-1 allows the part to handle
either ± 5 V or ± 10 V input signals while operating from a single
+5 V supply. The AD7892-2 handles a 0 V to +2.5 V analog
input range, while signal scaling on the AD7892-3 allows it to
handle ±2.5 V input signals when operating from a single supply.
The part requires a +2.5 V reference which can be provided from
the part’s own internal reference or from an external reference
source.
Conversion is initiated on the AD7892 by pulsing the CONVST
input. On the rising edge of CONVST, the track/hold goes
from track mode to hold mode and the conversion sequence is
started. At the end of conversion (falling edge of EOC), the
track/hold returns to tracking mode and the acquisition time
begins. Conversion time for the part is 1.47 µs (AD7892-3) and
the track/hold acquisition time is 200 ns (AD7892-3). This allows
the AD7892-3 to operate at throughput rates up to 600 kSPS.
The AD7892-1 and AD7892-2 are specified with a 1.6 µs conversion and 400 ns acquisition time allowing a throughput rate
of 500 kSPS.
Track/Hold Section
The track/hold amplifier on the AD7892 allows the ADC to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 600 kHz (i.e., the track/
hold can handle input frequencies in excess of 300 kHz).
The track/hold amplifier acquires an input signal to 12-bit accuracy in less than 200 ns. The operation of the track/hold is
essentially transparent to the user. The track/hold amplifier
goes from its tracking mode to its hold mode on the rising edge
of CONVST. The aperture time for the track/hold (i.e., the
delay time between the external CONVST signal and the track/
hold actually going into hold) is typically 15 ns. At the end of
conversion, the part returns to its tracking mode. The acquisition time of the track/hold amplifier begins at this point.
Reference Section
The AD7892 contains a single reference pin, labelled REF OUT/
REF IN, which either provides access to the part’s own +2.5 V
reference or to which an external +2.5 V reference can be connected to provide the reference source for the part. The part is
specified with a +2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7892’s transfer
function and will add to the specified full-scale errors on the
part. On the AD7892-1 and AD7892-3, it will also result in an
offset error injected in the attenuator stage.
The AD7892 contains an on-chip +2.5 V reference. To use this
reference as the reference source for the AD7892, simply connect a 0.1 µF disc ceramic capacitor from the REF OUT/
REF IN pin to AGND. The voltage that appears at this pin is
internally buffered before being applied to the ADC. If this
reference is required for use external to the AD7892, it should
be buffered as the part has a FET switch in series with the reference output resulting in a source impedance for this output of
5.5 kΩ nominal. The tolerance on the internal reference is
± 10 mV at 25°C with a typical temperature coefficient of
25 ppm/°C and a maximum error over temperature of ± 25 mV.
If the application requires a reference with a tighter tolerance or
the AD7892 needs to be used with a system reference, then the
user has the option of connecting an external reference to this
REF OUT/REF IN pin. The external reference will effectively
overdrive the internal reference and thus provide the reference
source for the ADC. The reference input is buffered before
being applied to the ADC with the maximum input current is
± 100 µA. Suitable reference sources for the AD7892 include the
AD680, AD780 and REF43 precision +2.5 V references.
INTERFACING
The part provides two interface options, a 12-bit parallel interface and a three-wire serial interface. The required interface
mode is selected via the MODE pin. The two interface modes
are discussed in the following sections.
Parallel Interface Mode
The parallel interface mode is selected by tying the MODE
input to a logic high. Figure 2 shows a timing diagram illustrating the operational sequence of the AD7892. The on-chip
track/hold goes into hold mode, and conversion is initiated on
the rising edge of the CONVST signal. When conversion is
complete, the end of conversion line (EOC) pulses low to indicate that new data is available in the AD7892’s output register.
This EOC line can be used to drive an edge-triggered interrupt
of a microprocessor. The falling edge of the RD signal should
occur 200 ns prior to the next rising edge of CONVST. CS and
RD going low accesses the 12-bit conversion result. In systems
where the part is interfaced to a gate array or ASIC, this EOC
CONVST (I)
tACQ
t1
t2
EOC (O)
tCONV
t9
t3
CS (I)
t4
t8
t5
RD (I)
t6
THREE-STATE
DB0–DB11 (O)
t7
VALID
DATA
NOTE:
I = INPUT; O = OUTPUT
Figure 2. Parallel Mode Timing Diagram
REV. C
–9–
THREE-STATE
AD7892
pulse can be applied to the CS and RD inputs to latch data out
of the AD7892 and into the gate array or ASIC. This eliminates
the logic required in the gate array or ASIC to recognize the end
of conversion and generate the read signal for the AD7892. To
obtain optimum performance from the AD7892, it is not recommended to tie CS and RD permanently low as this keeps the
three-state active during conversion.
Serial Interface Mode
The AD7892 is configured for serial mode interfacing by tying
the MODE input low. It provides for a three-wire, serial link
between the AD7892 and industry-standard microprocessors,
microcontrollers and digital signal processors. SCLK and RFS
of the AD7892 are inputs, and the AD7892’s serial interface is
designed for direct interface to systems that provide a serial
clock input that is synchronized to the serial data output including microcontrollers such as the 80C51, 87C51, 68HC11 and
68HC05 and most digital signal processors.
Figure 3 shows the timing diagram for reading from the AD7892
in the serial interface mode. RFS goes low to access data from
the AD7892. The serial clock input does not have to be continuous. The serial data can be accessed in a number of bytes.
However, RFS must remain low for the duration of the data
transfer operation. Sixteen bits of data are transmitted with four
leading zeros followed by the 12-bit conversion result starting
with the MSB. Serial data is clocked out of the device on the
rising edge of SCLK. Old data is guaranteed to be valid for 5 ns
after this edge. This is useful for high speed serial clocks where
the access time of the part would not allow sufficient set-up time
for the data to be accepted on the falling edge of the clock. In
this case, care must be taken that RFS does not go just prior to
a rising edge of SCLK. For slower serial clocks data is valid on
the falling edge of SCLK. At the end of the read operation, the
SDATA line is three-stated by a rising edge on either the SCLK
or RFS inputs, whichever occurs first. Serial data cannot be
read during conversion to avoid feedthrough problems from the
serial clock to the conversion process. For optimum performance of the AD7892-3, a serial read should also be avoided
within 200 ns of the rising edge of CONVST to avoid feedthrough
into the track/hold during its acquisition time. The serial read
should, therefore, occur between the end of conversion (EOC
falling edge) and 200 ns prior to the next rising edge of
CONVST. For the AD7892-1 and AD7892-2, a serial read
should also be avoided within 400 ns of the rising edge of
CONVST. This limits the maximum achievable throughput
rate in serial mode (assuming 20 MHz serial clock) to 400 kSPS
for the AD7892-3 and 357 kSPS for the AD7892-1 and
AD7892-2.
Analog Input Section
The AD7892 is offered as three part types allowing for four
different analog input voltage ranges. The AD7892-1 handles
either ± 5 V or ± 10 V input voltage ranges. The AD7892-2
handles a 0 V to +2.5 V input voltage range while the AD7892-3
handles an input range of ± 2.5 V.
AD7892-1
Figure 4 shows the analog input section for the AD7892-1. The
analog input range is pin-strappable (using VIN2) for either ± 5 V
or ± 10 V on the VIN1 input. With VIN2 connected to AGND, the
input range on VIN1 is ± 10 V, and the input resistance on VIN1 is
15 kΩ nominal. With VIN2 connected to VIN1, the input range on
VIN1 is ± 5 V, and the input resistance on VIN1 is 8 kΩ nominal.
As a result, the VIN1 and VIN2 inputs should be driven from a
low impedance source. The resistor attenuator stage is followed
by the high input impedance stage of the track/hold amplifier.
This resistor attenuator stage allows the input voltage to go to
± 17 V without damaging the AD7892-1.
+2.5
REFERENCE
2k⍀
REF OUT/
REF IN
3.25k⍀
TO ADC
REFERENCE
CIRCUITRY
6.5k⍀
TO HIGH
IMPEDANCE
SHA INPUT
13k⍀
VIN1
13k⍀
VIN2
AGND
Figure 4. AD7892-1 Analog Input Structure
RFS (I)
t10
t12
t16
SCLK (I)
t13
t11
FOUR LEADING ZEROS
SDATA (O)
t14
t15
DB11
DB10
t17A
t17
DB0
THREESTATE
NOTE:
I = INPUT; O = OUTPUT
Figure 3. Serial Mode Timing Diagram
–10–
REV. C
AD7892
The designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs). Output
coding is two’s complement binary with 1 LSB = FSR/4096 =
20 V/4096 = 4.88 mV for the ± 10 V range and 1 LSB = FSR/
4096 = 10 V/4096 = 2.44 mV for the ± 5 V range. The ideal
input/output transfer function for the AD7892-1 is shown in
Table I.
AD7892-2
The analog input section for the AD7892-2 contains no biasing
resistors. The analog input looks directly into the track/hold
input stage. The analog input range on the VIN1 input is 0 V to
+2.5 V. The VIN2 input can be left unconnected but if it is
connected to a potential then that potential must be AGND.
The VIN1 input connects directly to the input sampling capacitor
of the AD7892-2’s track/hold. The value of this input sampling
capacitor is nominally 10 pF.
AD7892-3
Figure 5 shows the analog input section for the AD7892-3. The
analog input range is ± 2.5 V on the VIN1 input. The VIN2 input
can be left unconnected but if it is connected to a potential then
that potential must be AGND. The input resistance on the VIN1
is 1.8 kΩ nominal. As a result, the VIN1 input should be driven
from a low impedance source. The resistor attenuator stage is
followed by the high input impedance stage of the track/hold
amplifier. This resistor attenuator stage allows the input voltage
to go to ± 7 V without damaging the AD7892-3.
The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs).
Output coding is two’s complement binary with 1 LSB = FSR/
4096 = 5 V/4096 = 1.22 mV with REF IN = +2.5 V. The ideal
input/output transfer function for the AD7892-3 is shown in
Table III.
Once again, the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs). Output coding is straight (natural) binary with
1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/
output transfer function for the AD7892-2 is shown in Table II.
2k⍀
+2.5
REFERENCE
REF OUT/
REF IN
Table I. Ideal Input/Output Code Table for the AD7892-1
3.25k⍀
Digital Output
Code Transition
Analog Input
1, 2
3
+FSR/2 – 3/2 LSB (9.99268 or 4.99634)
+FSR/2 – 5/2 LSBs (9.98779 or 4.99390)
+FSR/2 – 7/2 LSBs (9.98291 or 4.99146)
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
AGND + 3/2 LSB (0.00732 or 0.00366)
AGND + 1/2 LSB (0.00244 or 0.00122)
AGND – 1/2 LSB (–0.00244 or –0.00122)
AGND – 3/2 LSB (–0.00732 or –0.00366)
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
–FSR/2 + 5/2 LSB (–9.98779 or –4.99390)
–FSR/2 + 3/2 LSB (–9.99268 or –4.99634)
–FSR/2 + 1/2 LSB (–9.99756 or –4.99878)
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
to
to
to
to
3.25k⍀
Table II. Ideal Input/Output Code Table for the AD7892-2
Analog Input
Digital Output
Code Transition
+FSR – 3/2 LSB1, 2 (2.499084 V)
+FSR – 5/2 LSBs (2.498474 V)
+FSR – 7/2 LSBs (2.497864 V)
111 . . . 110 to 111 . . . 111
111 . . . 110 to 111 . . . 110
111 . . . 100 to 111 . . . 101
AGND + 5/2 LSB (0.001526 V)
AGND + 3/2 LSB (0.00916 V)
AGND + 1/2 LSB (0.000305 V)
000 . . . 010 to 010 . . . 011
000 . . . 001 to 001 . . . 010
000 . . . 000 to 000 . . . 001
VIN2*
AGND
* UNCONNECTED INTERNALLY ON THE AD7892-3
Figure 5. AD7892-3 Analog Input Structure
Table III. Ideal Input/Output Code Table for the AD7892-3
Analog Input
Digital Output
Code Transition
+FSR/2 – 3/2 LSB1, 2 (2.49817)
+FSR/2 – 5/2 LSBs (2.49695)
+FSR/2 – 7/2 LSBs (2.49573)
011 . . . 110 to 011 . . . 111
011 . . . 110 to 011 . . . 110
011 . . . 110 to 011 . . . 101
AGND + 3/2 LSB (0.00183)
AGND + 1/2 LSB (0.00061)
AGND – 1/2 LSB (–0.00061)
AGND – 3/2 LSB (–0.00183)
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
–FSR/2 + 5/2 LSB (–2.49695)
–FSR/2 + 3/2 LSB (–2.49817)
–FSR/2 + 1/2 LSB (–2.49939)
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
1
FSR is full-scale range and is 5 V with REF IN = +2.5 V.
2
1 LSB = FSR/4096 = 1.22 mV with REF IN = +2.5 V.
NOTES
1
FSR is full-scale range and is 2.5 V with REF IN = +2.5 V.
2
1 LSB = FSR/4096 = 0.61 mV with REF IN = +2.5 V.
REV. C
TO HIGH
IMPEDANCE
SHA INPUT
VIN1
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
NOTES
1
FSR is full-scale range and REF IN = +2.5 V, is 20 V for the ± 10 V range and 10 V
for the ± 5 V range.
2
1 LSB = FSR/4096 = 4.88 mV (± 10 V range) and 2.44 mV (± 5 V range) with REF
IN = +2.5 V.
3
± 10 V range or ± 5 V range.
TO ADC
REFERENCE
CIRCUITRY
–11–
to
to
to
to
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
AD7892
MICROPROCESSOR INTERFACING
EOC Pulse Provides CS and RD
The AD7892 features both high speed parallel and serial interfaces, allowing considerable flexibility in interfacing to microprocessor systems. To obtain optimum performance from the
part, data should not be read during conversion and this limits
the achievable throughput rate in serial mode to 400 kSPS for
the AD7892-3.
Figure 8 shows a parallel interface between the AD7892 and a
gate array or ASIC. CONVST starts conversion and at the end
of conversion the falling edge of the EOC output provides the
CS and RD pulse to latch data out of the AD7892 and into the
gate array/ASIC. This scheme allows for the fastest possible
throughput rate with the part as no time is lost in interrupt
service routines and as soon as data is available from the part it
is transferred out of it.
Figures 6, 7 and 9 show some typical interface circuits between
the AD7892 and popular DSP processors. Figure 8 shows an
interface between the part and a gate array or ASIC where data
is clocked into the ASIC by the AD7892 itself at the end of
conversion. In all cases, the CONVST signal is generated from
an external timer to ensure equidistant sampling.
TIMER
AD7892 to ADSP-2101 Interface
AD7892
GATE
ARRAY/ASIC
Figure 6 shows a parallel interface between the AD7892 and the
ADSP-2101 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output provides an interrupt request to the ADSP-2101.
CONVST
EOC
ENABLE
RD
CS
TIMER
DMA13–DMA0
ADSP-2101
ADDRESS BUS
DB11–DB0
ADDRESS DECODE
LOGIC
DMS
AD7892
EN
CONVST
CS
IRQn
DMD15–DMD0
RD
DATA BUS
Figure 8. AD7892 to Gate Array/ASIC Interface
AD7892 to DSP56000 Interface
DB11–DB0
TIMER
DSP56000
Figure 6. AD7892 to ADSP-2101
IRQA
Figure 7 shows a parallel interface between the AD7892 and the
TMS320C25 DSP processor. CONVST starts conversion and
at the end of conversion the falling edge of the EOC output
provides an interrupt request to the TMS320C25.
IS
EOC
SCK
SCLK
SRD
SDATA
SC1
RFS
Figure 9. AD7892 to DSP56000 Interface
TIMER
TMS320C25
AD7892
CONVST
AD7892 to TMS320C25 Interface
A15–A0
DB11–DB0
Figure 9 shows a serial interface between the AD7892 and the
DSP56000 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output provides an interrupt request to the DSP56000.
EOC
RD
DATA BUS
ADDRESS BUS
ADDRESS DECODE
LOGIC
EN
CS
CONVST
READY
G2
AD7892
MSC
STRB
RD
R/W
EOC
INT
D15–D0
DATA BUS
DB11–DB0
Figure 7. AD7892 to TMS320C25 Interface
–12–
REV. C
AD7892
Grounding and Layout
The AD7892 has a single supply voltage pin, VDD, which supplies both the analog and digital circuitry on the part. For optimum performance from the part, it is recommended that this
+5 V is taken from the +5 V analog supply in the system. The
analog and digital grounds to the AD7892 are independent and
separately pinned out to minimize coupling between the analog
and digital sections of the device. The part exhibits good immunity to noise on the supplies but care must still be taken with
regard to grounding and layout especially when using switching
mode supplies.
The printed circuit board which houses the AD7892 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD7892 is the only device requiring
an AGND to DGND connection, then the ground planes
should be connected at the AGND and DGND pins of the
AD7892. If the AD7892 is in a system where multiple devices
require AGND to DGND connections, the connection should
still be made at one point only, a star ground point which
should be established as close as possible to the AD7892.
Evaluating the AD7892 Performance
The recommended layout for the AD7892 is outlined in the
evaluation board for the AD7892. The evaluation board package
includes a fully assembled and tested evaluation board, documentation and software for controlling the board from a PC
using the EVAL-CONTROL BOARD. The EVAL-CONTROL
BOARD can be used in conjunction with the AD7892 evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator. Using the EVAL-CONTROL
BOARD with the AD7892 evaluation board allows the user to
evaluate the ac and dc performance of the AD7892 on a PC.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7892 to avoid noise coupling. The power
supply lines to the AD7892 should use as large a trace as possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
REV. C
Good decoupling is important when using high resolution ADCs.
All analog supplies should be decoupled with 10 µF tantalum in
parallel with 0.1 µF capacitors to AGND. To achieve the best
from these decoupling components, they have to be placed as
close as possible to the device, ideally right up against the device.
All logic chips should be decoupled with 0.1 µF disc ceramic
capacitors to DGND. It is recommended that the system’s
AVDD supply is used to supply the VDD for the AD7892. This
supply should have the recommended analog supply decoupling
capacitors between the VDD pin of the AD7892 and AGND and
the recommended digital supply decoupling capacitor between
the VDD pin of the AD7892 and DGND.
The software provided with the evaluation board allows the user
to perform ac (Fast Fourier Transform) and dc (histogram of
codes) tests on the AD7892. The evaluation board can also
be used in a stand-alone fashion without the EVAL-CONTROL
BOARD but in this case, the user has to write their own software
to evaluate the part. There are two versions of the evaluation
board available, one for the AD7892-2 and one for the AD7892-3.
To order the AD7892-2 evaluation board, the order number is
EVAL-AD7892-2CB and to order the AD7892-3 evaluation
board, the order number is EVAL-AD7892-3CB.
–13–
AD7892
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-24)
24
13
1
12
0.260 ± 0.001
(6.61 ± 0.03)
C1933c–2.5–6/00 (rev. C) 01359
1.228 (31.19)
1.226 (31.14)
0.32 (8.128)
0.30 (7.62)
PIN 1
0.130 (3.30)
0.128 (3.25)
0.02 (0.5)
0.11 (2.79)
0.016 (0.41)
0.09 (2.28)
SEATING
PLANE
0.07 (1.78)
0.05 (1.27)
0.011 (0.28)
0.009 (0.23)
15ⴗ
0
Cerdip (Q-24)
0.005 (0.13) MIN
0.098 (2.49) MAX
24
13
1
12
0.310 (7.87)
0.220 (5.59)
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
1.280 (32.51) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
SOIC (R-24)
1
12
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.012 (0.30)
0.004 (0.10)
0.050
(1.27)
BSC
8ⴗ
0.019 (0.49)
0ⴗ
SEATING
0.013 (0.32)
0.014 (0.35) PLANE
0.009 (0.23)
–14–
0.0291 (0.74)
ⴛ 45ⴗ
0.0098 (0.25)
0.050 (1.27)
0.015 (0.40)
PRINTED IN U.S.A.
13
0.419 (10.65)
0.394 (10.00)
24
0.299 (7.60)
0.291(7.40)
0.614 (15.6)
0.598 (15.2)
REV. C