Intersil ISL9000AIRFJZ Dual ldo with low noise, very high psrr and low iq Datasheet

Dual LDO with Low Noise, Very High PSRR and Low IQ
ISL9000A
Features
ISL9000A is a high performance dual LDO capable of sourcing
300mA current from each output. It has a low standby current
and very high PSRR and is stable with output capacitance of
1µF to 10µF with ESR of up to 200mΩ.
• Integrates two 300mA high performance LDOs
• Excellent transient response to large current steps
• ±1.8% accuracy over all operating conditions
• Excellent load regulation: < 0.1% voltage change across full
range of load current
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise filtering capacitor for low noise and highPSRR applications.
• Low output noise: typically 30µVRMS @ 100µA (1.5V)
• Very high PSRR: 90dB @ 1kHz
• Extremely low quiescent current: 42µA (both LDOs active)
• Wide input voltage capability: 2.3V to 6.5V
• Low dropout voltage: typically 200mV @ 300mA
The quiescent current is typically only 42µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
• Stable with 1µF to 10µF ceramic capacitors
• Separate enable and POR pins for each LDO
• Soft-start and staged turn-on to limit input current surge
during enable
Several combinations of voltage outputs are standard. Output
voltage options for each LDO range from 1.5V to 3.3V. Other
output voltage options may be available upon request.
• Current limit and overheat protection
• Tiny 10 Ld 3mmx3mm DFN package
• -40°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handheld
ISL9000A
1
VIN (2.3 TO 6.5V)
ON
2
ENABLE1
OFF ON
ENABLE2
OFF
3
4
5
C1
C2
10
VIN
VO1
VO1
9
EN1
VO2
VO2 OK
8
EN2
POR2
CBYP
POR1
CPOR
GND
7
VO2 TOO LOW
6
VOUT1 OK
C3
C4
C5
VO1 TOO LOW
VO2
RESET2
(200ms DELAY,
C3 = 0.01µF)
RESET1
(2ms DELAY)
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
FIGURE 1. TYPICAL APPLICATION
March 26, 2014
FN6391.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2008, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9000A
Block Diagram
VIN
VO1
VO2
LDO
VO1
ERROR
AMPLIFIER
~1.0V
VO2
VREF
TRIM
IS1
POR
COMPARATOR
QEN1
VOK1
1V
POR1
LDO-1
POR2
QEN2
VO1
100k
QEN1
IS2
LDO-2
IS1
VOK2
EN1
CONTROL
LOGIC
EN2
POR2
VOK2
POR2
DELAY
CBYP
VO2
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
GENERATOR
100k
UVLO
1.00V
VOK1
0.94V
2
POR1
0.90V
CPOR
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POR1
DELAY
GND
FN6391.2
March 26, 2014
ISL9000A
Pin Configuration
ISL9000A
(10 LD 3X3 DFN)
TOP VIEW
VIN 1
10 VO1
EN1 2
9
VO2
EN2 3
8
POR2
CBYP 4
7
POR1
CPOR 5
6
GND
Pin Descriptions
PIN
NUMBER
PIN
NAME
TYPE
1
VIN
Analog I/O
2
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4
CBYP
Analog I/O
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5
CPOR
Analog I/O
POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2
output reaches 94% of its specified voltage level. (200ms delay per 0.01µF).
6
GND
Ground
7
POR1
Open Drain Output (1mA)
Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100kΩ resistor.
8
POR2
Open Drain Output (1mA)
Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100kΩ resistor.
9
VO2
Analog I/O
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
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DESCRIPTION
Supply Voltage/LDO Input:
Connect a 1µF, X5R ceramic capacitor to GND.
GND is the connection to system ground. Connect to PCB Ground plane.
FN6391.2
March 26, 2014
ISL9000A
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
VO1 VOLTAGE
(V) (Note 2)
VO2 VOLTAGE
(V) (Note 2)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL9000AIRNNZ
DEYA
3.3
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRNJZ
DEWA
3.3
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRNFZ
DEVA
3.3
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRNCZ
DETA
3.3
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRMNZ
DESA
3.0
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRMMZ
DERA
3.0
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRMGZ
DEPA
3.0
2.7
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRLLZ
DENA
2.9
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKNZ
DELA
2.85
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKKZ
DEKA
2.85
2.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKJZ
DEJA
2.85
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKFZ
DEHA
2.85
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKPZ
DEMA
2.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRKCZ
DEGA
2.85
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRJNZ
DEEA
2.8
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRJMZ
DEDA
2.8
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRJRZ
DEFA
2.8
2.6
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRJCZ
DECA
2.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRJBZ
DEBA
2.8
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRGPZ
DDYA
2.7
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRGCZ
DDWA
2.7
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRFJZ
DDVA
2.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRFDZ
DDTA
2.5
2.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRFCZ
DDSA
2.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRPLZ
DFBA
1.85
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRPPZ
DFCA
1.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRCJZ
DDRA
1.8
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRCCZ
DDPA
1.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRBLZ
DDNA
1.5
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRBJZ
DDMA
1.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRBCZ
DDLA
1.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRBBZ
DDKA
1.5
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6391.2
March 26, 2014
ISL9000A
Evaluation Board Ordering Information
PART
NUMBER
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
ISL9000AIRNNZ-EVZ
3.3
3.3
ISL9000AIRNJZ-EVZ
3.3
2.8
ISL9000AIRNFZ-EVZ
3.3
2.5
ISL9000AIRNCZ-EVZ
3.3
1.8
ISL9000AIRMNZ-EVZ
3.0
3.3
ISL9000AIRMMZ-EVZ
3.0
3.0
ISL9000AIRMGZ-EVZ
3.0
2.7
ISL9000AIRLLZ-EVZ
2.9
2.9
ISL9000AIRKNZ-EVZ
2.85
3.3
ISL9000AIRKKZ-EVZ
2.85
2.85
ISL9000AIRKJZ-EVZ
2.85
2.8
ISL9000AIRKFZ-EVZ
2.85
2.5
ISL9000AIRKPZ-EVZ
2.85
1.85
ISL9000AIRKCZ-EVZ
2.85
1.8
ISL9000AIRJNZ-EVZ
2.8
3.3
ISL9000AIRJMZ-EVZ
2.8
3.0
ISL9000AIRJRZ-EVZ
2.8
2.6
ISL9000AIRJCZ-EVZ
2.8
1.8
ISL9000AIRJBZ-EVZ
2.8
1.5
ISL9000AIRGPZ-EVZ
2.7
1.85
ISL9000AIRGCZ-EVZ
2.7
1.8
ISL9000AIRFJZ-EVZ
2.5
2.8
ISL9000AIRFDZ-EVZ
2.5
2.0
ISL9000AIRFCZ-EVZ
2.5
1.8
ISL9000AIRPLZ-EVZ
1.85
2.9
ISL9000AIRPPZ-EVZ
1.85
1.85
ISL9000AIRPPZ-EVZ
1.8
2.8
ISL9000AIRCCZ-EVZ
1.8
1.8
ISL9000AIRBLZ-EVZ
1.5
2.9
ISL9000AIRBJZ-EVZ
1.5
2.8
ISL9000AIRBCZ-EVZ
1.5
1.8
ISL9000AIRBBZ-EVZ
1.5
1.5
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FN6391.2
March 26, 2014
ISL9000A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.1V
VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance (Notes 4, 5)
θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . . . . . . . .
52.8
11
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF;
CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
6.5
V
DC CHARACTERISTICS
Supply Voltage
VIN
2.3
Quiescent condition: IO1 = 0µA; IO2 = 0µA
Ground Current
IDD1
One LDO active
25
32
µA
IDD2
Both LDO active
42
52
µA
Shutdown Current
IDDS
@ +25°C
0.1
1.0
µA
UVLO Threshold
VUV+
1.9
2.1
2.3
V
VUV-
1.6
1.8
2.0
V
Regulation Voltage Accuracy
Maximum Output Current
IMAX
Internal Current Limit
ILIM
Dropout Voltage (Note 7)
VDO1
Thermal Shutdown
Temperature
Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C
-0.7
+0.7
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C
-0.8
+0.8
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to +125°C
-1.8
+1.8
%
Continuous
300
350
mA
475
600
mA
IO = 300mA; VO < 2.5V
300
500
mV
VDO2
IO = 300mA; 2.5V ≤ VO ≤ 2.8V
250
400
mV
VDO3
IO = 300mA; VO > 2.8V
200
325
mV
TSD+
145
°C
TSD-
110
°C
@ 1kHz
90
dB
@ 10kHz
70
dB
@ 100kHz
50
dB
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz
30
µVRMS
AC CHARACTERISTICS
Ripple Rejection (Note 6)
IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
Output Noise Voltage (Note 6)
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FN6391.2
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ISL9000A
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF;
CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
MIN
(Note 8)
TEST CONDITIONS
TYP
MAX
(Note 8)
UNITS
250
500
µs
30
60
µs/V
DEVICE START-UP CHARACTERISTICS
Device Enable Time
tEN
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VOx(NOM)
LDO Soft-Start Ramp Rate
tSSR
Slope of linear portion of LDO output voltage ramp during start-up
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN +
0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
POR1, POR2 PIN CHARACTERISTICS
POR1, POR2 Thresholds
VPOR+
POR1 Delay
As a percentage of nominal output voltage
91
94
97
%
VPOR-
87
90
93
%
tP1LH
1.0
2.0
3.0
ms
25
tP1HL
POR2 Delay
tP2LH
CPOR = 0.01µF
100
VOL
POR1, POR2 Pin Internal
Pull-Up Resistance
300
25
tP2HL
POR1, POR2 Pin Output Low
Voltage
200
µs
@ IOL = 1.0mA
RPOR
78
100
ms
µs
0.2
V
180
kΩ
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
EN1
EN2
tEN
VPOR+
VPOR-
VPOR+
VPOR-
<tP1HL
VO1
VO2
<tP2HL
tP1LH
tP1HL
tP2LH
tP2HL
POR1
POR2
FIGURE 2. TIMING PARAMETER DEFINITION
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ISL9000A
Typical Performance Curves
0.10
0.8
VO = 3.3V
ILOAD = 0mA
0.4
0.2
-40°C
0.0
+25°C
-0.2
+85°C
-0.4
VIN = 3.8V
VO = 3.3V
0.08
OUTPUT VOLTAGE CHANGE (%)
OUTPUT VOLTAGE, VO (%)
0.6
-0.6
0.06
0.04
-40°C
0.02
+25°C
0.00
-0.02
+85°C
-0.04
-0.06
-0.08
-0.8
3.4
3.8
4.6
4.2
5.0
5.4
5.8
6.2
-0.10
6.6
0
50
200
250
300
350
400
LOAD CURRENT - IO (mA)
FIGURE 3. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
VO = 3.3V
IO = 0mA
3.3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE CHANGE (%)
150
100
INPUT VOLTAGE (V)
3.2
IO = 150mA
3.1
IO = 300mA
3.0
2.9
-0.08
-0.10
-40
2.8
-25
5
-10
20 35 50 65
TEMPERATURE (°C)
80
95
3.1
110 125
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
2.9
350
VO = 2.8V
IO = 0mA
DROPOUT VOLTAGE, VDO (mV)
2.8
OUTPUT VOLTAGE, VO (V)
3.6
2.7
IO = 150mA
2.6
IO = 300mA
2.5
2.4
2.3
2.6
300
250
VO = 2.8V
200
VO = 3.3V
150
100
50
0
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 7. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT)
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8
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
400
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FN6391.2
March 26, 2014
ISL9000A
Typical Performance Curves
(Continued)
55
350
VO = 3.3V
50
GROUND CURRENT (µA)
DROPOUT VOLTAGE, VDO (mV)
300
250
+85°C
+25°C
-40°C
200
150
100
+125°C
+25°C
45
-40°C
40
35
VO1 = 3.3V
VO2 = 2.8V
30
50
IO(BOTH CHANNELS) = 0µA
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
25
400
3.0
3.5
4.0
4.58
5.5
5.0
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 9. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 10. GROUND CURRENT vs INPUT VOLTAGE
55
200
180
50
140
GROUND CURRENT (µA)
GROUND CURRENT (µA)
160
+85°C
+25°C
120
100
-40°C
80
60
40
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
20
50
100
150
200
250
300
40
35
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
30
BOTH OUTPUTS ON
0
0
45
25
-40
400
350
-25
-10
5
LOAD CURRENT (mA)
FIGURE 11. GROUND CURRENT vs LOAD
20 35 50 65
TEMPERATURE (°C)
80
95
110 125
FIGURE 12. GROUND CURRENT vs TEMPERATURE
3.5
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
5
VIN
IL2 = 300mA
V O1
3
2
VO2
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
2.5
VOLTAGE (V)
VOLTAGE (V)
4
POR1
3.0
POR2
CPOR = 0.1µF
2.0
VO1
1.5
1
1.0
0
0.5
V O2
0
0
1
2
3
4
5
TIME (s)
6
7
8
FIGURE 13. POWER-UP/POWER-DOWN
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9
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (s)
3.5
4.0
4.5
5.0
FIGURE 14. POWER-UP/POWER-DOWN WITH POR SIGNALS
FN6391.2
March 26, 2014
ISL9000A
Typical Performance Curves
(Continued)
VO = 3.3V
ILOAD = 300mA
VO2 (10mV/DIV)
VO1 (V)
CLOAD = 1µF
CBYP = 0.01µF
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
CL1, CL2 = 1µF
CBYP = 0.01µF
3
2
1
VIN (1V/DIV), 3.6V TO 4.2V
4.3V LINE TRANSIENT
3.6V
VEN (V)
0
VOx (10mV/DIV)
5
10mV/DIV
0
0
100
200
300
400
500
600
700
800
900 1000
400µs/DIV
TIME (µs)
FIGURE 16. LINE TRANSIENT RESPONSE (3.3V OUTPUT)
FIGURE 15. TURN-ON/TURN-OFF RESPONSE
VO = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
VO (25mV/DIV)
VIN (1V/DIV), 3.5V TO 4.2V
4.2V LINE TRANSIENT
3.5V
VO = 1.8V
VIN = 2.8V
ILOAD (200mA/DIV)
VOx (10mV/DIV)
300mA
10mV/DIV
100µA
100µs/DIV
400µs/DIV
FIGURE 17. LINE TRANSIENT RESPONSE (2.8V OUTPUT)
FIGURE 18. LOAD TRANSIENT RESPONSE
100
1000
90
80
CBYP = 0.1µF
70
PSRR (dB)
SPECTRAL NOISE DENSITY (nV/√Hz)
VIN = 3.6V
VO = 1.8V
IO = 10mA
CLOAD = 1µF
60
50
40
30
20
10
0
0.1
1k
10k
FREQUENCY (Hz)
100k
FIGURE 19. PSRR vs FREQUENCY
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10
1M
100
10
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
1
CBYP = 0.1µF
CIN = 1µF
CLOAD = 1µF
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 20. SPECTRAL NOISE DENSITY vs FREQUENCY
FN6391.2
March 26, 2014
ISL9000A
Functional Description
The ISL9000A contains two high performance LDO’s. High
performance is achieved through a circuit that delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9000A adjusts its biasing to achieve the lowest
standby current consumption.
The device also integrates current limit protection, smart thermal
shutdown protection, staged turn-on and soft-start. Smart
thermal shutdown protects the device against overheating.
Staged turn-on and soft-start minimize start-up input current
surges without causing excessive device turn-on time.
Power Control
The ISL9000A has two separate enable pins (EN1 and EN2) to
individually control power to each of the LDO outputs. When both
EN1 and EN2 are LOW, the device is in shutdown mode. During
this condition, all on-chip circuits are OFF, and the device draws
minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the device first
polls the output of the UVLO detector to ensure that VIN voltage is
at least about 2.1V. Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are first
read and latched. Then, sequentially, the bandgap, reference
voltage and current generation circuitry power-up. Once the
references are stable, a fast-start circuit quickly charges the
external reference bypass capacitor (connected to the CBYP pin)
to the proper operating voltage. After the bypass capacitor has
been charged, the LDOs power-up in their specified sequence.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge.
1kHz frequency band, which is crucial in many noise-sensitive
applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider provides
the regulation reference, POR detection thresholds, and other
voltage references required for current generation and overtemperature detection.
The current generator provides the references required for
adaptive biasing as well as references for LDO output current
limit and thermal shutdown determination.
LDO Regulation and Programmable Output
Divider
The LDO Regulator is implemented with a high-gain operational
amplifier driving a PMOS pass transistor. The design of the
ISL9000A provides a regulator that has low quiescent current,
fast transient response, and overall stability across all operating
and load current conditions. LDO stability is guaranteed for a 1µF
to 10µF output capacitor that has a tolerance better than 20%
and ESR less than 200mΩ. The design is performance-optimized
for a 1μF capacitor. Unless limited by the application, use of an
output capacitor value above 4.7µF is not normally needed as
LDO performance improvement is minimal.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down to 1V.
This is compared to the 1V reference for regulation. The resistor
division ratio is programmed in the factory to one of the following
output voltages: 1.5V, 1.8V, 1.85V, 2.5V, 2.6V, 2.7V, 2.8V, 2.85V,
2.9V, 3.0V, and 3.3V.
Power-On Reset Generation
If EN1 is brought HIGH, and EN2 goes HIGH before the VO1
output stabilizes, the ISL9000A delays the VO2 turn-on until the
VO1 output reaches its target level.
Each LDO has a separate Power-on Reset signal generation
circuit which outputs to the respective POR pins. The POR signal
is generated as follows:
If EN2 is brought high, and EN1 goes HIGH before VO2 starts its
output ramp, then VO1 turns on first and, the ISL9000A delays
the VO2 turn-on until the VO1 output reaches its target level.
A POR comparator continuously monitors the output of each LDO.
The LDO enters a power-good state when the output voltage is
above 94% of the expected output voltage for a period exceeding
the LDO PGOOD entry delay time. In the power-good state, the
open-drain PORx output is in a high-impedance state. An internal
100kΩ pull-up resistor pulls the pin up to the respective LDO
output voltage. An external resistor can be added between the
PORx output and the LDO output for a faster rise time, however,
the PORx output should not connect through an external resistor to
a supply greater than the associated LDO voltage.
If EN2 is brought HIGH, and EN1 goes HIGH after VO2 starts its
output ramp, then the ISL9000A immediately starts to ramp up
the VO1 output.
If both EN1 and EN2 are brought HIGH at the same time, the VO1
output has priority, and is always powered up first.
During operation, whenever the VIN voltage drops below about
1.8V, the ISL9000A immediately disables both LDO outputs.
When VIN rises back above 2.1V, the device re-initiates its
start-up sequence and LDO operation will resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed bandgap,
a trimmed voltage reference divider, a trimmed current reference
generator, and an RC noise filter. The filter includes the external
capacitor connected to the CBYP pin. A 0.01µF capacitor
connected CBYP implements a 100Hz lowpass filter, and is
recommended for most high performance applications. For the
lowest noise application, a 0.1µF or greater CBYP capacitor
should be used. This filters the reference noise below the 10Hz to
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The power-good state is exited when the LDO output falls below
90% of the expected output voltage for a period longer than the
PGOOD exit delay time. While power-good is false, the ISL9000A
pulls the respective POR pin low.
For LDO-1, the PGOOD entry delay time is fixed at about 2ms
while the PGOOD exit delay is about 25µs. For LDO-2, the PGOOD
entry and exit delays are determined by the value of the external
capacitor connected to the CPOR pin. For a 0.01µF capacitor, the
entry and exit delays are 200ms and 25µs respectively. Larger or
smaller capacitor values will yield proportionately longer or
shorter delay times. The POR exit delay should never be allowed
to be less than 10µs to ensure sufficient immunity against
transient induced false POR triggering.
FN6391.2
March 26, 2014
ISL9000A
Overheat Detection
The bandgap provides a proportional-to-temperature current that
is indicative of the temperature of the silicon. This current is
compared with references to determine if the device is in danger
of damage due to overheating. When the die temperature
reaches about +145°C, one or both of the LDO’s momentarily
shut down until the die cools sufficiently. In the overheat
condition, only the LDO sourcing more than 50mA will be shut
off. This does not affect the operation of the other LDO. If both
LDOs source more than 50mA and an overheat condition occurs,
both LDO outputs are disabled. Once the die temperature falls
back below about +110°C, the disabled LDO(s) are re-enabled
and soft-start automatically takes place.
The ISL9000A provides short-circuit protection by limiting the
output current to about 475mA. If short circuited, an output
current of 475mA will cause die heating. If the short circuit lasts
long enough, the overheat detection circuit will turn off the
output.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 26, 2014
FN6391.2
Added “Evaluation Board Ordering Information” on page 5.
Updated θJA and θJC in “Thermal Information” on page 6 from 50/10 to 52.8/11
Added standard "Boldface limits apply" verbiage to common conditions of “Electrical Specifications” table.
Bolded applicable specs.
Changed Note 8 in spec table from “Parts are 100% tested at +25°C. Temperature limits established by
characterization and are not production tested.” to “Parameters with MIN and/or MAX limits are 100% tested
at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.”
Updated Products section on page 12 to new About Intersil verbiage.
Updated “Package Outline Drawing” on page 13. Changes:
Updated format to new standard
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." - it is not applicable to this package. Renumbered notes accordingly.
March 11, 2008
FN6391.1
Added “VO1, VO2 Pins” to “Absolute Maximum Ratings” on page 6.
Added “Other output voltage options may be available upon request" to page 1.
January 7, 2010
FN6391.0
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN6391.2
March 26, 2014
ISL9000A
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 3, 10/11
3.00
5
PIN #1 INDEX AREA
A
B
10
5
PIN 1
INDEX AREA
1
2.38
3.00
0.50
2
10 x 0.25
6
(4X)
0.10 C B
1.64
TOP VIEW
10x 0.40
BOTTOM VIEW
(4X)
0.10 M C B
SEE DETAIL "X"
(10 x 0.60)
(10x 0.25)
0.90
MAX
0.10 C
BASE PLANE
2.38
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
2.80 TYP
C
0.20 REF
4
TYPICAL RECOMMENDED LAND PATTERN
0.05
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature.
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
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13
COMPLIANT TO JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN6391.2
March 26, 2014