IDT IDT7132SA25FB High-speed 2k x 8 dual-port static ram Datasheet

IDT7132SA/LA
IDT7142SA/LA
HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132
• Low-power operation
— IDT7132/42SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
— IDT7132/42LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-ormore bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)
• BUSY output flag on IDT7132; BUSY input on IDT7142
• Battery backup operation —2V data retention
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
• Industrial temperature range (–40°C to +85°C) is available,
tested to miliary electrical specifications
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a standalone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-ormore word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OER
OEL
CEL
CER
WL
R/
R/
I/O0L- I/O7L
I/O
Control
I/O0R-I/O7R
I/O
Control
(1,2)
BUSYR
BUSYL
A10L
A0L
Address
Decoder
MEMORY
ARRAY
11
NOTES:
1. IDT7132 (MASTER): BUSY is open
drain output and requires pullup
resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270Ω.
WR
(1,2)
A10R
Address
Decoder
A0R
11
ARBITRATION
LOGIC
CEL
CER
2692 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.02
OCTOBER 1996
DSC-2692/8
1
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
A5L
A6L
A7L
11
TSTG
IOUT
-55 to +125
50
-65 to +135
-65 to +150
50
°C
GND
0V
0V
°C
A10R
OER
WR
BUSYR
CER
R/
VCC
WL
CEL
R/
5 4
1
WR
R/
CER
VCC
CEL
3 2
BUSYR
2692 drw 03
N/C
A10R
I/O7R
I/O6R
52 51 50 49 48 47
I/O3L
20
34
°C
mA
8
9
10
11
12
13
14
15
16
IDT7132/42
J52-1
52-PIN PLCC
TOP VIEW (3)
21 22 23 24 25 26 27 28 29 30 31 32 33
A0R
A1R
A3R
A4R
A5R
A6R
A7R
A9R
N/C
I/O7R
2692 drw 04
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
VCC
GND
Parameter
Supply Voltage
Supply Voltage
VIH
Input High Voltage
VIL
VCC
5.0V ± 10%
5.0V ± 10%
A10L
33
17
32
18
31
19 20 21 22 23 24 25 26 27 28 29 30
I/O2L
I/O0L
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
16
A7R
A8R
A9R
A8R
V
A7L
2692 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +
0.5V.
Ambient
Temperature
-55°C to +125°C
0°C to +70°C
34
37
36
35
A6L
I/O1L
-55 to +125
15
17
18
19
Unit
A9L
-55 to +125
A6R
36
35
A2R
A8L
0 to +70
48-PIN LCC/ FLATPACK
TOP VIEW (3)
37
43
42
41
40
39
38
A5L
-0.5 to +7.0
13
14
38
I/O5R
I/O6R
TBIAS
-0.5 to +7.0
12
I/O2R
I/O3R
I/O4R
TA
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
39
IDT7132/42
L48-1
&
F48-1
OER
A4L
Military
10
I/O4L
VTERM
(2)
Commercial
A0R
A1R
A2R
A3R
A4R
A5R
42
46
45
44
A2L
A3L
Rating
48 47 46 45 44 43
41
40
7 6
A1L
ABSOLUTE MAXIMUM RATINGS(1)
1
8
9
INDEX
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
2
WL
A8L
A9L
I/O0L
I/O1L
I/O2L
4 3
BUSYL
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
7
R/
OER
A1L
A2L
A3L
A4L
GND
I/O0R
I/O1R
A10R
2692 drw 02
Symbol
A0L
6 5
BUSYR
A10L
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
WR
R/
N/C
OEL
CER
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
A10L
INDEX
VCC
A0L
BUSYL
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9 IDT7132/ 40
10 7142 39
11
38
12 P48-1
37
&
13 C48-2 36
14
35
15 DIP 34
16 TOP 33
17 VIEW (3) 32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
OEL
WL
I/O5L
I/O6L
I/O7L
N/C
CEL
R/
OEL
PIN CONFIGURATIONS (1,2)
BUSYL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Input Low Voltage
Min. Typ.
4.5
5.0
0
0
2.2
(1)
-0.5
Max.
5.5
0
Unit
V
V
—
6.0(2)
V
—
0.8
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
V
2692 tbl 03
2692 tbl 02
6.02
2
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%)
Symbol
Parameter
ICC
Dynamic Operating
Current (Both Ports
Active)
CEL and CER = VIL, MIL. SA
Outputs open,
LA
f = fMAX(4)
COM'L. SA
LA
—
— 110 280
—
— 110 220
110 250 110 220
110 200 110 170
80
80
80
80
230
170
165
120
65
65
65
65
190
140
155
110
65
65
65
65
190
140
155
110
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH, MIL. SA
f = fMAX(4)
LA
COM'L. SA
LA
—
—
30
30
—
—
65
45
30
30
30
30
80
60
65
45
25
25
25
25
80
60
65
45
20
20
20
20
65
45
65
35
20
20
20
20
65
45
55
35
mA
ISB2
Standby Current
(One Port - TTL
Level Inputs)
MIL.
—
—
65
65
—
—
165
125
65
65
65
65
160
125
150
115
50
50
50
50
150
115
125
90
40 125
40 90
40 110
40 75
40
40
40
40
125
90
110
75
mA
ISB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs
MIL.
SA
LA
COM'L. SA
LA
—
—
1.0
0.2
—
—
15
5
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
mA
MIL.
—
—
60
60
—
—
155
115
60
60
60
60
155
115
145
105
45
45
45
45
145
105
110
85
40 110
40 85
40 100
40 70
40
40
40
40
110
80
95
70
mA
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Conditions
CE"A" = VIL and
CE"B" = VIH (7)
Version
7132X20(2) 7132X25(3) 7132X35 7132X55 7132X100
7142X25(3) 7142X35 7142X55 7142X100
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
SA
LA
Active Port Outputs COM'L. SA
Open, f = fMAX(4)
LA
CEL and
CER > VCC -0.2V,
VIN > VCC -0.2V or
VIN < 0.2V,f = 0(5)
CE"A" < 0.2V and
CE"B" > VCC -0.2V(7)
VIN > VCC -0.2V or
VIN < 0.2V,
Active Port Outputs
Open, f = fMAX(4)
SA
LA
COM'L. SA
LA
NOTES:
2689 tbl 04
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. Not available in DIP packages.
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, TA=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
Symbol
Parameter
7132SA
7142SA
Min.
Max.
Test Conditions
7132LA
7142LA
Max.
Max.
Unit
|lLl|
Input Leakage
Current(1)
VCC = 5.5V,
VIN = 0V to VCCIN = GND to VCC
—
10
—
5
µA
|lLO|
Output Leakage
Current(1)
VCC = 5.5V,
CE = VIH, VOUT = 0V to VCCC
—
10
—
5
µA
VOL
Output Low Voltage
(l/O0-l/O7)
lOL = 4mA
lOL= 16mA
—
0.4
—
0.4
V
VOL
Open Drain Output
Low Voltage (BUSY, INT)
lOL = 16mA
—
0.5
—
0.5
V
VOH
Output High Voltage
Supply Current
lOH = -4mA
VIN > VCC -0.2V or < 0.2V
2.4
—
2.4
—
V
NOTE:
1. At Vcc < 2.0V leakages are undefined.
2689 tbl 05
6.02
3
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
Parameter
lDT7132LA/IDT7142LA
Min.
Typ.
Max.
Test Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2.0V, CE ≥ VCC -0.2V
Mil.
VIN ≥ VCC -0.2V or VIN ≤ 0.2V Com’l.
(3)
tCDR
Chip Deselect to Data
Retention Time
tR(3)
Operation Recovery
Time
2.0
—
—
V
—
100
4000
µA
—
100
1500
µA
0
—
—
ns
—
—
ns
tRC(2)
2692 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
VCC
VDR ≥ 2.0V
4.5V
4.5V
tCDR
CE
Unit
GND TO 3.0V
5ns
1.5V
1.5V
Figures 1, 2, and 3
2692 tbl 07
tR
VDR
VIH
VIH
2692 drw 05
5V
5V
1250Ω
DATA
1250Ω
OUT
DATA
775Ω
30pF*
OUT
775Ω
5pF*
100pF for 55 and 100ns versions
2692 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig
5V
270Ω
BUSY or INT
30pF*
100pF for 55 and 100ns versions
Figure 3. BUSY and INT
AC Output Test Load
6.02
4
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
Symbol
7132X20(2) 7132X25(5) 7132X35
7132X55
7132X100
7142X55
7142X100
7142X25(5) 7142X35
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
tHZ
tPU
tPD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,4)
Output High-Z Time(1,4)
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
20
—
—
3
0
—
0
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
0
—
0
—
—
25
25
12
—
—
10
—
25
35
—
—
—
3
0
—
0
—
—
35
35
20
—
—
15
—
35
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
55
—
—
—
3
5
—
0
—
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
0
—
—
100
100
40
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
tBDDH (2,3)
2692 drw 07
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations, BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.02
5
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (3)
tACE
CE
tAOE
(4)
tHZ (2)
OE
tLZ
(2)
(1)
tHZ
VALID DATA
DATAOUT
tLZ
(1)
(4)
tPD
tPU
ICC
CURRENT
ISS
50%
50%
2692 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH, and the address is valid prior to or coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7132X20(2) 7132X25(6)
(6)
Symbol
Parameter
Write Cycle
tWC
Write Cycle Time(3)
tEW
Chip Enable to End of Write
tAW
Address Valid to End of Write
tAS
Address Set-up Time
tWP
Write Pulse Width(4)
tWR
Write Recovery Time
tDW
Data Valid to End of Write
tHZ
Output High Z Time(1)
tDH
Data Hold Time
tWZ
Write Enabled to Output in High Z(1)
tOW
Output Active From End of Write(1)
Min.
20
15
15
0
15
0
10
—
0
—
0
Max.
7142X25
Min. Max.
—
—
—
—
—
—
—
10
—
10
—
25
20
20
0
15
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
7132X35
7132X55
7142X35
7142X55
Min. Max. Min. Max.
35
30
30
0
25
0
15
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
55
40
40
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
25
—
30
—
7132X100
7142X100
Min. Max.
100
90
90
0
55
0
40
—
0
—
0
—
—
—
—
—
—
—
40
—
40
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2692 tbl 09
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0°C to +70°C temperature range only, PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
CAPACITANCE(1) (TA = +25°C,f = 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions(2) Max. Unit
VIN = 3dV
11
pF
VIN = 3dV
11
pF
NOTES:
2692 tbl 10
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.02
6
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE
tWP(2)
tAS(6)
tWR (3)
tHZ
(7)
W
R/
tWZ (7)
tOW
(4)
DATA OUT
(4)
tDW
tDH
DATA IN
2692 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5)
tWC
ADDRESS
tAW
CE
tAS(6)
tEW (2)
tWR (3)
W
R/
tDW
tDH
DATA IN
2692 drw 10
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
6.02
7
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)8M824S258M824S30
7132X20(1)
Symbol
Parameter
Busy Timing (For Master lDT7130 Only)
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Min. Max.
7132158M824S4
7132X55 7132X100
7142X55 7142X100
Min. Max. Min. Max.
Unit
7132X25(8)
7132X35
7142X35
7142X25(8)
Min. Max. Min. Max.
Write Pulse to Data Delay(2)
Write Hold After BUSY(6)
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
—
—
—
—
—
12
—
5
20
20
20
20
50
—
35
—
—
—
—
—
—
15
—
5
20
20
20
20
50
—
35
—
—
—
—
—
—
20
—
5
20
20
20
20
60
—
35
—
—
—
—
—
—
20
—
5
30
30
30
30
80
—
55
—
—
—
—
—
—
20
—
5
50
50
50
50
120
—
100
—
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Disable to Valid Data(4)
tBDD
Busy Timing (For Slave IDT7140 Only)e
Write to BUSY Input(5)
tWB
Write Hold After BUSY(6)
tWH
Write Pulse to Data Delay(2)
tWDD
Write Data Valid to Read Data Delay(2)
tDDD
—
5
0
12
—
—
25
—
—
—
40
30
—
5
0
15
—
—
35
—
—
—
50
35
—
5
0
20
—
—
35
—
—
—
60
35
—
5
0
20
—
—
50
—
—
—
80
55
—
5
0
20
—
—
65
ns
—
—
120
100
ns
ns
ns
ns
tBAA
tBDA
tBAC
tBDC
tWDD
tWH
tDDD
tAPS
NOTES:
2689 tbl 11
1. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (S or L).
8. Not available in DIP package
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY
(1,2,3)
tWC
ADDR’A’
MATCH
tWP
W’A’
R/
tDW
DATAIN’A’
tDH
VALID
tAPS
(1)
ADDR’B’
MATCH
tBDD
t BDA
BUSY’B’
tWDD
DATAOUT’B’
VALID
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port 'B' is opposite from port 'A'.
6.02
2692 drw 11
8
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY(3)
tWP
R/
W
L
tWB
BUSYR
(1)
tWH
W
R/
R
(2)
2692 drw 12
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING
ADDR
'A'
(1)
ADDRESSES MATCH
and 'B'
CE'B'
tAPS (2)
CE'A'
tBAC
tBDC
BUSY'A'
2692 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
tRC or tWC
ADDR'A'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
tAPS(2)
ADDR'B'
tBAA
tBDA
BUSY'B'
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
6.02
9
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TRUTH TABLES
The IDT7132/IDT7142 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT7132/
IDT7142 has an automatic power down feature controlled by
CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE = VIL). When a port is enabled, access to the
entire memory array is permitted.
TABLE I — NON-CONTENTION
READ/WRITE CONTROL(4)
Left or Right Port(1)
OE
R/W CE
D0–7
X
H
X
Z
X
H
X
Z
L
H
H
L
L
L
X
L
H
DATAIN
DATAOUT
Z
Function
Port Disabled and in PowerDown Mode, ISB2 or ISB4
CER = CEL = VIH, Power-Down
Mode, ISB1 or ISB3
Data Written Into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
BUSY LOGIC
2654 tbl 12
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
TABLE II — ADDRESS BUSY ARBITRATION
Inputs
Outputs
CEL
CER
A0L-A10L
A0R-A10R
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
BUSYL(1) BUSYR(1)
Function
2654 tbl 13
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open
drain, not push-pull outputs. On slaves the BUSYX input internally inhibits
writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can
not be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin.
6.02
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
BUSY pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins High.
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.
The busy outputs on the IDT7132/IDT7142 RAM in master
mode, are pull-up type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication for the resulting array requires the use of an external AND gate.
10
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAM the busy
pin is an output if the part is used as a master (M/S pin = VIH),
and the busy pin is an input if the part used as a slave (M/S pin
= VIL) as shown in Figure 4.
LEFT
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/ signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
RIGHT
W
W
R/
R/
BUSY
R/
IDT7132
MASTER
BUSY
W
R/
BUSY
270 Ω
W
W
BUSY
270 Ω
+5V
W
R/
BUSY
+5V
IDT7142
IDT7142
(1)
SLAVE
SLAVE
W
R/
BUSY
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and IDT7142 (Slave) RAMs.
ORDERING INFORMATION
IDT
XXXX
A
Device Type Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
C
J
L48
F
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
55
100
Commercial PLCC Only
LA
SA
Low Power
Standard Power
7132
7142
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
Speed in nanoseconds
2692 drw 16
6.02
11