Microchip MCP6143 600 na, non-unity gain rail-to-rail input/output op amp Datasheet

M
MCP6141/2/3/4
600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps
Features
Description
•
•
•
•
The MCP6141/2/3/4 family of non-unity gain stable
operational amplifiers (op amps) from Microchip
Technology, Inc. operate with a single supply voltage
as low as 1.4V, while drawing less than 1 µA (max.) of
quiescent current per amplifier. These devices are also
designed to support rail-to-rail input and output swing.
•
•
•
•
Low Quiescent Current: 600 nA/Amplifier (typ.)
Stable for gains of 10 V/V or higher
Rail-to-Rail Input: -0.3V (min.) to VDD + 0.3V (max.)
Rail-to-Rail Output:
- VSS+10 mV (min.) to V DD-10 mV (max.)
Gain Bandwidth Product: 100 kHz (typ.)
Wide Supply Voltage Range: 1.4V to 5.5V (max.)
Available in Single, Dual and Quad
Chip Select (CS) with MCP6143
Applications
•
•
•
•
The MCP6141/2/3/4 op amps have a gain bandwidth
product of 100 kHz (typ.) and are stable for gains of
10 V/V or higher. This specification makes these
devices appropriate for battery-powered applications
where higher frequency responses from the amplifier
are required.
The MCP6141/2/3/4 family of op amps are offered in
single (MCP6141), single with a Chip Select (CS) feature (MCP6143), dual (MCP6142) and quad
(MCP6144) configurations.
Toll Booth Tags
Wearable Products
Temperature Measurement
Battery-Powered
Typical Applications
Available Tools
VDD
• Spice macro models (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
MCP6141
PDIP, SOIC, MSOP
NC 1
-IN 2
+IN 3
VSS 4
8 NC
+
MCP6142
PDIP, SOIC, MSOP
OUTA 1
7 VDD
-INA 2
6 OUT
+INA 3
5 NC
-IN 2
+IN 3
VSS 4
8 CS
+
7 VDD
6 OUT
5 NC
- A+
+1.4V
to
5.5V
7 OUTB
+B -
VSS 4
MCP6143
PDIP, SOIC, MSOP
NC 1
8 VDD
1k Ω
5 +INB
14 OUTD
A D
-INA1 2 - + + - 13 -IND
12 +IND
+INA1 3
VDD 4
+INB 5
-INB 6 - B+ +COUTB1 7
IDD
11 VSS
10 +INC
9 -INC
MCP614X
VSS
RI
100 kΩ
RF = 1 MΩ
6 -INB
High Side Battery Current Sensor
RF
G n =  1 + ------ ≥ 10V/V

RI 
MCP6144
PDIP, SOIC, TSSOP
OUTA 1
VDD
V1
V2
V3
R1
R2
R3
I1
I2
I3
RF
IF
8 OUTC
VOUT
VREF
MCP614X
Summing Amplifier
1
1
1
G n = 1 + R F  ------ + ------ + ------ ≥ 10V/V
 R 1 R 2 R 3
 2002 Microchip Technology Inc.
21668A-page 1
MCP6141/2/3/4
1.0
1.1
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
Maximum Ratings†
VDD - VSS .........................................................................7.0V
All inputs and outputs........................ VSS -0.3V to V DD +0.3V
Difference Input voltage ....................................... |VDD - VSS|
Function
+IN/+INA/+INB/+INC/+IND
Non-inverting Inputs
-IN/-INA/-INB/-INC/-IND
Inverting Inputs
VDD
Positive Power Supply
VSS
Negative Power Supply
OUT/OUTA/OUTB/OUTC/OUTD Outputs
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
CS
Chip Select
Current at Output and Supply Pins ............................±30 mA
NC
No internal connection
Storage temperature .....................................-65°C to +150°C
Junction Temperature, TJ ............................................ +150°C
ESD protection on all pins (HBM:MM).................. ≥ 4 kV:200 V
†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C,
VCM = VDD/2, R L = 1 MΩ to VDD /2, and VOUT ~ VDD/2.
Parameters
Sym
Min
Typ
Max
Units
VOS
-3.0
—
+3.0
mV
∆VOS/∆T
—
±1.5
—
µV/°C
PSRR
70
85
—
dB
Input Bias Current
IB
—
1.0
—
pA
Input Bias Current Over-Temperature
IB
—
—
100
pA
Input Offset Current
IOS
—
1.0
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
ZDIFF
—
13
10 ||6
—
Ω||pF
Common-Mode Input Range
VCMR
VSS − 0.3
—
VDD + 0.3
V
Common-Mode Rejection Ratio
CMRR
62
80
—
dB
VDD = 5V,
VCM = -0.3V to 5.3V
60
75
—
dB
VDD = 5V,
VCM = 2.5V to 5.3V
60
80
—
dB
VDD = 5V,
VCM = -0.3V to 2.5V
95
115
—
dB
RL = 50 kΩ to VDD /2,
100 mV < VOUT <
(V DD − 100 mV)
—
VDD − 10
mV
RL = 50 kΩ to VDD /2
21
—
mA
VOUT = 2.5V, VDD = 5 V
Input Offset
Input Offset Voltage
Drift with Temperature
Power Supply Rejection
Conditions
VCM = VSS
TA= -40°C to +85°C
Input Bias Current and Impedance
Differential Input Impedance
TA= -40°C to +85°C
Common Mode
Open Loop Gain
DC Open Loop Gain (large signal)
AOL
Output
Maximum Output Voltage Swing
Output Short Circuit Current
VOL, VOH VSS + 10
IO
—
V DD
1.4
—
5.5
V
IQ
0.3
0.6
1.0
µA
Power Supply
Supply Voltage
Quiescent Current per amplifier
21668A-page 2
IO = 0
2002 Microchip Technology Inc.
MCP6141/2/3/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +5V, VSS = GND, TA = 25 °C,
VCM = VDD/2, R L = 1 MΩ to VDD /2, CL = 60 pF, and VOUT ~ VDD /2.
Parameters
Sym
Min
Typ
Max
Units
GBWP
—
100
—
kHz
Slew Rate
SR
—
24
—
V/ms
Phase Margin
PM
—
60
—
°
Input Voltage Noise
En
—
5.0
—
µVp-p
Input Voltage Noise Density
en
—
170
—
nV/√Hz
f = 1 kHz
Input Current Noise Density
in
—
0.6
—
fA/√Hz
f = 1 kHz
Gain Bandwidth Product
Conditions
G = +10
f = 0.1 Hz to 10 Hz
SPECIFICATIONS FOR MCP6143 CHIP SELECT FEATURE
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND, TA = 25 °C,
VCM = VDD/2, R L = 1 MΩ to VDD /2, CL = 60 pF, and VOUT ~ VDD /2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
VSS + 0.3
V
For entire VDD range
CS Input Current, Low
ICSL
—
5.0
—
pA
CS = VSS
CS Logic Threshold, High
VIH
VDD - 0.3
—
V DD
V
For entire VDD range
CS Input Current, High
ICSH
—
5.0
—
pA
CS = VDD
IQ
—
20
—
pA
CS = VDD
—
20
—
pA
CS = VDD
tON
—
2.0
50
ms
CS low = VSS + 0.3V, G = +1 V/V,
VOUT = 0.9 VDD/2
tOFF
—
10
—
µs
CS high = VDD - 0.3V, G = +1 V/V
VOUT = 0.1 VDD/2
VHYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS High Specifications
CS Input High, GND Current
Amplifier Output Leakage, CS High
Dynamic Specifications
CS Low to Amplifier Output High
Turn-on Time
CS High to Amplifier Output High Z
Hysteresis
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND.
Parameters
Symbol
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
θJA
—
85
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
108
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1: The MCP6141/2/3/4 family of op amps operates over this extended range, but with reduced performance.
 2002 Microchip Technology Inc.
21668A-page 3
MCP6141/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
16%
14%
1200 Samples
VDD = 5.5 V
Percentage of Occurrences
Percentage of Occurrences
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
12%
10%
8%
6%
4%
2%
0%
-3
-2
-1
0
1
2
35%
30%
1200 Samples
VDD = 1.4 V
25%
20%
15%
10%
5%
0%
3
-10
Input Offset Voltage (mV)
14%
600
1200 Samples
VDD = 1.4 V
12%
10%
8%
6%
4%
2%
0%
-3
-2
-1
0
1
2
200
0
-200
TA = +85°C
TA = +25°C
TA = -40°C
-400
Input Offset Voltage (µV)
Percentage of Occurrences
25%
20%
15%
10%
5%
0%
-5
0
5
10
Input Offset Voltage Drift (µV/°C)
FIGURE 2-3:
Histogram of Input Offset
Voltage Drift with VDD = 5.5V.
21668A-page 4
0.0
0.5
1.0
1.5
Common Mode Input Voltage (V)
2.0
FIGURE 2-5:
Input Offset Voltage vs.
Common Mode Input Voltage vs. Temperature
with VDD = 1.4V.
600
1200 Samples
VDD = 5.5 V
-10
10
VDD = 1.4 V
-600
-0.5
3
FIGURE 2-2:
Histogram of Input Offset
Voltage with VDD = 1.4V.
30%
5
400
Input Offset Voltage (mV)
35%
0
FIGURE 2-4:
Histogram of Input Offset
Voltage Drift with VDD = 1.4V.
Input Offset Voltage (µV)
Percentage of Occurrences
FIGURE 2-1:
Histogram of Input Offset
Voltage with VDD = 5.5V.
16%
-5
Input Offset Voltage Drift (µV/°C)
VDD = 5.5 V
TA = +85°C
TA = +25°C
TA = -40°C
400
200
0
-200
-400
-600
-0.5
TA = +85°C
TA = +25°C
TA = -40°C
0.5
1.5
2.5
3.5
4.5
Common Mode Input Voltage (V)
5.5
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage vs. Temperature
with VDD = 5.5V.
2002 Microchip Technology Inc.
MCP6141/2/3/4
Input Offset Voltage (µV)
500
RL = 50 k:
450
VDD = 1.4 V
400
350
VDD = 5.5 V
300
250
Input Bias, Offset Currents (pA)
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
50
40
Input Bias Current
30
20
10
Input Offset Current
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
Output Voltage vs. Power Supply Voltage.
TA = 85°C
VDD = 5.5 V
Common Mode Input Voltage (V)
FIGURE 2-10:
Input Bias, Offset Currents
vs. Common Mode Input Voltage with
Temperature = 85°C.
300
Eni = 4.7 µVP-P, f = 0.1 to 10 Hz
eni = 167 nV/—Hz, f = 1 kHz
Input Noise Voltage Density
(nV/—Hz)
Input Noise Voltage Density
(nV/—Hz)
1,000
200
150
100
50
0
-0.5
100
FIGURE 2-8:
vs. Frequency.
100
10
100
Frequency (Hz)
1000
70
CMRR
50
40
30
20
1
10
100
100
1000
Frequency (Hz)
FIGURE 2-9:
Common Mode Rejection
Ratio, Power Supply Rejection Ratio vs.
Frequency.
 2002 Microchip Technology Inc.
1.5
2.5
3.5
4.5
5.5
FIGURE 2-11:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
100
VDD = 5.0 V
PSRR+ Referred to Input
80
60
0.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
PSRR-
90
CMRR, PSRR (dB)
1
CMRR, PSRR (dB)
0.1
f = 1 kHz
VDD = 5.0 V
250
95
90
PSRR (VCM = VSS)
85
80
CMRR (VDD = 5.0 V,
VCM = -0.3 V to +5.3 V)
75
70
-40
-20
0
20
40
60
Ambient Temperature (°C)
80
FIGURE 2-12:
Common Mode Rejection
Ratio, Power Supply Rejection Ratio vs. Ambient
Temperature.
21668A-page 5
MCP6141/2/3/4
50
VCM = VDD
VDD = 5.5 V
40
30
Input Bias
Current
20
10
Input Offset
Current
0
25
35
45
55
65
75
Quiescent Current per amplifier
(mA)
Input Bias and Offset Currents
(pA)
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
0.7
0.6
0.5
0.4
TA = 85°C
0.3
TA = 25°C
TA = -40°C
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
85
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-16:
Quiescent Current Vs.
Power Supply Voltage vs. Temperature.
-30
Gain
80
-60
60
-90
Phase
140
40
-120
20
-150
0
-180
130
120
110
100
90
RL = 50 k:
VOUT = 100 mV to VDD - 100 mV
60
1.0
1.5
2.0 2.5 3.0 3.5 4.0 4.5
Power Supply Voltage (V)
5.0
5.5
FIGURE 2-15:
DC Open Loop Gain vs.
Power Supply Voltage.
21668A-page 6
110
100
VDD = 1.4 V
VOUT = 0.5 V to 0.9 V
90
80
70
1k
10k
Load Resistance (:)
100k
FIGURE 2-17:
DC Open Loop Gain vs.
Load Resistance vs. Power Supply Voltage.
Small Signal DC Open Loop Gain
(dB)
DC Open Loop Gain (dB)
140
70
120
60
100
FIGURE 2-14:
Open Loop Gain, Phase vs.
Frequency with VDD = 5.5V.
80
VDD = 5.5 V
VOUT = 0.5 V to 5.0 V
130
100k
100000
Frequency (Hz)
10k
10000
1k
1000
100
-210
10
0.01
1
VDD = 5.5 V
-20
DC Open-Loop Gain (dB)
0
100
Open-Loop Phase (°)
120
0.1
Open-Loop Gain (dB)
FIGURE 2-13:
Input Bias and Offset
Currents vs. Ambient Temperature.
140
130
RL = 50 k:
VDD = 5.5 V
120
110
VDD = 1.4 V
100
90
80
70
60
0.00
0.05
0.10
0.15
0.20
0.25
0.30
Output Voltage Headroom;
VDD-VOUT or VOUT-VSS (V)
FIGURE 2-18:
Small Signal DC Open Loop
Gain vs. Output Voltage Headroom vs. Power
Supply.
2002 Microchip Technology Inc.
MCP6141/2/3/4
FIGURE 2-19:
Channel to Channel
Separation vs. Frequency (MCP6142 and
MCP6144 only).
60
Phase Margin
60
45
40
30
20
100
15
VDD = 5.5 V
0
-20
0
20
40
60
60
-20
8
60
Phase Margin
2
0
45
30
G = +10 V/V
VDD = 5.5 V
0.00
10p
15
0
0.00
100p
0.00
1n
Load Capacitance (F)
FIGURE 2-21:
Closed Loop Gain
Frequency, Phase Margin vs. Load Capacitance
with VDD = 5.5V.
 2002 Microchip Technology Inc.
Phase Margin (°)
0
0
20
40
60
Ambient Temperature (°C)
80
FIGURE 2-23:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD = 1.4V.
Output Short Circuit Current
(pA)
75
Phase Margin (°)
Closed Loop Gain
Frequency (kHz)
90
15
VDD = 1.4 V
CL = 60 pF
-40
10
4
5.5
30
0
80
Closed Loop Gain Frequency
45
40
20
FIGURE 2-20:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD = 5.5V.
6
5.0
60
Phase Margin
Ambient Temperature (°C)
12
4.5
80
0
-40
75
Phase Margin (°)
75
90
Gain Bandwidth Product
Gain Bandwidth Product
(kHz)
100
120
Phase Margin (°)
Gain Bandwidth Product
(kHz)
FIGURE 2-22:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
90
Gain Bandwidth Product
80
4.0
Common Mode Input Voltage (V)
Frequency (Hz)
120
3.5
10
0
-0.5
10k
10000
20
20
0
3.0
90
1k
1000
30
40
2.5
Input-Referred
Gain Bandwidth Product
2.0
100
60
50
40
60
1.5
110
1.0
120
90
80
70
Phase Margin
120
100
80
0.5
130
180
160
140
0.0
140
Gain Bandwidth Product
(kHz)
Channel-to-Channel Separation
(dB)
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
40
35
-ISC, VDD = 5.5 V
30
+ISC, VDD = 5.5 V
25
20
15
10
5
+ISC, VDD = 1.4 V
-ISC, VDD = 1.4 V
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
FIGURE 2-24:
Output Short Circuit Current
vs. Ambient Temperature vs. Power Supply
Voltage.
21668A-page 7
MCP6141/2/3/4
Falling Edge
Rising Edge
-40
-20
0
20
40
60
Ambient Temperature (°C)
FIGURE 2-25:
Temperature.
Output Voltage Headroom (mV)
Output Voltage Swing (VP-P)
50
45
40
35
30
25
20
15
10
5
0
80
Slew Rate vs. Ambient
VOL-VSS, VDD = 5.5 V
1
1.E-05
10µ
1.E-04
100µ
1.E-03
1m
VDD = 1.4 V
1
0.1
100
100
1k
1000
10k
10000
FIGURE 2-28:
Output Voltage Swing vs.
Frequency vs. Power Supply Voltage.
VOL-VSS, VDD = 1.4 V
10
VDD = 5.5 V
Frequency (Hz)
1,000
100
10
Output Voltage Headroom (mV)
Slew Rate (V/ms)
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
1.E-02
10m
4.0
VDD = 5.5 V
RL = 50 k:
3.5
3.0
2.5
VOL - VSS
2.0
1.5
1.0
VDD - VOH
0.5
0.0
-40
-20
Output Current Magnitude (A)
FIGURE 2-26:
Output Voltage Headroom
vs. Output Current Magnitude vs. Power Supply
Voltage.
0
20
40
60
Ambient Temperature (°C)
80
FIGURE 2-29:
Output Voltage Headroom
vs. Ambient Temperature with VDD = 5.5V.
0.08
0.06
Output Voltage (20 mV/div)
Output Voltage (20 mV/div)
0.08
G = +11 V/V
RL = 50 k:
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
7.E-04
8.E-04
9.E-04
1.E-03
Time (100 µs/div)
FIGURE 2-27:
Small Signal Non-Inverting
Pulse Response vs. Time.
21668A-page 8
G = -10 V/V
RF = 50 k:
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
7.E-04
8.E-04
9.E-04
1.E-03
Time (100 µs/div)
FIGURE 2-30:
Small Signal Inverting Pulse
Response vs. Time.
2002 Microchip Technology Inc.
MCP6141/2/3/4
Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF,
and VOUT ~ V DD/2.
5.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
G = -10 V/V
RF = 50 k:
4.5
Output Voltage (V)
Output Voltage (V)
5.0
G = +11 V/V
RL = 50 k:
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.E+00
2.E-04
4.E-04
6.E-04
8.E-04
1.E-03
1.E-03
1.E-03
2.E-03
2.E-03
0.0
2.E-03
0.E+00
2.E-04
4.E-04
Time (200 µs/div)
VOUT on
VOUT Hi-Z
CS Voltage
0.E+00
1.E-03
2.E-03
3.E-03
4.E-03
5.E-03
6.E-03
7.E-03
8.E-03
9.E-03
1.E-02
FIGURE 2-32:
Chip Select (CS) to
Amplifier Output Response Time
(MCP6143 only).
Input, Output Voltages (V)
1.E-03
1.E-03
2.E-03
2.E-03
2.E-03
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT on
Hysteresis
CS swept
high to low
CS swept
low to high
VOUT HI-Z
G = +11 V/V
VIN = 3.0 V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Chip Select Voltage (V)
Time (1 ms/div)
6
1.E-03
FIGURE 2-34:
Large Signal Inverting Pulse
Response vs. Time.
Output Voltage (V)
VOUT on
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Output Voltage (V)
Chip Select Voltage (V)
G = +11 V/V
V IN = 3.0 V
8.E-04
Time (200 µs/div)
FIGURE 2-31:
Large Signal Non-Inverting
Pulse Response vs. Time.
27.5
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0.0
6.E-04
FIGURE 2-35:
Output Voltage vs. Chip
Select (CS) Voltage (MCP6143 only).
G = +11 V/V
5
4
3
2
VIN
1
VOUT
0
-1
0.E+00
5.E-03
1.E-02
2.E-02
2.E-02
3.E-02
Time (5 ms/div)
FIGURE 2-33:
The MCP6141/2/3/4 family
shows no phase reversal (for information only–
the Maximum Absolute Input Voltage is still
VSS - 0.3V and VDD + 0.3V).
 2002 Microchip Technology Inc.
21668A-page 9
MCP6141/2/3/4
3.0
APPLICATIONS INFORMATION
3.3
Rail-to-Rail Output
The MCP6141/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are stable for noise gain of 10 V/V or
higher. Microchip also produces a unity gain stable
product, the MCP6041/2/3/4 family, which has similar
specifications. The MCP6041/2/3/4 family has a bandwidth of 1.4 kHz at a noise gain of 10 V/V, while the
MCP6141/2/3/4 family has a bandwidth of 10 kHz at a
noise gain of 10 V/V. These devices are suitable for a
wide range of applications requiring very low power
consumption. With these op amps, the power supply
pin needs to be bypassed with a 0.1 µF capacitor.
The MCP6141/2/3/4 family Maximum Output Voltage
Swing defines the maximum swing possible under a
particular output load. According to the specification
table, the output can reach up to 10 mV of either supply
rail with a 50 kΩ load.
3.1
The maximum operating VCM that can be applied to the
inputs is VSS -0.3V and VDD + 0.3V. Voltage on the
input that exceeds this absolute maximum rating can
cause excessive current to flow in or out of the input
pins. Current beyond ±2 mA can cause possible reliability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 3-1.
Rail-to-Rail Input
The input stage of these devices uses two differential
input stages in parallel; one operates at low VCM (common mode input voltage) and the other at high V CM.
With this topology, the MCP6141/2/3/4 family operates
with VCM up to 300 mV past either supply rail. The Input
Offset Voltage is measured at both VCM = VSS - 0.3V
and VDD + 0.3V to ensure proper operation.
3.2
3.4
Input Voltage and Phase Reversal
The MCP6141/2/3/4 op amp family uses CMOS transistors at the input. It is designed to prevent phase
reversal when the input pins exceed the supply voltages. Figure 2-33 shows an input voltage exceeding
both supplies without output phase reversal.
Output Loads and Battery Life
The MCP6141/2/3/4 op amp family has low quiescent
current, which supports battery-powered applications.
There is minimal quiescent current glitch when chip
select (CS) is raised or lowered. This prevents excessive current draw and reduced battery life when the
part is turned off or on.
Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across
a 100 kΩ load resistor will cause the supply current to
increase by 25 µA, depleting the battery 43 times as
fast as IQ (0.6 µA typ) alone.
High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current.
For instance, a 0.1 µF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz
sinewave. It can be shown that the average power
drawn from the battery by a 5.0 Vp-p sinewave
(1.77 Vrms) under these conditions is:
EQUATION
P SUPPLY = ( V DD – V SS ) ( I Q + V L ( p – p ) fC L )
= ( 5V ) ( 0.6µA + 5.0V p – p ⋅ 100Hz ⋅ 0.1µF )
= 3.0µW + 50µW
This will drain the battery 18 times as fast as IQ alone.
21668A-page 10
RIN
MCP614X
VOUT
VIN
( Maximum expected V IN ) – V DD
R IN ≥ -----------------------------------------------------------------------------2 mA
V SS – ( Minimum expected V IN )
R IN ≥ --------------------------------------------------------------------------2 mA
FIGURE 3-1:
An input resistor, RIN,
should be used to limit excessive input current if
the inputs exceed the absolute maximum
specification.
3.5
Stability
The MCP6141/2/3/4 op amp family is designed to give
high bandwidth and faster slew rate for circuits with
high noise (Gn) or signal gain. The related unity-gain
stable MCP6041/2/3/4 op amp family has lower AC
performance, but it is preferable for low noise gain
applications.
Noise gain is defined to be the gain from a voltage
source at the non-inverting input to the output when all
other voltage sources are zeroed (shorted out). Noise
gain is independent of signal gain and depends only on
components in the feedback loop.
2002 Microchip Technology Inc.
MCP6141/2/3/4
RG
Note that the integrator circuit in Figure 3-3 becomes
unity gain at high frequencies because of the capacitor. Therefore, this circuit is unstable for the
MCP6141/2/3/4.
RF
MCP614X
VOUT
VIN
Non-inverting noise gain: 1 + RF/RG ≥ +10 V/V
RG
VIN
RF
MCP614X
VOUT
Inverting noise gain: 1 + RF/R G ≥ +10 V/V
FIGURE 3-2:
Noise gain for inverting and
non-inverting amplifier configuration.
Figure 3-2 shows non-inverting and inverting amplifier
circuits. In order for the amplifiers to be stable, the
noise gain should meet the specified requirement:
3.6
Capacitive Load and Stability
Driving capacitive loads can cause stability problems
with voltage feedback op amps. Figure 2-21 shows how
increasing the load capacitance will decrease the phase
margin. While a phase margin above 60° is ideal, 45° is
on the verge of instability. As can be seen, up to
CL = 150 pF can be placed on the MCP6141/2/3/4 op
amp outputs without any problems, while 250 pF creates a 45° phase margin.
When the op amp is required to drive large capacitive
loads (CL >150 pF), a small series resistor (RISO in
Figure 3-4) at the output of the amplifier improves the
phase margin. This resistor makes the output load
resistive at higher frequencies, which improves the
phase margin. The bandwidth reduction caused by the
capacitive load, however, is not changed. To select
RISO, start with 1 kΩ, then use the MCP6141 SPICE
macro model and bench testing to adjust RISO until
there is a minimum frequency response peaking.
EQUATION
R2
R1
RF
G n = 1 + ------- ≥ 10V/V
RG
RISO
Note that an inverting signal gain of G = -9 V/V corresponds to a noise gain G n = +10 V/V.
Figure 3-3 shows a unity gain buffer and integrator that
are unstable when used with the MCP6141/2/3/4 family. However, they are suitable for the MCP6041/2/3/4
family.
VIN
VOUT
VIN
R
Unity gain buffer:
Unstable for MCP614X
C
VIN
MCP604X
CL
FIGURE 3-4:
capacitive loads.
3.7
MCP604X
VOUT
MCP614X
Amplifier circuit for heavy
The MCP6143 Chip Select (CS)
Option
The MCP6143 is a single amplifier with a chip select
(CS) option. When CS is pulled high, the supply current
drops to 20 pA (typ.) and goes through the CS pin to
VSS. When this happens, the amplifier is put into a high
impedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier will
not operate properly. Figure 3-5 shows the output
voltage and supply current response to a CS pulse.
VOUT
Integrator:
Unstable for MCP614X
FIGURE 3-3:
Typical Circuits that are not
suitable for the MCP6141/2/3/4 family.
 2002 Microchip Technology Inc.
21668A-page 11
MCP6141/2/3/4
CS
VIL
VIH
tOFF
tON
VOUT
Hi-Z
Hi-Z
0.6 µA, typ
IVDD
Circuit schematics for different guard ring implementations are shown in Figure 3-7. Figure 3-7A biases the
guard ring to the input common mode voltage, which is
most effective for non-inverting gains. Figure 3-7B
biases the guard ring to a reference voltage (VREF,
which can be ground), which is useful for inverting
gains and precision photo sensing circuits.
Figure 3-7A
5 pA, typ
5 pA, typ
VDD
0.6 µA, typ
20 pA, typ
IVSS 20 pA, typ
ICS
5 pA, typ
5 pA, typ
FIGURE 3-5:
Timing Diagram for the CS
function on the MCP6143 op amp.
3.8
MCP614X
VREF
Figure 3-7B
VDD
Layout Considerations
Good PC board layout techniques will help you achieve
the performance shown in the specifications and typical
performance curves. It will also assist in minimizing
Electro-Magnetic Compatibility (EMC) issues.
3.8.1
SURFACE LEAKAGE
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace to trace need to be considered.
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 1012Ω. A 5V difference would cause 5 pA of current
to flow, which is greater than the input current of the
MCP6141/2/3/4 family at 25°C (1 pA, typ).
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace. Figure 3-6 shows an example of
a typical layout.
IN-
IN+
MCP614X
VREF
FIGURE 3-7:
Two possible guard ring
connection strategies to reduce surface leakage
effects.
3.8.2
COMPONENT PLACEMENT
In order to help prevent crosstalk:
• Separate digital components from analog components, and low speed devices from high speed
devices.
• Keep sensitive traces short and straight. Separate
them from interfering components and traces.
This is especially important for high frequency
(low rise time) signals.
• Use a 0.1 µF supply bypass capacitor within 0.1”
(2.5 mm) of the VDD pin. It must connect directly
to the ground plane.
VSS
Guard Ring
FIGURE 3-6:
layout.
21668A-page 12
Example of Guard Ring
2002 Microchip Technology Inc.
MCP6141/2/3/4
3.8.3
3.9
SIGNAL COUPLING
The input pins of the MCP6141/2/3/4 family of op amps
are high impedance, which allows noise injection. This
noise can be capacitively or magnetically coupled. In
either case, using a ground plane helps reduce noise
injection.
When noise is coupled capacitively, the ground plane
provides shunt capacitance to ground for high frequency signals (Figure 3-8 shows the equivalent circuit). The coupled current, IM, produces a lower voltage
(VTRACE 2) on the victim trace when the trace to ground
plane capacitance (C SH2) is large and the terminating
resistor (RT2) is small. Increasing the distance between
traces and using wider traces also helps.
CM
IM
VTRACE 1
CSH1
VTRACE 2
CSH2
Typical Applications
3.9.1
BATTERY CURRENT SENSING
The MCP6141/2/3/4 op amps’ Common Mode Input
Range, which goes 300 mV beyond both supply rails,
supports their use in high side and low side battery
current sensing applications. The very low quiescent
current (0.6 µA, typ.) help prolong battery life, while the
rail-to-rail output allows you to detect low currents.
Figure 3-9 shows a high side battery current sensor circuit. The feedback and input resistors are sized to minimize power losses. The battery current (IDD) through
the 1 kΩ resistor causes its top terminal to be more
negative than the bottom terminal. This keeps the common mode input voltage of the op amp ≤ VDD, which is
within its allowed range. The output of the op amp can
reach VDD - 0.1 mV (see Figure 2-26), which is a
smaller error than the offset voltage.
RT2
VDD
FIGURE 3-8:
Equivalent circuit for
capacitive coupling between traces on a PC
board (with ground plane).
When noise is coupled magnetically, the ground plane
reduces the mutual inductance between traces. This
occurs because the ground return current at high frequencies will follow a path directly beneath the signal
trace. Increasing the separation between traces makes
a significant difference. Changing the direction of one
of the traces can also reduce magnetic coupling.
If these techniques are not enough, it may help to place
guard traces next to the victim trace. They should be on
both sides of the victim trace and be as close as possible. Connect the guard traces to ground plane at both
ends and in the middle for long traces.
VDD
IDD
1k Ω
+1.4 V
to
5.5 V
MCP614X
VSS
100 kΩ
1 MΩ
FIGURE 3-9:
Sensor.
3.9.2
High Side Battery Current
SUMMING AMPLIFIER
The rail-to-rail input and output, the 600 nA (typ.) quiescent current and the wide bandwidth make the
MCP6141/2/3/4 family of operational amplifiers fit well
in a summing amplifier circuit, as shown in Figure 3-10.
V1
V2
V3
R1
I
R2 1
I
R3 2
I3
VREF
RF
-
IF
+
VOUT
MCP614X
FIGURE 3-10:
 2002 Microchip Technology Inc.
Summing amplifier circuit.
21668A-page 13
MCP6141/2/3/4
In this configuration, the amplifier outputs the sum of
the three input voltages. The ratio of the sum and the
output voltage is defined using the feedback and input
resistors. V REF is used to offset the output voltage. This
family of amplifiers is stable for noise gain (G n) of 10 V/
V or higher. The Gn and the signal gain of the summing
amplifier is calculated as shown below:
EQUATION
Noise Gain:
1
1
1
G n = 1 + R F  ------ + ------ + ------ ≥ 10 V/V
 R 1 R 2 R 3
Signal Gain:
–R
V 01 = ---------F × V 1
R1
–R
V 02 = ---------F × V 2
R2
–R
V 03 = ---------F × V 3
R3
RF RF RF
V 04 =  1 + ------ + ------ + ------ × V REF

R 1 R 2 R 3
V OUT = V 01 + V 02 + V 03 + V 04
VOUT
V
– V 1 V REF – V 2 V REF – V 3
REF
= R F ---------------------- + ---------------------- + ---------------------- + V REF
R
R
R
1
2
3
At a noise gain of 10 V/V, the amplifier bandwidth is
approximately 10 kHz. The bandwidth to quiescent current ratio of MCP6141/2/3/4 makes this device an
appropriate choice for battery-powered applications.
21668A-page 14
2002 Microchip Technology Inc.
MCP6141/2/3/4
4.0
SPICE MACRO MODEL
The Spice macro model for the MCP6141, MCP6142,
MCP6143 and MCP6144 simulates the typical amplifier performance of offset voltage, DC power supply
rejection, input capacitance, DC common mode rejection, open loop gain over frequency, phase margin, output swing, DC power supply current, power supply
current change with supply voltage, input common
mode range, output voltage range vs. load and input
voltage noise.
The characteristics of the MCP6141, MCP6142,
MCP6143 and MCP6144 amplifiers are similar in terms
of performance and behavior. This single op amp
macro model supports all four devices, with the exception of the chip select function of the MCP6143, which
is not modeled.
The listing for this macro model is shown on the next
page. The most recent revision of the model can be
downloaded from
Microchip’s
web site at
www.microchip.com.
 2002 Microchip Technology Inc.
21668A-page 15
MCP6141/2/3/4
Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, the Company’s customer, for use solely and exclusively on Microchip products.
The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.
Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
.SUBCKT MCP6141 1 2 3 4 5
*
| | | | |
*
| | | | Output
*
| | | Negative Supply
*
| | Positive Supply
*
| Inverting Input
*
Non-inverting Input
*
* Macromodel for the MCP6141/2/3/4 op amp family:
*
MCP6141 (single)
*
MCP6142 (dual)
*
MCP6143 (single w/ CS; chip select is not modeled)
*
MCP6144 (quad)
*
* Revision History:
*
REV A: 06-Sep-02, KEB (created model)
*
* Recommendations:
*
Use PSPICE (or SPICE 2G6; other simulators may require translation)
*
For a quick, effective design, use a combination of: data sheet
*
specs, bench testing, and simulations with this macromodel
*
For high impedance circuits, set GMIN=100F in the .OPTIONS
*
statement
*
* Supported:
*
Typical performance at room temperature (25 degrees C)
*
DC, AC, Transient, and Noise analyses.
*
Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
*
open loop gain, voltage ranges, supply current, ... , etc.
*
* Not Supported:
*
Chip select (MCP6143)
*
Variation in specs vs. Power Supply Voltage
*
Distortion (detailed non-linear behavior)
*
Temperature analysis
*
Process variation
*
Behavior outside normal operating region
*
* Input Stage
V10 3 10 -300M
R10 10 11 258K
R11 10 12 258K
C11 11 12 3.53P
C12 1 0 6.00P
E12 1 14 POLY(4) 20 0 21 0 26 0 27 0
1.00M 117 117 1 1
I12 14 0 1.50P
M12 11 14 15 15 NMI L=2.00U W=5.00U
C13 14 2 6.00P
M14 12 2 15 15 NMI L=2.00U W=5.00U
I14 2 0 500E-15
C14 2 0 6.00P
 2002 Microchip Technology Inc.
21668A-page 16
MCP6141/2/3/4
I15 15 4 300N
V16 16 4 200M
D16 16 15 DL
V13 3 13 50.0M
D13 14 13 DL
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20 0 DN1
D21 0 21 DN1
G26 0 26 POLY(1) 3 4
308U -56.0U
R26 26 0 1
G27 0 27 POLY(2) 1 3 2 4
-979U 178U 178U
R27 27 0 1
*
* Open Loop Gain, Slew Rate
G30 0 30 POLY(1) 12 11
0 1.00K
R30 30 0 1
E31 31 0 POLY(1) 3 4
29.3 1.05
D31 30 31 DL
E32 0 32 POLY(1) 3 4
57.0 2.04
D32 32 30 DL
G33 0 33 POLY(1) 30 0
0 562
R33 33 0 1
C33 33 0 838M
G34 0 34 POLY(1) 33 0
0 1.00
R34 34 0 1.00
C34 34 0 8.53U
G35 0 35 POLY(2) 34 0 33 34
0 1.00 1.22
R35 35 0 1.00
*
* Output Stage
G50 0 50 POLY(1) 57 5
0 1.00
D51 50 51 DL
R51 51 0 1K
D52 52 50 DL
R52 52 0 1K
G53 3 0 POLY(1) 51 0
300N 1M
G54 0 4 POLY(1) 52 0
300N -1M
E55 55 0 POLY(2) 3 0 51 0
-10M 1 -100M
D55 57 55 DLS
E56 56 0 POLY(2) 4 0 52 0
10M 1 -100M
D56 56 57 DLS
G57 0 57 POLY(3) 3 0 4 0 35 0
0 17.8U 17.8U 35.5U
R57 57 0 28.2K
R58 57 5 1.00
C58 5 0 2.00P
*
* Models
.MODEL NMI NMOS
.MODEL DL D
N=1
IS=1F
.MODEL DLS D
N=10M IS=1F
.MODEL DN1 D
IS=1F KF=1.17E-18 AF=1
*
.ENDS MCP6141
 2002 Microchip Technology Inc.
21668A-page 17
MCP6141/2/3/4
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
MCP6141
I/P058
0223
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
MCP6142
I/SN0223
NNN
058
8-Lead MSOP
Note:
Example:
XXXXXX
6143I
YWWNNN
223058
Legend:
*
Example:
XX...X
YY
WW
NNN
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
21668A-page 18
2002 Microchip Technology Inc.
MCP6141/2/3/4
5.1
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6144)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (150 mil) (MCP6144)
Example:
MCP6144-I/P
0223058
Example:
MCP6144ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6144)
0223058
Example:
XXXXXX
YYWW
6144ST
0223
NNN
058
 2002 Microchip Technology Inc.
21668A-page 19
MCP6141/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
21668A-page 20
2002 Microchip Technology Inc.
MCP6141/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
 2002 Microchip Technology Inc.
21668A-page 21
MCP6141/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
p
E1
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Number of Pins
Pitch
Dimension Limits
n
p
Overall Height
NOM
MAX
8
0.65
.026
A
.044
.030
Standoff
A1
.002
E
.184
Molded Package Width
MIN
8
A2
Overall Width
MAX
NOM
Molded Package Thickness
§
MILLIMETERS*
INCHES
MIN
1.18
.038
0.76
.006
0.05
.193
.200
.034
0.86
0.97
4.67
4.90
.5.08
0.15
E1
.114
.118
.122
2.90
3.00
3.10
Overall Length
D
.114
.118
.122
2.90
3.00
3.10
Foot Length
L
.016
.022
.028
0.40
0.55
0.70
Footprint (Reference)
.035
.037
.039
0.90
0.95
1.00
Foot Angle
F
φ
6
0
Lead Thickness
c
.004
.006
.008
0.10
0.15
0.20
Lead Width
B
α
.010
.012
.016
0.25
0.30
0.40
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
6
7
7
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
21668A-page 22
2002 Microchip Technology Inc.
MCP6141/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
eB
B1
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
 2002 Microchip Technology Inc.
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
21668A-page 23
MCP6141/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
21668A-page 24
2002 Microchip Technology Inc.
MCP6141/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B1
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
 2002 Microchip Technology Inc.
21668A-page 25
MCP6141/2/3/4
NOTES:
21668A-page 26
2002 Microchip Technology Inc.
MCP6141/2/3/4
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
092002
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2002 Microchip Technology Inc.
DS21668A-page 27
MCP6141/2/3/4
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
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Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: MCP6141/2/3/4
Y
N
Literature Number: DS21668A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21668A-page 28
 2002 Microchip Technology Inc.
MCP6141/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
X
/XX
Temperature
Range
Package
MCP6141: CMOS Single Op Amp
MCP6141T: CMOS Single Op Amp
(Tape and Reel for SOIC, MSOP)
MCP6142: CMOS Dual Op Amp
MCP6142T: CMOS Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
MCP6143: CMOS Single Op Amp w/CS Function
MCP6143T: CMOS Single Op Amp w/CS Function
(Tape and Reel for SOIC and MSOP)
MCP6144: CMOS Quad Op Amp
MCP6144T: CMOS Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range:
I
= -40°C to +85°C
Package:
MS
P
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4mm Body), 14-lead
Examples:
a)
MCP6141-I/P:
PDIP package.
Industrial
temperature,
b)
MCP6141T-I/SN: Tape and Reel, Industrial temperature, SOIC package.
a)
MCP6142-I/SN:
SOIC package.
Industrial
temperature,
b)
MCP6142-I/MS:
MSOP package.
Industrial
temperature,
a)
MCP6143-I/MS:
MSOP package.
Industrial
temperature,
b)
MCP6143-I/P:
PDIP package.
Industrial
temperature,
a)
MCP6144-I/SL:
SIOC package.
Industrial
temperature,
b)
MCP6144T-I/ST: Tape and Reel, Industrial temperature, TSSOP package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2002 Microchip Technology Inc.
DS21668A-page 29
MCP6141/2/3/4
NOTES:
DS21668A-page 30
 2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, K EELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro ® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
DS21668A - page 31
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
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Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Rocky Mountain
China - Beijing
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Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
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Tel: 86-10-85282100 Fax: 86-10-85282104
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Co., Ltd.
Room 701, Bldg. B
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Tel: 86-755-2350361 Fax: 86-755-2366086
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EUROPE
Austria
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Denmark
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France
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Italy
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United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
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Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
08/01/02
DS21668A-page 32
 2002 Microchip Technology Inc.