Intersil ISL9113A Skip mode under light-load condition Datasheet

DATASHEET
Low Input Voltage and High Efficiency, Synchronous
Boost Converter with 1.3A Switch
ISL9113A
Features
The ISL9113A provides a power supply solution for devices
powered by three-cell alkaline, NiCd, NiMH, or one-cell
Li-Ion/Li-Polymer batteries. It offers either a fixed 5V or an
adjustable output option for USB-OTG or portable HDMI
applications. The device is guaranteed to supply 500mA from
a 3V input and 5V output, and has a typical 1.3A peak current
limit. High 1.8MHz switching frequency allows for the use of
tiny, low-profile inductors, and ceramic capacitors to minimize
the size of the overall solution.
• Up to 95% efficiency at typical operating conditions
• Input voltage range: 0.8V to 4.7V
• Output current: Up to 500mA (VBAT = 3.0V, VOUT = 5.0V)
• Low quiescent current: 20μA (typical)
• Logic control shutdown (IQ < 1µA)
• 1.2V EN high logic
• Output disconnect during shutdown
The ISL9113A is an internally compensated, fully integrated
synchronous converter optimized for efficiency with minimal
external components. At light load, the device enters Skip
mode and consumes only 20µA of quiescent current, resulting
in higher efficiency at light loads and maximum battery life.
• Skip mode under light-load condition
The device is available in an 8 Ld DFN package.
Applications
Related Literature
• Undervoltage lockout
• Fault protection: OVP, OTP, short-circuit
• 8 Ld 2mmx2mm DFN Package
• Products including portable HDMI and USB-OTG
• Smartphones
• For a full list of related documents, visit our website
- ISL9113A product page
• Tablet and mobile internet devices
100
90
5
VOUT
2
VOUT =
5.0V/500mA
R1
523k
VBAT
FB
EN
4
R2
100k
GND
1
4.7µF
EFFICIENCY (%)
4.7µF
SW
7
VBAT = 3.0V
85
8
VBAT =
0.8 TO 4.7V
VBAT = 4.2V
VBAT = 3.6V
95
2.2µH
80
75
January 4, 2017
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1
VBAT = 1.2V
65
60
55
50
0.0001
FIGURE 1. TYPICAL APPLICATION
VBAT = 2.3V
70
VOUT = 5.0V
0.001
0.01
LOAD CURRENT (A)
0.1
1
FIGURE 2. EFFICIENCY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2017. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9113A
Block Diagram
C1
VOUT
VBAT
C2
7
UVLO
VINT
2
VOLTAGE
SELECTOR
START-UP
N-WELL
SWITCH
GATE
DRIVER
VOUT
OVP
SW
L1
8
AND
ANTI-CROSS
CONDUCTION
SW
ZCD
EN
VOUT
5
OFF
ON
CURRENT
SENSE
CONTROL LOGIC
R1
AND
DIGITAL
SOFT-START
CURRENT
LIMIT
SLOPE COMP
FB
FAULT
MONITORING
4
gm
R2
1.8MHz
OSCILLATOR
VINT
VOLTAGE
CLAMP
REFERENCE
GENERATOR
THERMAL
SHUTDOWN
1
6
FIGURE 3. BLOCK DIAGRAM
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ISL9113A
Pin Configuration
Pin Descriptions
ISL9113A
(8 LD DFN)
TOP VIEW
PGND
1
VOUT
2
8
SW
7
VBAT
PIN
NUMBER
PIN
NAME
1
PGND
Power ground
2
VOUT
Device output
3
NC
No connection
4
FB
Feedback pin of the converter. Connect voltage
divider resistors between VOUT, FB, and GND for
desired output.
5
EN
The EN pin is an active-HIGH logic input for
enabling the device. When asserted HIGH, the
boost function begins. When asserted LOW, the
device is completely disabled, and current is
blocked from flowing from the SW pin to the
output, and vice versa. This pin should be tied
either HIGH to enable the device, or LOW to
disable the device.
6
AGND
7
VBAT
Device input supply from a battery. Connect a
4.7µF ceramic capacitor to the power ground.
8
SW
The SW pin is the switching node of the power
converter. Connect one terminal of the inductor to
the SW pin and the other to power input.
EPAD
The exposed pad must be connected to PGND pin
for proper electrical performance. Place as many
vias as possible under the pad connecting to the
system GND plane for optimal thermal
performance.
EPAD
NC
3
6
AGND
FB
4
5
EN
PIN DESCRIPTION
Analog ground
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT
(V)
TEMP RANGE
(°C)
TAPE AND REEL
(UNITS)
Adjustable
-40 to +85
6k
ISL9113AIRAZ-T
3AA
ISL9113AIRAZ-EVZ
Evaluation Board for ISL9113AIRAZ-T
PACKAGE
(RoHS COMPLIANT)
8 Ld DFN
PKG.
DWG. #
L8.2x2D
NOTES:
1. Refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for ISL9113A. For more information on MSL see Tech Brief TB363.
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ISL9113A
Absolute Maximum Ratings
Thermal Information
VBAT, EN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
SW Voltage
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Pulse <10ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 8.0V
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
(Other ESD specifications should meet Level 1 requirement)
Latch-Up (Tested per JESD78; Class 2, Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld DFN Package (Notes 4, 5). . . . . . . . . .
80
15
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to+125°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to+85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VBAT (After start-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 4.7V
VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VBAT + 0.2V) to 5.2V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
-40°C to +85°C.
PARAMETER
VBAT = 3.0V, VOUT = 5.0V, TA = +25°C. Boldface limits apply across the operating temperature range,
SYMBOL
TEST CONDITIONS
Start-Up Voltage
VMIN
VEN = VBAT, RLOAD = 50Ω
Input Undervoltage Lockout
VUVLO
VEN = VBAT, RLOAD = 50Ω
Feedback Voltage
VFB
Output Voltage
VOUT
VBAT = 2.8V
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
0.75
0.90
V
0.66
0.70
0.76
V
784
800
816
mV
5.2
V
100
nA
3.0
VFB = 0.8V
Feedback Pin Input Current
Quiescent Current from VOUT
IQ1
VBAT = VEN = 1.2V, no load (Note 7)
20
45
μA
Shutdown Current from VBAT
ISD
VEN = 0V, VBAT = 1.2V, VO = 0
0.5
2.8
μA
1.0
μA
VEN = 0V, VBAT = 4.7V, VO = 0
Leakage Current at SW Pin
N-Channel MOSFET ON-Resistance
0.20
Ω
P-Channel MOSFET ON-Resistance
0.35
Ω
IPK
1.1
1.3
Maximum Duty Cycle
DMAX
82
87.5
PWM Switching Frequency
FOSC
1.5
1.8
N-Channel MOSFET Peak Current Limit
EN Logic High
2.5V < VBAT < 4.7V
VBAT < 2.5V
Line Regulation
V
0.2
ILOAD = 0 to 50mA
-1.5
VBAT = 3.0V to 3.6V, ILOAD = 1mA
-1.0
Output Overvoltage Protection Threshold
Thermal Shutdown
MHz
V
COUT = 4.7μF, L = 2.2μH
ΔVOUT/VOUT
Load Regulation
2.0
1.2
VBAT < 2.5V
Soft Start-Up Time
A
%
0.48*VBAT
2.5V < VBAT < 4.7V
EN Logic Low
1.5
TSD
Thermal Shutdown Hysteresis
0.35
V
0.14*VBAT
V
1
ms
+1.5
%
+1.0
%
5.9
V
150
oC
25
oC
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
7. IQ1 is measured at VOUT and multiplied by VOUT/VBAT; thus, the equivalent input quiescent current is calculated.
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ISL9113A
Detailed Description
Current Mode PWM Operation
The control scheme of the device is based on the peak current
mode control and the control loop is compensated internally. The
peak current of the N-channel MOSFET switch is sensed to limit
the maximum current flowing through the switch and the
inductor. The typical current limit is set to 1.3A.
The control circuit includes a ramp generator, slope
compensator, error amplifier, and a PWM comparator (see
“Block Diagram” on page 2). The ramp signal is derived from the
inductor current. This ramp signal is then compared to the error
amplifier output to generate the PWM gating signals for driving
both N-channel and P-channel MOSFETs. The PWM operation is
initialized by the clock from the internal oscillator (typical
1.8MHz). The N-channel MOSFET is turned ON at the beginning of
a PWM cycle, the P-channel MOSFET remains OFF, and the
current starts ramping up. When the sum of the ramp and the
slope compensator output reaches the error amplifier output
voltage, the PWM comparator outputs a signal to turn OFF the
N-channel MOSFET. Here, both MOSFETs remain OFF during the
dead-time interval. Next, the P-channel MOSFET is turned ON and
remains ON until the end of this PWM cycle. During this time, the
inductor current ramps down until the next clock. At this point,
following a short dead time, the N-channel MOSFET is again
turned ON, repeating as previously described.
Skip Mode Operation
The boost converter is capable of operating in two different
modes. When the inductor current is sensed to cross zero for
eight consecutive times, the converter enters Skip mode. In Skip
mode, each pulse cycle is still synchronized by the PWM clock.
The N-channel MOSFET is turned ON at the rising edge of the
clock and turned OFF when the inductor peak current reaches
typically 25% of the current limit. Then, the P-channel MOSFET is
turned ON, and it stays ON until its current goes to zero.
Subsequently, both N-channel and P-channel MOSFETs are
turned OFF until the next clock cycle starts, at which time the
N-channel MOSFET is turned ON again. When VOUT is 1.5% higher
than the nominal output voltage, the N-channel MOSFET is
immediately turned OFF, and the P-channel MOSFET is turned ON
until the inductor current goes to zero. The N-channel MOSFET
resumes operation when VFB falls back to its nominal value,
repeating the previous operation. The converter returns to
1.8MHz PWM mode operation when VFB drops 1.5% below its
nominal voltage.
Given the Skip mode algorithm incorporated in the ISL9113A,
the average value of the output voltage is approximately 0.75%
higher than the nominal output voltage under PWM operation.
This positive offset improves the load transient response when
switching from Skip mode to PWM mode operation. The ripple on
the output voltage is typically 1.5%*VOUT (nominal) when input
voltage is sufficiently lower than output voltage, and it increases
as the input voltage approaches the output voltage.
Because the commonly used discrete Schottky rectifier is
replaced with the low rDS(ON) P-channel MOSFET, the power
conversion efficiency reaches a value above 90%. Since a typical
step-up converter has a conduction path from the input to the
output via the body diode of the P-channel MOSFET, a special
circuit (see “Block Diagram” on page 2) is used to reverse the
polarity of the P-channel body diode when the device is shut
down. Thus, this configuration completely disconnects the load
from the input during shutdown of the converter. The benefit of
this feature is that the battery will not be completely depleted
during shutdown of the converter. No additional components are
needed to disconnect the battery from the output of the
converter.
Soft-Start
The soft start-up duration is the time between the device being
enabled and VOUT rising to within 3% of target voltage. When the
device is enabled, the start-up cycle starts with a linear phase.
During the linear phase, the rectifying switch is turned ON in a
current limited configuration, delivering about 350mA, until the
output capacitor is charged to approximately 90% of the input
voltage. At this point, PWM operation begins in Boost mode. If
the output voltage is below 2.3V, PWM switching is done at a
fixed duty-cycle of 75% until the output voltage reaches 2.3V.
When the output voltage exceeds 2.3V, the closed-loop current
mode PWM loop overrides the duty cycle until the output voltage
is regulated. Peak inductor current is ramped to the final value
(typically 1.3A) during the soft-start period to limit inrush current
from the input source. Fault monitoring begins approximately
2ms after the device is enabled.
Over-Temperature Protection (OTP)
The device offers over-temperature protection. A temperature
sensor circuit is integrated and monitors the internal IC
temperature. Once the temperature exceeds the preset threshold
(typically +150°C), the IC shuts down immediately. The OTP has
a typical hysteresis of +25°C. When the device temperature
decreases by this, the device starts operating.
Printed Circuit Board Layout
Recommendations
The ISL9113A is a high-frequency, switching boost converter.
Accordingly, the converter has fast voltage change and high
switching current that may cause EMI and stability issues if the
layout is not done properly. Therefore, careful layout is critical to
minimize the trace inductance and reduce the area of the power
loop.
Power components, such as input capacitor, inductor, and output
capacitor, should be placed close to the device. Board traces that
carry high switching current should be routed wide and short. A
solid power ground plane is important for EMI suppression.
Synchronous Rectifier
The switching node (SW pin) of the converter and the traces
connected to this pin are very noisy. Noise sensitive traces, such
as the FB trace, should be kept away from SW node. The voltage
divider should be placed close to the FB pin to prevent noise
pickup. Figure 4 on page 6 shows the recommended PCB layout.
The ISL9113A integrates one N-channel MOSFET and one
P-channel MOSFET to realize a synchronous boost converter.
In the 8 Ld DFN package, the heat generated in the device is
mainly dissipated through the thermal pad. Maximizing the
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ISL9113A
copper area connected to the thermal pad is preferable. It is
recommended to add at least four vias within the pad to the GND
plane for the best thermal relief.
Capacitor Selection
INPUT CAPACITOR
A minimum of a 4.7µF ceramic capacitor is recommended to
provide stable operation under typical operating conditions. For
input voltage less than 1.0V application, an additional 4.7µF
ceramic capacitor is recommended for better noise filtering and
EMI suppression. The input capacitor should be placed close to
the input pin, GND pin, and the non-switching terminal of the
inductor.
OUTPUT CAPACITOR
For the output capacitor, a ceramic capacitor with small ESR is
recommended to minimize output voltage ripple. A typical 4.7µF
should be used to provide stable operation at different typical
operating conditions. The output capacitor should be placed
close to the output pin and GND pin of the device. Table 2 shows
the recommended capacitors.
TABLE 2. CAPACITOR VENDOR INFORMATION
MANUFACTURER
FIGURE 4. RECOMMENDED PCB LAYOUT
Output Voltage Setting Resistor Selection
Resistors R1 and R2, shown in the “Block Diagram” on page 2,
can be used to set the desired output voltage values using
Equation 1:
R 1

V OUT = V FB   1 + -------
R 2

X5R
www.avx.com
Murata
X5R
www.murata.com
Taiyo Yuden
X5R
www.t-yuden.com
TDK
X5R
www.tdk.com
TABLE 3. FAULT DETECTION AND RESPONSE
FAULT CONDITION
Inductor Selection
An inductor with core material suitable for high-frequency
applications (e.g., ferrite) is desirable to minimize core loss and
improve efficiency. The inductor should have a low ESR to reduce
copper loss. Moreover, the inductor saturation current should be
higher than the maximum peak current of the device; i.e., 1.5A.
The device is designed to operate with an inductor value of 2.2µH
to provide stable operation across the range of load, input, and
output voltages. Stable mode switching between PWM and Skip
mode operation is guaranteed at this inductor value. Table 1
shows recommended inductors.
WEBSITE
AVX
(EQ. 1)
where VFB is the internal FB reference voltage (0.8V typical). The
current flowing through the divider resistors is calculated as
VOUT /(R1 + R2). Large resistance is recommended to minimize
current into the divider, and thus improve the total efficiency of
the converter. R1 and R2 should be placed close to the FB pin of
the device to prevent noise pickup.
SERIES
Low Battery Voltage
DETECTION DETAILS
VBAT < 0.7V
VOUT Out of Regulation VOUT is 10% below
the target output
voltage
ACTION
Shut down until VEN or
VBAT is cycled.
Shut down only if VBAT
and VOUT fall below 2.1V.
Device automatically
restarts after 200ms.
Short-Circuit
VOUT falls below VBAT Shut down immediately.
Device automatically
restarts after 200ms.
Over-Temperature
Protection
Die temperature is
> +150°C
Switching stops. Device
automatically restarts
when temperature
decreases to +125°C.
Output Overvoltage
Protection
VOUT > 5.9V
Switching stops until EN
pin is toggled or power is
cycled.
TABLE 1. INDUCTOR VENDOR INFORMATION
MANUFACTURER
PART NUMBER
DIMENSIONS - W x L x H (mm)
Murata
LQH32PN2R2NN0L
3.2 x 2.5 x 1.7 (maximum)
Toko
1239AS-H-2R2M
2.5 x 2.0 x 1.2 (maximum)
1286AS-H-2R2M
2.0 x 1.6 x 1.2 (maximum)
TDK
TFM201610A-2R2M
2.0 x 1.6 x 1.0 (maximum)
Cyntec
PSE25201B-2R2MS
2.0 x 1.6 x 1.2 (maximum)
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ISL9113A
Typical Characteristics
1.2
5.16
5.14
1.0
VOUT = 5.0V
0.8
VOUT = 4.0V
VOUT (V)
IOUT (A)
ILOAD = 1mA (PFM)
5.12
0.6
0.4
5.10
ILOAD = 100mA (PWM)
5.08
5.06
0.2
5.04
0
0.8
1.3
1.8
2.3
2.8
3.3
VBAT (V)
3.8
4.3
4.8
5.02
0
2
3
4
5
VBAT (V)
FIGURE 5. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
L = 2.2µH, COUT = 4.7μF
1
VBAT = 3.0V, VOUT = 5.0V, ILOAD = 20mA
FIGURE 6. LINE REGULATION, VOUT = 5V
L = 2.2µH, COUT = 4.7μF
VBAT = 3.0V, VOUT = 5.0V, ILOAD = 250mA
VOUT WITH 5.0V OFFSET (50mV/DIV)
VOUT WITH 5.0V OFFSET (200mV/DIV)
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (500mA/DIV)
SW (2V/DIV)
TIME 10µs/DIV
SW (2V/DIV)
FIGURE 7. PULSE SKIP MODE WAVEFORM
TIME 1µs/DIV
FIGURE 8. PWM WAVEFORM
VBAT = 3.0V, VOUT = 5.0V, ILOAD = 50mA
VBAT = 3.0V, VOUT = 5.0V, ILOAD = 250mA
EN
EN (5V/DIV)
VOUT (2V/DIV)
VOUT (2V/DIV)
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (500mA/DIV)
SW (5V/DIV)
SW (5V/DIV)
TIME 40ms/DIV
FIGURE 9. START-UP AFTER ENABLE (ILOAD = 250mA)
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TIME 40ms/DIV
FIGURE 10. START-UP AFTER ENABLE (ILOAD = 50mA)
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ISL9113A
Typical Characteristics (Continued)
VBAT = 3.6V, VOUT = 5.0V
VBAT = 3.6V, VOUT = 5.0V
VOUT (100mV/DIV)
VOUT (200mV/DIV)
TBD
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (500mA/DIV)
ILOAD AT 0.66Ω
(200mV/DIV)
ILOAD AT 0.66Ω
(200mV/DIV)
TIME 400µs/DIV
TIME 400µs/DIV
FIGURE 11. LOAD TRANSIENT RESPONSE (100mA TO 500mA)
FIGURE 12. LOAD TRANSIENT RESPONSE (20mA TO 250mA)
5.20
VOUT (V)
5.15
5.10
4.2V
3.0V
5.05
5.00
0
0.2
0.4
0.6
ILOAD (A)
3.6V
0.8
1.0
FIGURE 13. LOAD REGULATION
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ISL9113A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
January 4, 2017
FN8620.1
On page 1:
Figure 1, improved diagram to make it more readable.
Updated Related Literature section to new standard.
On page 10, updated POD from rev 0 to rev 1. Changes:
Tiebar Note 5 updated From: "Tiebar shown (if present) is a non-functional feature." To: "Tiebar shown (if
present) is a non-functional feature and may be located on any of the 4 sides (or ends)."
December 19, 2013
FN8620.0
Initial Release
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address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
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ISL9113A
Package Outline Drawing
For the most recent package outline drawing, see L8.2x2D.
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 1, 3/15
2.00
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
A
B
8
1
2.00
6x 0.50
(4X)
1.55±0.10
0.15
0.10M C A B 0.22
4
TOP VIEW
( 8x0.30 )
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08 C
SIDE VIEW
0 . 2 REF
C
DETAIL "X"
( 8x0.20 )
PACKAGE
OUTLINE
( 8x0.30 )
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
( 6x0.50 )
1.55
2.00
between 0.15mm and 0.30mm from the terminal tip.
( 8x0.22 )
0.90
2.00
TYPICAL RECOMMENDED LAND PATTERN
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10
5.
6.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8620.1
January 4, 2017