ADS5120 SBAS247B – MARCH 2002 – REVISED NOVEMBER 2002 8-Channel, 10-Bit, 40MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 8 DIFFERENTIAL ANALOG INPUTS The ADS5120 is a low-power, 8-channel, 10-bit, 40MSPS CMOS Analog-to-Digital Converter (ADC) that operates from a single 1.8V supply, while offering 1.8V and 3.3V digital I/O flexibility. A single-ended input clock is used for simultaneous sampling of up to eight analog differential input channels. The flexible duty cycle adjust circuit (DCASEL) allows the use of a non-50% clock duty cycle. Individual standby pins allow users the ability to power-down any number of ADCs. A sample-andhold stage is added in front of the ADC and a digital error correction circuit is used to generate the final digital code. ● 1Vp-p DIFFERENTIAL INPUT RANGE ● INT/EXT VOLTAGE REFERENCE ● ANALOG/DIGITAL SUPPLY 1.8V ● DIGITAL I/O SUPPLY 1.8V/3.3V ● INTEGRAL NONLINEARITY: ±0.8LSB ● SIGNAL-TO-NOISE: 58dB at fIN = 20MHz ● SPURIOUS-FREE DYNAMIC RANGE: 72dB at fIN = 20MHz The internal reference can be bypassed to use an external reference to suit the accuracy and temperature drift requirements of the application. A 10-bit parallel bus on eight channels is provided with 3-state outputs. ● 794mW POWER DISSIPATION ● INDIVIDUAL CHANNEL POWER-DOWN ● 257-LEAD, 0.8 BALL PITCH, PLASTIC MicroSTAR BGA™ (16 • 16mm) The speed, resolution, and low-power of the ADS5120 makes it ideal for applications requiring high-density signal processing in low-power environments. APPLICATIONS The ADS5120 is characterized for operation from 0°C to 70°C. ● PORTABLE ULTRASOUND ● PORTABLE INSTRUMENTATION MicroSTAR BGA is a trademark of Texas Instruments. AVDD STBY (x8) OE DRVDD DVDD CLK AINA+ T&H 10-Bit ADC 3-State Output Buffers D[9:0]A T&H 10-Bit ADC 3-State Output Buffers D[9:0]H AINA– AINH– AINH+ Internal Reference Circuit IREFR CM DCASEL AGND BG PDREF REFT REFB CML DRVGND DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage: AVDD to AGND, DVDD to DGND ............. –0.3V to +2.2V DRVDD to DGND ..................................... –0.3V to +4.0V AGND to DGND ...................................... –0.3V to +0.3V AVDD to DVDD .......................................... –2.2V to +2.2V Reference Voltage Input Range REFT, REFB to AGND ... –0.3V to AVDD + 0.3V Analog Input Voltage Range AIN to AGND ........... –0.3V to AVDD + 0.3V Clock Input CLK to DGND ..................................... –0.3V to AVDD + 0.3V Digital Input to DGND ........................................... –0.3V to DVDD + 0.3V Digital Outputs to DRGND .................................. –0.3V to DRVDD + 0.3V Operating Temperature Range (TJ) ................................... 0°C to +105°C Storage Temperature Range (TSTG) ................................. –65°C + 150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT ADS5120 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY MicroSTAR BGA-257 GHK 0°C to +70°C ADS5120CGHK ADS5120CGHK Tray, 90 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. BLOCK DIAGRAM AVDD STBY (x8) OE DRVDD DVDD CLK AINA+ T&H 10-Bit ADC 3-State Output Buffers D[9:0]A T&H 10-Bit ADC 3-State Output Buffers D[9:0]B T&H 10-Bit ADC 3-State Output Buffers D[9:0]C T&H 10-Bit ADC 3-State Output Buffers D[9:0]D T&H 10-Bit ADC 3-State Output Buffers D[9:0]E T&H 10-Bit ADC 3-State Output Buffers D[9:0]F T&H 10-Bit ADC 3-State Output Buffers D[9:0]G T&H 10-Bit ADC 3-State Output Buffers D[9:0]H AINA– AINB– AINB+ AINC+ AINC– AIND– AIND+ AINE+ AINE– AINF– AINF+ AING+ AING– AINH– AINH+ Internal Reference Circuit IREFR CM DCASEL AGND 2 BG PDREF REFT REFB CML DRVGND DGND ADS5120 www.ti.com SBAS247B DC CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, Clock = 40MSPS, 50% Clock Duty Cycle, –0.5dBFS Input Span, Internal Reference, and TMIN = 0°C, and TMAX = +70°C, unless otherwise noted. ADS5120 PARAMETER CONDITION MIN TYP RESOLUTION 10 DC ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) No Missing Codes Gain Error Offset Error Gain Temperature Coefficient Gain Matching External Reference External Reference REFB EXTERNAL REFERENCE GENERATION Reference, Top (REFT) Reference, Bottom (REFB) Input Resistance, REFRIN (between REFB and REFT) +1.0 +1.5 LSB LSB +1.0 +1.8 %FSR %FSR ppm/°C %FSR REFT V Vp-p V kΩ pF 1 (REFT + REFB)/ 2 83 5 fCLK = 40MSPS INTERNAL REFERENCE VOLTAGES Reference, Top (REFT) Reference, Bottom (REFB) Int Reference Temperature Coefficient PSRR, Power-Supply Rejection Ratio –1.0 UNITS Bits ±0.4 ±0.8 Tested 0.1 0.2 80 ±0.4 –0.9 –1.5 ANALOG INPUT Input Voltage Range (AIN+, AIN–) Input Voltage, Differential Full-Scale Input Common-Mode Range Input Resistance, RIN Input Capacitance, CIN POWER SUPPLY Operating Supply Current, IDD Analog Operating Supply Current, IAVDD Digital Operating Supply Current, IDVDD Driver Operating Supply Current, IDRVDD Operating Voltage AVDD DVDD DRVDD Power-Dissipation Standby Power (STBY) MAX 1.30 0.76 1.34 0.81 50 1.40 0.85 V V ppm/°C 1.15 0.65 1.25 0.75 80 1.35 0.85 V V Ω 398 294 44 53 450 340 49 60 mA mA mA mA 1.8 1.8 1.8 794 68 60 10 2.5 0.8 2.0 2.0 3.6 850 V V V mW mW mW mW mW mV/V fIN = 3.5MHz CL = 20pF 1.65 1.65 1.65 CLK Running CLK Stopped PDREF = 1, External REF, CLK Running PDREF = 1, External REF, CLK Stopped ±5% 15 5 DC CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, Clock = 40MSPS, 50% Clock Duty Cycle, –0.5dBFS Input Span, Internal Reference, and TMIN to TMAX, unless otherwise noted. ADS5120 PARAMETER DIGITAL INPUTS (STBY A-H, PDREF, OE) High-Level Input Voltage, VIH Low-Level Input Voltage, VIL High-Level Input Current, IIH Low-Level Input Current, IIL DIGITAL INPUTS (DCASEL) High-Level Input Voltage, VIH Low-Level Input Voltage, VIL High-Level Input Current, IIH Low-Level Input Current, IIL DIGITAL OUTPUTS ( DRVDD = 3.3/1.8V) High-Level Output Voltage, VOH Low-Level Output Voltage, VOL External Load Capacitance, CL 3-State Leakage Current, ILEAK CONDITION MIN DRVDD = 3.3V/1.8V VIH = DRVDD VIL = 0V 0.70 • DRVDD VIH = DVDD VIL = 0V 0.70 • DVDD IOH = –50µA IOL = 50µA 0.8 • DRVDD MAX UNITS 0.25 • DRVDD ±1 ±1 V V µA µA 0.25 • DVDD ±1 ±1 V V µA µA 0.2 • DRVDD 15 OE = HIGH ADS5120 SBAS247B TYP www.ti.com ±1 V V pF µA 3 TARGETED AC CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at –0.5dBFS Input Span, Internal voltage reference, TMIN = 0°C, TMAX = 70°C, and typical values are at TA = 25°C, unless otherwise noted. ADS5120 PARAMETER CONDITION Signal-to-Noise Ratio (SNR) MIN (SINAD) (ENOB) Spurious-Free Dynamic Range (SFDR) 55 58 dB 55 58 dB 58 dB fIN = 3.5MHz 55 57 dB fIN = 10MHz 55 57 dB 57 dB fIN = 3.5MHz 8.8 9.2 Bits Bits fIN = 10MHz 8.8 9.2 fIN = 20MHz 8.8 9.2 Bits fIN = 3.5MHz 65 73 dBc fIN = 10MHz 65 72 dBc 72 dBc fIN = 20MHz 2nd-Harmonic Distortion (HD2) fIN = 3.5MHz 68 79 dBc fIN = 10MHz 68 80 dBc 80 dBc fIN = 20MHz 3rd-Harmonic Distortion (HD3) 2-Tone Intermod. Distortion (IMD) UNITS fIN = 10MHz fIN = 20MHz Effective Number of Bits MAX fIN = 3.5MHz fIN = 20MHz Signal-to-Noise and Distortion TYP fIN = 3.5MHz 65 76 dBc fIN = 10MHz 65 78 dBc fIN = 20MHz 73 dBc f1 = 4.43MHz, f2 = 4.53MHz at –6.5dB –69 dBFS Channel-to-Channel Crosstalk fIN = 10MHz, DRVDD = 3.3V 89 dB 300 MHz Over-Voltage Recovery Time(1) 20 ns Differential Gain(1) ±1 % ±0.25 Degree Large-Signal Bandwidth (FPBW) Differential Phase(1) NOTE: (1) Assured by design. SWITCHING CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at –0.5dBFS Input Span, Internal voltage reference, TMIN = 0°C, TMAX = 70°C, and Typical values are at TA = 25°C, unless otherwise noted. ADS5120 PARAMETER CONDITION Maximum Conversion Rate Clock Duty Cycle Data Latency(1) Clock ↓ to Data Valid OE ↓ to Outputs Enabled OE ↑ Rising to Outputs Tri-Stated Aperture Delay Aperture Uncertainty (Jitter) MIN TYP 1 DCASEL Enabled 30 to 70 7 8 8 8 1 2 tDO(1) tEN(1) tDIS MAX UNITS 40 MSPS % Clk Cycles ns ns ns ns ps, r ms 10 NOTE: (1) See Timing Diagram. TIMING DIAGRAM (Per ADC Channel) Sample 2 Sample 1 Analog Input CLK 1 2 3 4 5 6 7 8 9 10 OE tEN D[9:0] 4 tDIS tDO S–7 S–6 S–5 S–4 S–3 S–2 S–1 S1 S2 ADS5120 www.ti.com SBAS247B PIN CONFIGURATION 14,40 TYP Bottom View BGA 0,80 0,80 W V U T R P N M L K J H G F E D C B A 3 1 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 PIN DESCRIPTIONS NAME PINS I/O AVDD AGND I I Analog Supply, (1.8V) Analog Ground AINA+ AINA– AINB+ AINB– AINC+ AINC– AIND+ AIND– AINE+ AINE– AINF+ AINF– AING+ AING– AINH+ AINH– CLK REFT REFB CML BG C6, C7, E6, F1, F2, F3, F5, F6, J6, N3, P3, P5, P6, P7, R6, V6, W6 A3, A5, B5, B9, C1, C5, C9, E3, E7, F7, G1, G5, G6, H6, J1, J2, M2, N5, N6, P8, R1, R2, R3, R7, U1, U5, U10, V5, V10, W3, W7 U7 V7 W4 V4 T1 T2 P2 P1 G3 G2 D1 D2 A4 B4 B6 A6 W9 K3, L1, J3 K5, J5, L5 L2, L3 K1 I I I I I I I I I I I I I I I I I/O I/O O I/O IREFR K6 I DNC DNC NC DCASEL DVDD I I I I I I Digital Ground PDREF W5 U6 E1, E2, E5, K2, L6, M1 N2 C2, C3, C4, D3, E8, F8, H3, H5, M3, M5, R8, T3, U3, U4, U8, V3, P13, R13 P17, L15, J14, F17, F12, E12 A2, A7, B1, B2, B3, B7, B13, C13, G15, H1, H2, H17, L17, M6, N1, N15, U2, U13, U14, V1, V2, V8, W2, W8 V9 Analog Input Channel A Complementary Analog Input Channel A Analog Input Channel B Complementary Analog Input Channel B Analog Input Channel C Complementary Analog Input Channel C Analog Input Channel D Complementary Analog Input Channel D Analog Input Channel E Complementary Analog Input Channel E Analog Input Channel F Complementary Analog Input Channel F Analog Input Channel G Complementary Analog Input Channel G Analog Input Channel H Complementary Analog Input Channel H Clock Input Reference Top Reference Bottom Common-Mode Level Output Bandgap Decoupling (Decouple with 1µF cap to AGND and 100kΩ to AVDD) Internal Reference Bias Current (Connect 6.19kΩ resistor from this pin AGND to set internal bias amplifier current.) Do Not Connect Do Not Connect No Internal Connection Duty Cycle Adjust Digital Supply (1.8V) I STBY A STBY B STBY C STBY D STBY E STBY F STBY G STBY H OE W10 P9 R9 U9 C8 B8 A8 A9 P10 I I I I I I I I I DRVDD B17, C16, D17, E9, E10, E11, E17, F9, H14, H15, K17, L14, N14, P12, P14, P15 R10, R12, R14 E13, F10, F11, F13, F14, F15, G14, G17, M14, M15, M17, N17, U11, U12, U15, U16 I I I Power-Down Ref: 0 = internal reference, 1 = external reference. In external reference mode connect REFT to BG pin. Power-Down Channel A Power-Down Channel B Power-Down Channel C Power-Down Channel D Power-Down Channel E Power-Down Channel F Power-Down Channel G Power-Down Channel H Enable all Digital Outputs, Ch A-H. OE: 0 = Outputs Enable. OE: 1 = Outputs disabled (3-State). Driver Digital Supply (1.8V or 3.3V) DGND DRGND ADS5120 SBAS247B www.ti.com TERMINAL DESCRIPTION Driver Digital Ground 5 DATA OUTPUT PINS NAME PINS I/O TERMINAL DESCRIPTION D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D0C D1C D2C D3C D4C D5C D6C D7C D8C D9C D0D D1D D2D D3D D4D D5D D6D D7D D8D D9D V14 W14 V13 W13 V12 W12 R11 P11 V11 W11 V19 V18 U17 W18 V17 W17 V16 W16 V15 W15 P19 P18 R19 R18 R17 T19 T18 U19 U18 T17 K14 K15 K18 K19 L18 L19 M19 M18 N19 N18 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Bit 1, Channel A (LSB) Bit 2, Channel A Bit 3, Channel A Bit 4, Channel A Bit 5, Channel A Bit 6, Channel A Bit 7, Channel A Bit 8, Channel A Bit 9, Channel A Bit 10, Channel A (MSB) Bit 1, Channel B (LSB) Bit 2, Channel B Bit 3, Channel B Bit 4, Channel B Bit 5, Channel B Bit 6, Channel B Bit 7, Channel B Bit 8, Channel B Bit 9, Channel B Bit 10, Channel B (MSB) Bit 1, Channel C (LSB) Bit 2, Channel C Bit 3, Channel C Bit 4, Channel C Bit 5, Channel C Bit 6, Channel C Bit 7, Channel C Bit 8, Channel C Bit 9, Channel C Bit 10, Channel C (MSB) Bit 1, Channel D (LSB) Bit 2, Channel D Bit 3, Channel D Bit 4, Channel D Bit 5, Channel D Bit 6, Channel D Bit 7, Channel D Bit 8, Channel D Bit 9, Channel D Bit 10, Channel D (MSB) 6 NAME D0E D1E D2E D3E D4E D5E D6E D7E D8E D9E D0F D1F D2F D3F D4F D5F D6F D7F D8F D9F D0G D1G D2G D3G D4G D5G D6G D7G D8G D9G D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H PINS F18 F19 G18 G19 H18 H19 J15 J17 J18 J19 A18 B18 C17 B19 C18 C19 D18 D19 E18 E19 A14 B14 C14 A15 B15 E14 C15 A16 B16 A17 C10 B10 A10 C11 B11 A11 A12 B12 C12 A13 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O TERMINAL DESCRIPTION Bit 1, Channel E (LSB) Bit 2, Channel E Bit 3, Channel E Bit 4, Channel E Bit 5, Channel E Bit 6, Channel E Bit 7, Channel E Bit 8, Channel E Bit 9, Channel E Bit 10, Channel E (MSB) Bit 1, Channel F (LSB) Bit 2, Channel F Bit 3, Channel F Bit 4, Channel F Bit 5, Channel F Bit 6, Channel F Bit 7, Channel F Bit 8, Channel F Bit 9, Channel F Bit 10, Channel F (MSB) Bit 1, Channel G (LSB) Bit 2, Channel G Bit 3, Channel G Bit 4, Channel G Bit 5, Channel G Bit 6, Channel G Bit 7, Channel G Bit 8, Channel G Bit 9, Channel G Bit 10, Channel G (MSB) Bit 1, Channel H (LSB) Bit 2, Channel H Bit 3, Channel H Bit 4, Channel H Bit 5, Channel H Bit 6, Channel H Bit 7, Channel H Bit 8, Channel H Bit 9, Channel H Bit 10, Channel H (MSB) ADS5120 www.ti.com SBAS247B TYPICAL CHARACTERISTICS TA = 25°C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, Clock = 40MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 9.8MHz –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 3.5MHz –20 –60 –80 –100 –60 –80 –100 –120 –120 0 5 10 15 20 0 5 Frequency (MHz) 15 20 DIFFERENTIAL NONLINEARITY SPECTRAL PERFORMANCE 1 0 fIN = 19.5MHz 0.8 –20 0.6 0.4 –40 DNL (LSB) Amplitude (dB) 10 Frequency (MHz) –60 –80 0.2 0 –0.2 –0.4 –0.6 –100 –0.8 –1 –120 0 5 10 15 0 20 256 768 1024 2ND- AND 3RD-HARMONIC vs INPUT FREQUENCY INTEGRAL NONLINEARITY 88 0.8 86 2nd- and 3rd-Harmonic (dBc) 1 0.6 0.4 INL (LSB) 512 Input Codes Frequency (MHz) 0.2 0 –0.2 –0.4 –0.6 –0.8 3rd 84 82 80 78 2nd 76 74 72 –1 0 256 512 768 1024 Input Codes ADS5120 SBAS247B www.ti.com 0 5 10 15 Input Frequency (MHz) 20 7 TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, Clock = 40MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted. SNR AND SFDR vs CLOCK FREQUENCY SNR AND SFDR vs CLOCK FREQUENCY 85 85 fIN = 3.5MHz fIN = 10MHz 80 SFDR SNR (dB), SFDR (dBc) SNR (dB), SFDR (dBc) 80 75 70 65 SNR 60 55 SFDR 75 70 65 SNR 60 55 50 50 5 10 15 20 25 30 35 40 45 5 10 15 Clock Frequency (MHz) 20 25 30 35 40 45 Clock Frequency (MHz) SINAD vs DUTY CYCLE (DCASEL = ENABLE) SNR vs INPUT FREQUENCY 60 60 fIN = 3.5MHz 59 59 58 56 SNR (dB) SINAD (dB) 57 55 54 58 57 53 56 52 51 55 50 20 30 40 50 0 70 60 4 8 12 20 16 Input Frequency (MHz) Clock Duty Cycle (%) IAVDD vs CLOCK FREQUENCY SWEPT INPUT POWER (SNR) 305 70 60 dBFS IAVDD (mA) SNR (dBFS, dBc) 300 50 40 dBc 30 295 290 20 285 10 0 280 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 0 8 5 10 15 20 25 30 35 40 Clock Frequency (MSPS) Input Amplitude (dBFS) ADS5120 www.ti.com SBAS247B TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, AVDD = DVDD = 1.8V, DRVDD = 3.3V, fIN = –0.5dBFS, Internal Reference, Clock = 40MSPS, and Differential Input Range = 1Vp-p, unless otherwise noted. IDVDD vs CLOCK FREQUENCY IDRVDD vs CLOCK FREQUENCY 50 60 45 50 40 IDRVDD (mA) IDVDD (mA) 35 30 25 20 15 10 40 30 20 10 5 0 0 0 5 10 15 20 25 30 35 40 0 5 10 Clock Frequency (MSPS) TOTAL POWER vs CLOCK FREQUENCY 20 25 30 35 40 60 70 POWER vs TEMPERATURE 850 805 800 800 Power (mW) 750 Power (mW) 15 Clock Frequency (MSPS) 700 650 600 795 790 785 780 550 500 775 0 5 10 15 20 25 30 35 40 0 10 20 25 Clock Frequency of CLK (MSPS) 30 40 50 Temperature (°C) GAIN ERROR vs TEMPERATURE 0.6 Ch-A Gain Error (% Full-Scale) 0.5 0.4 Ch-H Ch-C 0.3 0.2 Ch-G Ch-E 0.1 0 Ch-B Ch-D Ch-F –0.1 –0.2 0 10 20 25 30 40 50 60 70 Temperature (°C) ADS5120 SBAS247B www.ti.com 9 APPLICATION INFORMATION INPUT IMPEDANCE CONVERTER OPERATION The ADS5120 is an 8-channel, simultaneous sampling ADC. Its low power (100mW/channel) and high sampling rate of 40MSPS is achieved using a state-of-the-art switched capacitor pipeline architecture built on an advanced low-voltage CMOS process. The ADS5120 primarily operates from a +1.8V single supply. For additional interfacing flexibility, the digital I/O supply (DRVDD) can be set to either +1.8V or +3.3V. The ADC core of each channel consists of 10 pipeline stages. Each of the 10 stages produces one digital bit per stage. Both the rising and the falling clock edges are utilized to propagate the sample through the pipeline every half clock, for a total of five clock cycles. Two additional clock cycles are needed to pass the sample data through the digital error correction logic and the output latches. The total pipeline delay, or data latency, is therefore seven clock cycles long. Since a common clock controls the timing of all eight channels, the analog signal is sampled at the same time, as well as the data on the parallel ports which becomes updated simultaneously. ANALOG INPUTS The analog input for each channel of the ADS5120 consists of a differential track-and-hold amplifier implemented using a switched capacitor technique, shown in Figure 1. This differential input topology along with closely matched capacitors produces a high level of AC performance up to high sampling rates. Differential versus Single-Ended VBIAS S2 CIN AIN+ T&H AIN– S4 VBIAS S6 Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open. Hold Phase: The ADS5120 operates from a single +1.8V analog supply, and requires each of the analog inputs (AIN+, AIN–) to be externally biased by a suitable common-mode voltage. For example, with a common-mode voltage of +1V, the 1Vp-p full-scale, differential input signal will swing symmetrically around +1V, or between 0.75V and 1.25V. This is determined by the two reference voltages, the top reference (REFT), and the bottom reference (REFB). Typically, the input commonmode level is related to the reference voltages and defined as (REFT + REFB)/2. This reference mid-point is provided at the CML pin and can directly be used for input biasing purposes. The voltage at CML will assume the mid-point for either internal or external reference operation. In any case, it is recommended to bypass the CML pin with a ceramic 0.1µF capacitor. DRIVING THE ANALOG INPUTS S3 CIN INPUT BIASING ADS5120 S5 S1 Because of the switched capacitor input track-and-hold amplifier, the input impedance of the ADS5120 is effectively capacitive, and the driving source needs to provide sufficient slew current to charge and discharge the input sampling capacitor while the track-and-hold amplifier is in track mode. The input impedance of the ADS5120 is also a function of the sampling rate. As the sampling frequency increases, the input impedance decreases linearly at a rate of 1/fs. For most applications, this does not represent a limitation since the impedance remains relatively high, for example, approximately 83kΩ at the max sampling rate of 40MSPS. For applications using an op amp to drive the ADC, it is recommended that a series resistor, typically 10Ω to 50Ω, be added between the amplifier’s output and the converter inputs. This will isolate the converter’s capacitive input from the driver and avoid potential gain peaking, or instability. S1, S2, S3, S4 open; S5, S6 closed. The analog input of the ADS5120 allows it to be driven either single-ended or differentially. Differential operation of the ADS5120 requires an input signal that consists of an inphase and a 180° out-of-phase part simultaneously applied to the inputs (AIN+, AIN–). The differential operation offers a number of advantages, which in most applications will be instrumental in achieving the best dynamic performance of the ADS5120: • The signal swing is half of that required for the singleended operation and is therefore less demanding to achieve while maintaining good linearity performance from the signal source. • The reduced signal swing allows for more headroom of the interface circuitry and therefore a wider selection of the best suitable driver op amp. FIGURE 1. Simplified Circuit of Input Track-and-Hold. • Even-order harmonics are minimized. • Improves the noise immunity based on the converter’s common-mode input rejection. 10 ADS5120 www.ti.com SBAS247B For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance. Applying the signal to the complementary input (AIN–) instead of the AIN+ input, however, will invert the orientation of the input signal relative to the output code. This could be helpful, for example, if the input driver operates in inverting mode using input AIN– as the signal input will restore the phase of the signal to its original orientation. INPUT DRIVER CONFIGURATIONS Transformer-Coupled Interface If the application requires a signal conversion from a singleended source to drive the ADS5120 differentially, a RFtransformer might be a good solution. The selected transformer must have a center tap in order to apply the commonmode DC voltage necessary to bias the converter inputs. ACgrounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode, both inputs (AIN+ and AIN–) of the ADS5120 see matched impedances. Figure 2 shows the schematic for the suggested transformercoupled interface circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. Single-Ended, AC-Coupled Driver The circuit of Figure 3 shows an example for driving the inputs of the ADS5120 in a single-ended configuration. The signal is AC-coupled between the driver amplifier and the converter input (AIN+). This allows for setting the required common-mode voltages for the ADC and op amp separately. The single-supply op amp is biased at mid-supply by two resistors connected at its noninverting input. Connecting each input to the CML pin provides the required commonmode voltage for the inputs of the ADS5120. Here, two resistors of equal value ensure that the inputs see closely matched source impedances. If the op amp features a disable function, it could be easily tied together with the power-down pin of the ADS5120 channel (STBY). In the circuit example depicted in Figure 3, the OPA355’s EN pin is +5V –5V RS VIN 0.1µF OPA690 RIN 1:n AIN+ RT R1 CIN RIN ADS5120 AIN– CML R2 0.1µF FIGURE 2. Converting a Single-Ended Input Signal into a Differential Signal Using a RF-Transformer. +3V/+5V R1 0.1µF VIN EN RS 24Ω STBY 0.1µF AIN+ OPA355 R2 18pF ADS5120 RF 604Ω 1.82kΩ AIN– 1.82kΩ RG 604Ω CML 0.1µF 0.1µF FIGURE 3. Single-Ended, AC-Coupled Driver Configuration for Single Supply. ADS5120 SBAS247B www.ti.com 11 IREFR pin to analog ground, AGND (as shown in Figure 5). While a 1% resistor tolerance is adequate, deviating from this resistor value will cause altered and degraded performance. directly connected to the STBY pin to allow for a power-down mode of the entire circuit. Other, suitable op amps for singlesupply driver applications include the OPA634, OPA635, or OPA690, for example. To ensure proper operation with any reference configuration, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum. Figure 5 shows the recommended decoupling scheme. Good performance can be obtained using 0.1µF low inductance ceramic capacitors. Adding tantalum capacitors (1µF to 10µF) may lead to a performance improvement, depending on the application. All bypassing capacitors should be located as close to their respective pins as possible. DC-Coupled Interface with Differential Amplifier Differential input/output amplifiers can simplify the driver circuit for applications requiring input DC-coupling. Flexible in their configurations, such amplifiers can be used for singleended to differential conversion, allow for signal amplification, and also filtering prior to the ADC. Figure 4 shows one possible circuit implementation using the THS4130 amplifier. Here, the amplifier operates with a gain of +1. The commonmode voltage available at the CML pin can be conveniently connected to the amplifier’s VOCM pin to set the required input bias for the ADS5120. INTERNAL REFERENCE The internal reference circuit of the ADS5120 consists of a bandgap voltage reference, the drivers for the top and bottom reference, and the resistive reference ladder. The corresponding reference pins are REFT, REFB, CML, IREFR, BG, and PDREF. In order to enable the internal reference, REFERENCE OPERATION For proper operation of the ADS5120 and its reference, an external 6.19kΩ resistor must be connected from the 390Ω ADS5120 390Ω 20Ω VIN+ AIN+ VOCM THS4130 20Ω 18pF 390Ω AIN– 390Ω CML 0.1µF 2.2µF FIGURE 4. DC-Coupled Interface Using Differential I/O Amplifier THS4130. +1.8V PDREF AVDD 100kΩ ADS5120 BG REFT 1µF 0.1µF CML + 2.2µF REFB 0.1µF 0.1µF IREFR + 6.19kΩ 2.2µF FIGURE 5. Internal Reference; Recommended Configuration and Bypassing. 12 ADS5120 www.ti.com SBAS247B obtaining better matching of the full-scale range between converters. pin PDREF must be at a logic LOW = 0 level. In addition, the bandgap pin BG must have a 100kΩ pull-up resistor to AVDD, and should be decoupled with a 1µF capacitor. The reference circuit provides the reference voltages to each of the eight channels. Setting the ADS5120 for external reference mode requires taking the PDREF pin HIGH. In addition, pins BG and REFT must be connected together (as shown in Figure 6). The common-mode voltage at the CML pin will be maintained at approximately the mid-point of the applied reference voltages, according to CML ≈ (VREFT – VREFB)/2. The internal buffer amplifiers for REFT and REFB are disabled when the ADS5120 operates in the external reference mode. The external reference circuit must be designed to drive the internal reference ladder (80Ω) located between the REFT and REFB pins. For example, setting REFT = +1.25V and REFB = +0.75V will require a current drive capability of at least 0.5V/ 80Ω = 6.25mA. The external references can vary as long as the value of the external top reference (REFTEXT) stays within the range of +1.15V to +1.35V, and the external bottom reference (REFBEXT) stays within +0.65V to +0.85V (as shown in Figure 7). The reference buffers can be utilized to supply up to 1mA (sink and source) to an external circuitry. The common-mode level output pin, CML, represents the mid-point of the internal resistor ladder and is an unbuffered node. Loading of this pin should be avoided, as it will lead to degradation of the converter’s linearity. USING EXTERNAL REFERENCES For even more design flexibility, the internal reference can be disabled and an external reference voltage used. The utilization of an external reference may be considered for applications, requiring higher accuracy or improved temperature performance. Especially in multi-channel applications, the use of a common external reference has the benefit of +1.8V PDREF AVDD ADS5120 BG REFT CML + 0.1µF 2.2µF REFB 0.1µF + 0.1µF REFTEXT IREFR 6.19kΩ 2.2µF REFBEXT FIGURE 6. External Reference; Recommended Configuration and Bypassing. +5V +5V 1/2 OPA2234 4.7kΩ REFT + R3 + 0.1µF ADS5120 R4 R1 REF1004 +2.5V 2.2µF 10µF 1/2 OPA2234 R2 REFB + 0.1µF 2.2µF 0.1µF FIGURE 7. Circuit Example of an External Reference Circuit Using Single-Supply, Low-Power, Dual Op Amp (OPA2234). ADS5120 SBAS247B www.ti.com 13 DIGITAL INPUTS AND OUTPUTS Clock Input DIFFERENTIAL INPUT The clock input is designed to operate with +1.8V or +3.3V CMOS logic levels. The clock circuitry is internally connected to the DRVDD supply. Therefore, the input HIGH and LOW levels will vary depending on the applied DRVDD supply, see ‘Digital Characteristics’. Since both edges of the clock are used in this pipeline ADC, the ideal clock should be a squarewave logic signal with a 50% duty-cycle. Since this condition cannot always easily be met, the ADS5120 features an internal clock conditioning circuitry that can be activated through the duty-cycle adjust pin (DCASEL). The DCASEL pin is a logic input, with its logic levels related to the DVDD supply (+1.8V only): a) DCASEL = LOW (GND); in this mode the clock conditioning circuitry is disabled. Use this setting if the applied clock signal is a square-wave clock with a duty cycle of 50%; or if the duty cycle stays within a range of 48% to 52%. b) DCASEL = HIGH (DVDD); in this mode the clock conditioning circuitry is enabled. Use this setting if the applied external clock signal is a square-wave clock that does not meet the criteria listed above, but has a duty cycle in the range of 30% to 70%. MINIMUM SAMPLING RATE The pipeline architecture of the ADS5120 uses a switched capacitor technique for the internal track-and-hold stages. With each clock cycle, charges representing the captured signal level are moved within the ADC pipeline core. The high sampling rate necessitates the use of very small capacitor values. In order to hold the droop errors low, the capacitors require a minimum ‘refresh rate’. To maintain full accuracy of the acquired sample charge, the sampling clock of the ADS5120 should not be lower than the specified minimum of 1MSPS. DATA OUTPUT FORMAT The output data format of the ADS5120 is a positive Straight Offset Binary (SOB) code. Tables I and II show output coding of a single-ended and differential signal. For all data output channels, the MSBs are located at the D9x pins. SINGLE-ENDED INPUT (AIN– = CML) STRAIGHT OFFSET BINARY (SOB) +FS – 1LSB (AIN+ = CML + FSR/2) 11 1111 1111 +1/2 FS 11 0000 0000 Bipolar Zero (AIN+ = CML) 10 0000 0000 –1/2 FS 01 0000 0000 –FS (AIN+ = CML – FSR/2) 00 0000 0000 +FS – 1LSB (AIN+ = REFT, AIN– = REFB) 11 1111 1111 +1/2 FS 11 0000 0000 Bipolar Zero (AIN+ = AIN– = CML) 10 0000 0000 –1/2 FS 01 0000 0000 –FS (AIN+ = REFB, AIN– = REFT) 00 0000 0000 TABLE II. Coding Table for Differential Input Configuration and 1Vp-p Full-Scale Range. DIGITAL OUTPUT LOADING Minimizing the capacitive loading on the digital outputs is very important in achieving the best performance. The total load capacitance is typically made up of two sources: the next stage input capacitance and the parasitic/pc-board capacitance. It is recommended to keep the total capacitive loading on the data lines as low as possible (≤ 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing states. High current surges may cause feedback into the analog portion of the ADS5120 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. A suggested device is the SN74AVC16827 (20-bit buffer/driver), a member of the ‘Advanced Very Low Voltage CMOS’ logic family (AVC). Using such a logic device can also provide the added benefit of isolating the ADS5120 from any digital noise activities on the bus coupling back high-frequency noise. Some applications may also benefit from the use of series resistors (≤ 100Ω) in the data lines. This will provide a current limit and reduce any existing over- or undershoot. OUTPUT ENABLE The ADS5120 provides one output enable pin (OE) that controls the digital outputs of all channels simultaneously. A LOW (L = 0) level on the OE pin will have all channels active and the converter in normal operation. Taking the OE pin HIGH (H = 1) will disable or tri-state the outputs of all channels. Note that the OE pin has no internal pull-up resistor and therefore requires a defined potential to be applied. The timing relations between OE and the output bus enable/disable times are shown in the Timing Diagram. POWER-DOWN (STANDBY) TABLE I. Coding Table for Single-Ended Input Configuration with Input AIN– Tied to the Common-Mode Voltage (CML). 14 STRAIGHT OFFSET BINARY (SOB) The ADS5120 is equipped with a power-down function for each of the eight channels. Labeled as STBY pins, the normal operational mode is when this pin is connected to logic high (H = 1). The selected ADC channel will be in a power-down mode if the corresponding STBY pin is connected to logic LOW (L = 0). The logic levels for the STBY pins are dependent on the DRVDD supply. The power-down function controls internal biasing nodes, and as a consequence, any data present in the pipeline of the converter will become invalid. This is independent of whether the clock remains applied during power-down, or not. Following a ADS5120 www.ti.com SBAS247B power-up, new, valid data will become available after a minimum of seven clock cycles. As a note, the operation of the STBY pins is not intended for the use of dynamically multiplexing between the eight channels of the ADS5120. DIGITAL OUTPUT DRIVER SUPPLY, DRVDD The ADS5120 uses a dedicated supply connection for the output logic drivers, DRVDD, along with its digital driver ground connections, labeled DRGND. Setting the voltage at DRVDD to either +3.3V or +1.8V the output logic levels are set accordingly, allowing the ADS5120 to directly interface to a selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS5120 with a +1.8V driver supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply lines, which otherwise may affect the AC performance of the converter. In some applications it might be advantageous to decouple the DRVDD supply with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Multilayer pc-boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS5120 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. The ground pins should directly connect to an analog ground plane covering the pc-board area under the converter. While designing the layout it is important to keep the analog signal traces separated from any digital line to prevent noise coupling onto the analog signal path. Due to its high sampling rate, the ADS5120 generates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. In most cases 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore they should be located as close to the supply pins as possible. In addition, a larger bipolar capacitor (1µF to 22µF) should be placed on the pc-board in proximity of the converter circuit. LAYOUT OF THE PCB WITH A MICROSTAR BGA PACKAGE The ADS5120 is housed in a polymide film-based chipscale package (CSP). Like most CSPs, solder alloy balls are used as the interconnect between the package substrate and the board on which the package is soldered. For detailed information regarding these packages, please refer to literature number SSYZ015B, MicroStar BGA Packaging Reference Guide, which addresses the specific considerations required when integrating a MicroStar BGA package into the PCB design. This document can be found at: http://www-s.ti.com/sc/psheets/ssyz015b/ssyz015b.pdf ADS5120 SBAS247B www.ti.com 15 TERMINOLOGY INTERMODULATION DISTORTION (IMD) ANALOG BANDWIDTH The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3dB. The 2-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) Intermodulation products. The individual input tone levels are at –6.5dB fullscale, and their envelope is at –0.5dB full-scale. OFFSET ERROR (ZERO-SCALE ERROR) APERTURE DELAY The delay between the 50% point of the rising edge of the Clock and the instant at which the analog input is sampled. APERTURE UNCERTAINTY (JITTER) The first transition should occur for an analog value 1/2 LSB above negative full-scale. Offset error is defined as the deviation of the actual transition from that point. OFFSET MATCHING The sample-to-sample variation in aperture delay. The change in offset error between adjacent channels. EFFECTIVE NUMBER OF BITS (ENOB) POWER-SUPPLY REJECTION RATIO (PSRR) The ENOB is calculated from the measured SINAD based on the equation: SINAD – 1.76dB ENOB = 6.02 The ratio of a change in input offset voltage to a change in power-supply voltage. SIGNAL-TO-NOISE AND DISTORTION (SINAD) GAIN ERROR Gain Error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. The ratio of the rms signal amplitude (set 0.5dB below fullscale) to the rms value of the sum all other spectral components, including harmonics but excluding DC. SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS) The ratio of the rms signal amplitude (set 0.5dB below fullscale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC. GAIN MATCHING Variation in Gain Error between adjacent channels. HARMONIC DISTORTION, SECOND SPURIOUS-FREE DYNAMIC RANGE (SFDR) The ratio of the rms signal amplitude to the rms value of the 2nd-harmonic component, reported in dBc. HARMONIC DISTORTION, THIRD The ratio of the rms signal amplitude to the rms value of the 3rd-harmonic component, reported in dBc. 16 The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full-scale). ADS5120 www.ti.com SBAS247B PACKAGE DRAWING GHK (S-PBGA-N257) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 0,80 W V U T R P N M L K J H G F E D C B A 1 3 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4145273-3/C 12/99 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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