Digital pulse compression module CI E03 To make an enquiry please email: [email protected] Product Description CI E03 is a digital dual pulse compression module, well suited for RADARS performance enhancement. Analog inputs and outputs make it an ideal replacement for SAW based pulse compression subsystems. Each of the two available channels may be configured as chirp expander or chirp compressor. All the pulse compression parameters are programmable (center frequency, bandwidth, time dispersion, modulation law, weighting function, etc.). CI E03 is provided with FPGA firmware, which will be configured by Rakon, based on customer requirements. Features Digital pulse compression module 2 concurrent channels : Expander or compressor for each channel 2 x IF analog inputs, 2 x IF analog outputs High precision clock, self sufficient or externally locked BITE function Low profile High BxT compression gain Fig. 1 : Maximum B x T compression parameters Applications SAW based pulse compression RADARS upgrade March 15th, 2013 CI E03 Revision A3 1 / 11 www.rakon.com Digital pulse compression module CI E03 Technical description CI E03 functional bloc diagram is featured on Fig. 2. DA C 250 MS PS 16 bits RF OUT B (J5) DA C 250 MS PS 16 bits RF OUT A (J4) (J1) FPGA config (SPI ) JTA G VA NA (x2) US ER (x15) FPGA XC5VSX35T RE FCLK (J6) PLL / VCO CPLD Superv ision BIT E IF Os c RF INA (J2) RF INB (J3) US ER (x4) BO ARD_OK Sta tus (x3) N_ RST ADC 250 MS PS 12 bits ADC 250 MS PS 12 bits CLKEXT _EN Power Control VCFG N_ BOA RD_PD VINMA IN VINVCO Fig. 2 : CI E03 functional bloc diagram This module is specifically designed to upgrade existing SAW based pulse compression subsystems. Plugged on a specific carrier board, this module may upgrade many existing expanders and/or compressors. With a low size and low profile, it may be embedded in small form factors. This module is able to process on-the-fly 2 independent and concurrent channels. Each channel may be an expander or a compressor. The two independent channels are processed in a single FPGA, but each of them uses dedicated resources. The internal clock generator is self-sufficient but may also be locked on an external clock. An external clock is required for expander channels, but is optional for compressor channels. As the two channels uses the same ADC, same DAC component types and the same reference clock, the phase difference will be close to 0, and will be very stable inside the operating range. There is no need to use phase shifters to adjust phase difference. 16 different waveforms, each of them with different specification, may be stored for each expander channel. The active waveform is selected with 4 user inputs on J1 connector. Expander channel waveforms allows for Doppler pre-correction, e.g. there may be 2 waveforms with different specifications, each of them with 8 different Doppler pre-corrections ranging from negative values to positive values. FPGA firmware resides inside a flash PROM located on the carrier board, thus CI E03 has not to be application dependant; the same CI E03 board may be used without any modification or firmware upgrade for different applications. Firmware is automatically loaded in the FPGA at startup. CI E03 module continuously monitors its internal temperature, powers off FPGA and some other components and deasserts TEMP_OK signal on J1 connector if temperature exceeds a secure maximum threshold. CI E03 module is provided with FPGA firmware to be loaded on the carrier flash memory. Functions, and channels specifications (time dispersion, compressed pulse width, side lobes level,…) should be provided by customer; Rakon will customize the FPGA program to fulfill customer requirements. Expander channel bloc diagram is featured in Fig. 3. After each trigger pulse, a chirp defined by the samples set selected by EXP_SELECT_x (user signals) is generated, and presented to the DAC input to be translated into an analog signal. When the control input state changes, another waveform samples set is selected, and will be active for the next trigger pulse. For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted. March 15th, 2013 CI E03 Revision A3 2 / 11 www.rakon.com Digital pulse compression module CI E03 EXP_SELECT Waveforms RFOUT DAC TRIG Timing CLOCK Fig. 3 : Expander channel bloc diagram Compressor, featured in Fig. 4, uses a FIR filter whose coefficients are matched to the expander waveform samples. Input data are preliminary translated into baseband, and then are translated again into IF signal. Digital IF signal is then presented to the DAC to be translated into an analog IF signal. For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted. RF IN ADC To ba seba nd OS C FIR To F0 DA C RF OUT Timing Fig. 4 : Compressor channel bloc diagram Fig. 5 represents the maximum time dispersion vs. bandwidth area covered with one and two concurrent compressor channels operating. These areas assume 250 MHz internal clock, and a compressor sample period of ζ-3dB / 3.5. Contact Rakon-Temex form higher Time x Bandwidth products. Fig. 5 : Maximum Time dispersion vs. Bandwidth March 15th, 2013 CI E03 Revision A3 3 / 11 www.rakon.com Digital pulse compression module CI E03 Specifications 1.0 Environmental conditions Line Parameter Test Condition Min. Typ. Max. Unit Operating temperature range 1.1 Forced air cooling (250 ft/min at sea VITA 47 Class AC2, FC2 level) -40 +55 °C 1.2 Conduction cooling with specific heat sink VITA 47 Class CC3 -40 +70 °C -40 +85 °C 95 % RH 1.3 Storage temperature range VITA 47 Class C2 1.4 Humidity 30 °C (non condensing) Vibration 1.5 PSD (5 Hz to 100 Hz) VITA 47 Class V2 1.6 PSD (100 Hz ~ 1000 Hz) VITA 47 Class V2 1.7 PSD (100 Hz ~ 1000 Hz) VITA 47 Class V2 1.8 Shock 2.0 Electrical Interface Line Parameter increasing at 3 dB/octave g2/Hz 2 decreasing at 6 dB/octave g /Hz VITA 47, Class OS1 Test Condition g2/Hz 0.04 20 Min. Typ. Max. g Unit Power supply 2.1 Voltage 5.5 13.2 V 2.2 Power dissipation 1 1 or 2 expander channels operation 5 10 W 2.3 Power dissipation 1 1 compressor channel operation 8 15 W 2.4 Power dissipation 1 2 compressor channels operation 9.5 15 W RF_IN_A / RF_IN_B 2.5 Coupling AC 2.6 Impedance 50 2.7 Sampling rate 2.8 Resolution 2.9 Bandwidth 100 MHz 2.10 Input level 8 dBm Ω 250 12 MSPS bits March 15th, 2013 CI E03 Revision A3 4 / 11 www.rakon.com Digital pulse compression module CI E03 Line Parameter Test Condition Min. Typ. Max. Unit RF_OUT_A / RF_OUT_B 2.11 Coupling AC 2.12 Impedance 50 2.13 Sampling rate 2.14 Resolution 2.15 Bandwidth 2.16 Output level Ω 250 16 MSPS bits 100 MHz 5 dBm CLK_IN 2.17 Coupling AC 2.18 Impedance 50 2.19 Frequency 10 202 Ω 125 MHz Status signals (BOARD_OK, INITTIME_ALM, POWER_OK, TEMP_OK) 2.20 Logic high output voltage IOH = 8 mA 2.9 3.3 V 2.21 Logic low output voltage IOL = 8 mA 0 0.4 V Control signals (CLKEXT_EN, N_RST) 2.22 Logic high input voltage 2.0 3.3 V 2.23 Logic low input voltage 0 0.8 V 0 1 V Power down signal (N_BOARD_PD) 2.24 Logic low input voltage User signals (USERCLVTx) 2.25 Logic high input voltage 2.0 3.3 V 2.26 Logic low input voltage 0 0.8 V 2.27 Logic high output voltage IOH = 8 mA 2.9 3.3 V 2.28 Logic low output voltage IOL = 8 mA 0 0.4 V User signals (USERFLVTx) 2.29 Logic high input voltage 2.0 3.3 V 2.30 Logic low input voltage 0 0.8 V 2.31 Logic high output voltage 2.4 3.3 V 2.32 Logic low output voltage 0 0.4 V IOH = 2 to 24 mA (programmable) IOL = 2 to 24 mA (programmable) User signals (USERFDIFFx, programmed as single 2.5V LVCMOS signals) 2.33 Logic high input voltage 1.7 2.5 V 2.34 Logic low input voltage 0 0.7 V 2.35 Logic high output voltage 2.1 2.5 V IOH = 2 to 24 mA (programmable) March 15th, 2013 CI E03 Revision A3 5 / 11 www.rakon.com Digital pulse compression module CI E03 2.36 Logic low output voltage IOL = 2 to 24 mA (programmable) 0 0.4 V 1 Power dissipation highly depends on channels specifications. Typical figures are given as a rough guide. 2 Frequency should be divisible by 10 MHz March 15th, 2013 CI E03 Revision A3 6 / 11 www.rakon.com Digital pulse compression module CI E03 3.0 Expander operation Performances Line Parameter 3.1 Stored waveforms 3.2 Center frequency (F0) 3.3 Bandwidth (B) Test Condition Min. Typ. Max. Unit 16 100 – MHz B/2 3 100 MHz Time dispersion (T) 3.4 16 Exp Wve for each channel 2 expander channels operation 25 µs 3.5 1 Exp Wve for each channel 2 expander channels operation 400 µs 4 Measured from the trigger input rising edge to the center of the output chirp T/2 + 0.3 3.6 Minimal Expander delay (TE) 3.7 Additional Expander delay (TE) 3.8 Modulation slope Up-chirp / Down-chirp 3.9 Modulation Type Linear / Non linear Measured from the trigger input rising edge to the center of the output chirp µs 1 s 3 Some frequency values are not allowed. Center frequency should be related to the master clock by a fractional number. 4 Minimal delay depends slightly on the design. The typical figure is given as a rough guide. March 15th, 2013 CI E03 Revision A3 7 / 11 www.rakon.com Digital pulse compression module CI E03 4.0 Compressor operation Performances Line Parameter 4.1 Center frequency (F0) 4.2 Bandwidth (B) Test Condition Min. Typ. Max. Unit 100 – MHz B/2 5 46.9 MHz 267 µs Time dispersion (T) 4.3 B < 3 MHz 2 compressor operation 6 4.4 B < 7 MHz 2 compressor operation 6 48 µs 2 compressor operation 6 5 µs 178 µs 21 µs 4.5 B < 20 MHz 4.6 B < 7 MHz 1 compressor operation 6 4.7 B < 20 MHz 1 compressor operation 6 4.8 Compressed pulse width @ -3 dB (τ-3dB) 4.9 Side lobe level (SLL) 7 4.10 Minimal Compressor delay (TC) 8, 9 9 18 Measured from the center of the input chirp, to the center of the compressed pulse output ns 35 to 45 dB T/2 + 2.5 µs Measured from the center of the input chirp, to the center of the compressed pulse output 4.11 Additional Compressor delay (TC) 5 4.12 Modulation slope Up-chirp / Down-chirp 4.13 Modulation type Linear / Non linear ms 5 Some frequency values are not allowed. Center frequency should be related to the master clock by a fractional number. 6 Assuming 250 MHz FPGA processing, 3.5 points inside the compressed pulse width @ -3dB. 7 Side lobe level depends on B, T and other programmable parameters. Higher values are achievable. 8 Minimal delay depends slightly on the design. The typical figure is given as a rough guide. 9 Assuming B < 7 MHz. March 15th, 2013 CI E03 Revision A3 8 / 11 www.rakon.com Digital pulse compression module CI E03 Mechanical features 5.0 Mechanical features Line Parameter 5.1 Module size 5.2 Module height 5.3 Stacking height Test Condition Measured from the upper side of the carrier board Value Unit 75 x 120 mm 10 mm 6.4 mm 2 Fig. 6 : CI E03 interfaces drawing March 15th, 2013 CI E03 Revision A3 9 / 11 www.rakon.com Digital pulse compression module CI E03 Interfaces description J1 : Low profile 1.27 pitch, 2x50 pins connector J2 to J6 : MMCX jack connectors 6.0 Line Interfaces description Pin number Name Description 6.1 P1-76 BOARD_OK Board status correct output 6.2 P1-56 CFGCCLK FPGA configuration Clock output 6.3 P1-60 CFGCEO FPGA configuration PROM counter input 6.4 P1-50 CFGDIN FPGA configuration Data input 6.5 P1-48 CFGDONE FPGA configuration termination signal output 6.6 P1-78 CLKEXT_EN Enable external reference clock input 6.7 P1-70 INITTIME_ALM FPGA configuration time exceeded output 6.8 P1-96 JTAGTCK JTAG Clock input 6.9 P1-90 JTAGTDI JTAG Data input 6.10 P1-92 JTAGTDO JTAG Data output 6.11 P1-86 JTAGTMS JTAG Test Mode select input 6.12 P1-100 JTAG_EN JTAG clock buffer enable input 6.13 P1-93 N_BOARD_PD Board power down, active low open-drain input / output with internal pull-up. Should not be driven with a logic high level. 6.14 P1-50 N_CFGINIT FPGA configuration init signal, active low output 6.15 P1-52 N_CFGPROG FPGA configuration program signal, active low output 6.16 P1-82 N_RST Board active low reset input 6.17 P1-74 POWER_OK Board power status output 6.18 P1-72 TEMP_OK Board temperature status output 6.19 P1-68; 66; 64; 62 USERCLVT[3:0] 6.20 P1-30; 26; 22; 18; 14 (+) P1-28; 24; 20; 16; 12 (-) USERFDIFF[4:0]± 6.21 P1-10; 8; 6; 4; 2 USERFLVT[4:0] LVTTL user signals Each signal may be programmed independently as input or output May be used for waveform selection or other purpose Differential LVDS user signals Each pair may be programmed independently as input or output These signal may also be used as 2.5V LVCMOS single inputs or outputs LVTTL user signals Each signal may be programmed independently as input or output May be used for trigger input, waveform selection, or other purpose March 15th, 2013 CI E03 Revision A3 10 / 11 www.rakon.com Digital pulse compression module CI E03 Low frequency differential analog input |VANAx+ - VANAx-| ≤ 1Vpp 6.22 P1-34; 42 (+) P1-36; 40 (-) VANA[1:0]± 0 ≤ VANAx- ≤ 0.5V May be used for current measurement, RF power measurement, or other purpose 6.23 P1-59 RFU Reserved for future use 6.24 P1-11; 13; 15 VCFG 2.5V Power supply output for FPGA configuration flash PROM 6.25 P1-45; 47; 49; 51; 65; 67; 69; 71; 73; 75; 77 VINMAIN Main power input 5.5 to 13.2 V 6.26 P1-89; 91 VINVCO System clock power input 5.5 to 13.2 V / 30 mA 6.27 P1-1; 3; 5; 7; 9; 17; 19; 21; 23; 25; 27; 29; 31; 32; 33; 35; 37; 38; 39; 41; 43; 44; 53; 54; 55; 57; 58; 61; 63; 79; 80; 81; 83; 84; 85; 87; 88; 94; 95; 97; 98; 99 GNDD Digital ground 6.28 J6 REFCLK 6.29 J2 RFINA 6.30 J3 RFINB 6.31 J4 RFOUTA 6.32 J5 RFOUTB External clock input AC, 50 ohms, 0 dBm typ Channel A input AC, 50 ohms, 8 dBm max Channel B input AC, 50 ohms, 8 dBm max Channel A output AC, 50 ohms, 5 dBm max Channel B output AC, 50 ohms, 5 dBm max March 15th, 2013 CI E03 Revision A3 11 / 11 www.rakon.com