LINER LTC3375 8-channel programmable, parallelable 1a buck dc/dc Datasheet

LTC3375
8-Channel Programmable,
Parallelable 1A Buck DC/DCs
Features
n
n
n
n
n
n
n
n
n
n
Description
8-Channel Independent Step-Down DC/DCs
Master-Slave Configurable for Up to 4A Per Output
Channel with a Single Inductor
Independent VIN Supply for Each DC/DC
(2.25V to 5.5V)
All DC/DCs Have 0.425V to VIN Output Voltage Range
Precision Enable Pin Thresholds for Autonomous
Sequencing (or I2C Control)
1MHz to 3MHz Programmable/Synchronizable
Oscillator Frequency (2MHz Default)
I2C Selectable Phasing (90° Steps) Per Channel
Programmable Power-On Reset/Watch Dog/
Pushbutton Timing
Die Temperature Monitor Output
48-Lead (7mm × 7mm) QFN Package
Applications
n
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General Purpose Multichannel Power Supplies
Industrial/Automotive/Communications
The LTC®3375 is a digitally programmable high efficiency
multioutput power supply IC. The DC/DCs consist of eight
synchronous buck converters (IOUT up to 1A each) all
powered from independent 2.25V to 5.5V input supplies.
DC/DC enables, output voltages, operating modes, and
phasing may all be independently programmed over I2C
or used in standalone mode via simple I/O with power-up
defaults. The DC/DCs may be used independently or in
parallel to achieve higher output currents of up to 4A per
output with a shared inductor. Alarm levels for high die
temperature may also be programmed via I2C with a maskable IRQ output for monitoring DC/DC and system faults.
Pushbutton ON/OFF/RESET control, power-on reset, and
a watchdog timer provide flexible and reliable power-up
sequencing and system monitoring. The LTC3375 is available in a low profile 48-lead 7mm × 7mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
8-Channel 1A Multioutput Buck Regulator
4V TO 40V
ALWAYS-ON
LDO
VIN1
SW1
10µF
VCC
LTC3375
FBVCC
ON
KILL
2.2µH
FB1
VIN2
SW2
90
2.2µH
SLAVE
10µF
0.425V TO VIN2
UP TO 1A
2
RT
MASTER
VIN7
SW7
2.2µH
VIN8
SW8
60
50
40
30
Burst Mode OPERATION
VIN = 3.3V
VOUT = 1.8V
fOSC = 2MHz
L = 2.2µH
10
0.425V TO VIN7
UP TO 1A
MASTER
2.2µH
70
20
•
•
•
SLAVE
10µF
FB7
1A BUCK
2A BUCK
3A BUCK
4A BUCK
80
FB2
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
RST
TEMP
WDI
WD0
IRQ
I2C
SYNC
100
MASTER
PB
PB
Buck Efficiency vs Load
0.425V TO VIN1
UP TO 1A
EFFICIENCY (%)
VSHNT
0
1
100
1000
10
LOAD CURRENT (mA)
3375 TA01b
SLAVE
10µF
0.425V TO VIN8
UP TO 1A
FB8
CT
3375 TA01a
3375fd
For more information www.linear.com/3375
1
LTC3375
Table of Contents
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 3
Order Information........................................... 3
Pin Configuration........................................... 3
Electrical Characteristics.................................. 4
Typical Performance Characteristics.................... 7
Pin Functions............................................... 12
Block Diagram.............................................. 15
Operation................................................... 16
Buck Switching Regulators...................................... 16
Buck Regulators with Combined Power Stages....... 16
Pushbutton Interface............................................... 17
Power-Up and Power-Down Via Pushbutton............ 17
Power-Up and Power-Down Via Enable Pin or I2C... 19
I2C Interface............................................................20
I2C Bus Speed..........................................................20
I2C Start and Stop Conditions..................................20
I2C Byte Format.......................................................20
I2C Acknowledge.....................................................20
I2C Slave Address.................................................... 21
I2C Sub-Addressed Writing......................................22
I2C Bus Write Operation ..........................................22
I2C Bus Read Operation...........................................22
Error Condition Reporting Via RST and IRQ Pins.....22
Temperature Monitoring and
Overtemperature Protection....................................23
RESET_ALL Functionality........................................ 24
Programming the Operating Frequency................... 24
VCC Shunt Regulator................................................25
Watchdog Timer......................................................25
2
Applications Information................................. 26
Buck Switching Regulator Output Voltage and
Feedback Network...................................................26
Buck Regulators......................................................26
Combined Buck Regulators.....................................26
VCC Shunt Regulator................................................ 28
Input and Output Decoupling Capacitor Selection ..29
Choosing the CT Capacitor.......................................29
Programming the Global Register............................29
Programming the RST and IRQ Mask Registers......29
Status Byte Read Back............................................29
PCB Considerations................................................. 31
Typical Applications....................................... 32
Package Description...................................... 35
Typical Application........................................ 36
Related Parts............................................... 36
3375fd
For more information www.linear.com/3375
LTC3375
(Note 1)
TOP VIEW
FB1 1
VIN1 2
SW1 3
SW2 4
VIN2 5
FB2 6
FB3 7
VIN3 8
SW3 9
SW4 10
VIN4 11
FB4 12
36 FB8
35 VIN8
34 SW8
33 SW7
32 VIN7
31 FB7
30 FB6
29 VIN6
28 SW6
27 SW5
26 VIN5
25 FB5
GND
49
EN4 13
EN3 14
IRQ 15
RST 16
CT 17
SYNC 18
RT 19
ON 20
PB 21
KILL 22
EN6 23
EN5 24
VIN1-8, FB1-8, EN1-8, VCC, VSHNT, FBVCC, CT,
ON, KILL, IRQ, RST, PB, WDI, WDO, SYNC, RT,
SDA, SCL...................................................... –0.3V to 6V
TEMP....................–0.3V to Lesser of (VCC + 0.3V) or 6V
IIRQ , IRST, IWDO, ION..................................................5mA
IVSHNT.......................................................................3mA
Operating Junction Temperature Range
(Notes 2, 3)............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
48 EN1
47 EN2
46 SDA
45 SCL
44 TEMP
43 VSHNT
42 FBVCC
41 VCC
40 WDI
39 WDO
38 EN7
37 EN8
Absolute Maximum Ratings
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3375EUK#PBF
LTC3375EUK#TRPBF
LTC3375UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3375IUK#PBF
LTC3375IUK#TRPBF
LTC3375UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 125°C
LTC3375HUK#PBF
LTC3375HUK#TRPBF
LTC3375UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3375fd
For more information www.linear.com/3375
3
LTC3375
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
VVCC
VCC Voltage Range
VVCC_UVLO
Undervoltage Threshold on VCC
VCC Voltage Falling
VCC Voltage Rising
IVCC_ALLOFF
VCC Input Supply Current
IVCC
VCC Input Supply Current
fOSC
Internal Oscillator Frequency
fSYNC
Synchronization Frequency
VSYNC
SYNC Level High
SYNC Level Low
VRT
RT Servo Voltage
CONDITIONS
TYP
MAX
5.5
V
2.45
2.55
2.55
2.65
V
V
All Switching Regulators in Shutdown,
PB = HIGH
11
25
µA
At Least 1 Buck Active, SYNC = 0V, RT = 400k,
VFB_BUCK = 0.85V
At Least 1 Buck Active, SYNC = 2MHz
50
85
µA
200
325
µA
2
2
2
2.2
2.25
2.2
MHz
MHz
MHz
3
MHz
VRT = VCC, SYNC = 0V
VRT = VCC, SYNC = 0V
RRT = 400k, SYNC = 0V
MIN
l
2.7
l
l
2.35
2.45
l
l
tLOW, tHIGH > 40ns
RRT = 400k
1.8
1.75
1.8
1
l
l
1.2
l
780
800
UNITS
0.4
V
V
820
mV
Temperature Monitor
VTEMP(ROOM)
TEMP Voltage at 25°C
∆VTEMP/°C
VTEMP Slope
l
OT
Overtemperature Shutdown
OT_HYST
Overtemperature Hysteresis
Temperature Rising
DT_WARN
Die Temperature Warning Threshold (Die DT[1], DT[0] = 00
Temperature that Causes IRQ = 0)
DT[1], DT[0] = 01
DT[1], DT[0] = 10
DT[1], DT[0] = 11
150
mV
6.75
mV/°C
165
°C
10
°C
Inactive
140
125
110
°C
°C
°C
1A Buck Regulators
VBUCK
Buck Input Voltage Range
VOUT
l
2.25
5.5
V
l
VFB
VIN
V
l
l
1.95
2.05
2.05
2.15
2.15
2.25
V
V
18
400
0
1
50
550
1
2
µA
µA
µA
µA
2.0
2.3
2.7
A
VIN_UVLO
Undervoltage Threshold on VIN
VIN Voltage Falling
VIN Voltage Rising
IVIN_BUCK
Burst Mode® Operation
Forced Continuous Mode Operation
Shutdown Input Current
Shutdown Input Current
VFB_BUCK = 0.85V (Note 4)
ISW_BUCK = 0µA, VFB_BUCK = 0V
All Switching Regulators in Shutdown
At Least One Other Buck Active
IFWD
PMOS Current Limit
(Note 5)
VFB (Default)
Feedback Regulation Voltage
Forced Continuous Mode Default (1, 1, 0, 0)
l
705
725
745
mV
VFB (High)
Feedback Regulation Voltage
Forced Continuous Mode Full Scale (1, 1, 1, 1)
l
780
800
820
mV
VFB (Low)
Feedback Regulation Voltage
Forced Continuous Mode Zero Scale (0, 0, 0, 0) l
405
425
445
mV
–50
VLSB
VFB Servo Voltage Step Size
IFB
Feedback Leakage Current
VFB_BUCK = 0.85V
DMAX
Maximum Duty Cycle
VFB_BUCK = 0V
RPMOS
PMOS On-Resistance
ISW_BUCK = 100mA
335
mΩ
RNMOS
NMOS On-Resistance
ISW_BUCK = –100mA
315
mΩ
ILEAKP
PMOS Leakage Current
EN_BUCK = 0
–2
2
µA
ILEAKN
NMOS Leakage Current
EN_BUCK = 0
–2
2
µA
RSWPD
Output Pull-Down Resistance in Shutdown
EN_BUCK = 0 (I2C Bit Set)
1
tSS
Soft-Start Time
Default (1, 1, 0, 0) Reference Voltage
1
4
25
l
mV
50
100
nA
%
kΩ
ms
3375fd
For more information www.linear.com/3375
LTC3375
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VPGOOD(FALL)
Falling PGOOD Threshold Voltage
% of Full-Scale (1, 1, 1, 1) Reference Voltage
VPGOOD(HYS)
PGOOD Hysteresis
% of Regulated VFB
MIN
TYP
MAX
UNITS
92.5
%
1
%
Buck Regulators Combined
IFWD2
PMOS Current Limit
2 Buck Converters Combined (Note 5)
4.6
A
IFWD3
PMOS Current Limit
3 Buck Converters Combined (Note 5)
6.9
A
IFWD4
PMOS Current Limit
4 Buck Converters Combined (Note 5)
9.2
A
VCC Regulator
VFBVCC
FBVCC Regulation Voltage
RREG
Pull-Down Resistance for VCC
(Regulator)
VVSHNT_MAX
VSHNT Clamp Voltage
RCLAMP
Pull-Down Resistance for VSHNT (Clamp)
1.17
1.2
ISHNT = 2mA, FBVCC = 0V
1.23
V
200
Ω
6.1
V
200
Ω
I2C Port
ADDRESS
I2C Address
VIH
Input High Voltage
SDA/SCL
l
VIL
Input Low Voltage
SDA/SCL
l
IIH
Input High Current
SDA/SCL
IIL
Input Low Current
VOL_SDA
SDA Output Low Voltage
fSCL
Clock Operating Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
1.3
µs
tHD_SDA
Hold Time After Repeated Start
Condition
0.6
µs
tSU_STA
Repeated Start Condition Set-Up Time
0.6
µs
tSU_STO
Stop Condition Set-Up Time
0.6
µs
tHD_DAT(O)
Data Hold Time Output
0110100[R/WB]
l
1.2
V
0.4
V
50
nA
SDA/SCL
50
nA
ISDA = 3mA
0.4
V
400
kHz
0
900
ns
tHD_DAT(I)
Data Hold Time Input
0
ns
tSU_DAT
Data Set-Up Time
250
ns
tLOW
SCL Clock Low Period
1.3
µs
tHIGH
SCL Clock High Period
tf
Clock/Data Fall Time
CB = Capacitance of One Bus Line (pF)
20+0.1CB
300
ns
tr
Clock/Data Rise Time
CB = Capacitance of One Bus Line (pF)
20+0.1CB
300
ns
-1
1
µA
0.6
µs
Interface Logic Pins (ON, KILL, RST, IRQ, PB, WDI, WDO)
IOH
Output High Leakage Current
ON, RST, IRQ, WDO 5.5V at Pin
VOL
Output Low Voltage
ON, RST, IRQ, WDO 3mA Into Pin
VIH
Input High Threshold
KILL, PB, WDI
l
VIL
Input Low Threshold
KILL, PB, WDI
l
tWDI
Time From Last WDI
1.5
sec
tWDO
WDO Low Time Absent a Transition at WDI
200
ms
tWDRESET
Time From a WDI Transition Until the
WD Timer Is Reset
0.1
0.4
1.2
V
V
0.4
2
V
µs
3375fd
For more information www.linear.com/3375
5
LTC3375
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1200
mV
Interface Logic Pins (EN1, EN2, EN3, EN4, EN5, EN6, EN7, EN8)
VHI_ALLOFF
Enable Rising Threshold
All Regulators Disabled
l
400
730
l
380
400
VEN_HYS
Enable Hysteresis
VHI
Enable Rising Threshold
At Least One Regulator Enabled
60
IEN
Enable Pin Leakage Current
EN = VCC = VIN = 5.5V
–1
ON High
28
mV
420
mV
1
µA
50
72
ms
140
200
260
ms
Pushbutton Parameters, CT = 0.01µF
tPB_LO
PB Low Time to IRQ Low
tPB_ON
PB Low Time to ON High
tPB_OFF
PB Low to ON Forced Low
7
10
13
sec
tHR
Time for Which All Enabled Regulators
ON High
Are Disabled After KILL is Asserted High
0.7
1
1.3
sec
tIRQ_PW
IRQ Minimum Pulse Width
ON High
28
50
72
ms
tKILLH
Time in Which KILL Must Be Asserted
High
After ON Rising Edge
7
10
13
sec
tKILLL
KILL Low Time to ON Low
ON High
28
50
72
ms
tRST
RST Assertion Delay
160
230
300
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3375 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3375E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3375I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3375H is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
6
(TJ in °C) is calculated from the ambient temperature (TA in °C) and
power dissipation (PD in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: The LTC3375 includes overtemperature protection which protects
the device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 4: Static current, switches not switching. Actual current may be
higher due to gate charge losses at the switching frequency.
Note 5: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the maximum specified pin current rating may result in device
degradation over time.
3375fd
For more information www.linear.com/3375
LTC3375
Typical Performance Characteristics
Buck VIN Undervoltage Threshold
vs Temperature
2.30
2.65
2.25
2.60
VCC RISING
2.55
2.50
VCC FALLING
2.45
2.40
60
ALL REGULATORS
55 IN SHUTDOWN
50
2.20
VIN RISING
2.15
2.10
VIN FALLING
2.05
2.00
2.35
0
0
VCC = 3.3V
50
240
VCC = 3.3V
200
VCC = 2.7V
160
2.05
2.00
1.95
0
–50 –25
0
1.80
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
Oscillator Frequency vs RT
Oscillator Frequency vs VCC
4.0
2.15
2.15
3.5
2.10
2.10
3.0
2.05
2.05
1.85
1.80
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G07
VRT = VCC
2.00
fOSC (MHz)
fOSC (MHz)
VRT = VCC
VCC = 5.5V
VCC = 3.3V
VCC = 2.7V
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G06
2.20
1.90
0
3375 G05
3375 G04
Default Oscillator Frequency
vs Temperature
1.95
VCC = 5.5V
VCC = 3.3V
VCC = 2.7V
1.85
40
25 50 75 100 125 150
TEMPERATURE (°C)
RRT = 400k
1.90
80
2.00
25 50 75 100 125 150
TEMPERATURE (°C)
2.10
VCC = 5.5V
120
25
2.20
0
2.15
fOSC (MHz)
IVCC (µA)
IVCC (µA)
2.20
320
VCC = 5.5V
VCC = 2.7V
RT Programmed Oscillator
Frequency vs Temperature
AT LEAST ONE BUCK ENABLED
360 SYNC = 2MHz
VCC = 2.7V
fOSC (MHz)
VCC = 3.3V
3375 G03
400
280
0
VCC = 5.5V
15
VCC Supply Current
vs Temperature
AT LEAST ONE BUCK ENABLED
SYNC = 0V
FB = 850mV
0
–50 –25
20
3375 G02
VCC Supply Current
vs Temperature
75
30
25
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G01
100
35
5
1.90
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
45
40
10
1.95
2.30
–50 –25
125
VCC Supply Current
vs Temperature
IVCC_ALLOFF (µA)
2.70
UV THRESHOLD (V)
UV THRESHOLD (V)
VCC Undervoltage Threshold
vs Temperature
RRT = 400k
1.95
2.5
2.0
1.5
1.90
1.0
1.85
0.5
1.80
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
3375 G08
VCC = 3.3V
0
250 300 350 400 450 500 550 600 650 700 750 800
RRT (kΩ)
3375 G09
3375fd
For more information www.linear.com/3375
7
LTC3375
Typical Performance Characteristics
VTEMP vs Temperature
1400
900
ALL REGULATORS DISABLED
VCC = 3.3V
1200
850
415
600
400 ACTUAL VTEMP
200
750
EN THRESHOLD (mV)
EN THRESHOLD (mV)
EN RISING
700
650
EN FALLING
600
550
500
0
0
20
40
60
80 100 120
TEMPERATURE (°C)
400
–50 –25
140
0
VIN = 5.5V
VIN = 2.25V
VIN = 3.3V
450
1.86
VIN = 5.5V
400
0
350
VIN = 2.25V
300
250
1.78
1.76
100
600
0
2.5
RDS(ON) (mΩ)
IFWD (A)
2.1
2
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G15
NMOS RDS(ON) vs Temperature
600
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
550
500
500
450
450
400
350
350
300
250
250
200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G17
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
400
300
3375 G16
8
1.72
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
PMOS RDS(ON) vs Temperature
550
2.2
VIN = 3.3V
1.74
RDS(ON) (mΩ)
VIN = 3.3V
2.3
VIN = 2.25V
3375 G14
PMOS Current Limit
vs Temperature
2.4
VIN = 5.5V
1.8
150
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
FORCED CONTINUOUS MODE
ILOAD = 0mA
1.82
200
3375 G13
2.6
25 50 75 100 125 150
TEMPERATURE (°C)
1.84
VIN = 3.3V
50
0
–50 –25
0
VOUT vs Temperature
1.88
FORCED CONTINUOUS MODE
500 FB = 0V
IVIN_FORCED_CONTINUOUS (µA)
Burst Mode OPERATION
FB = 850mV
10
390
3375 G12
550
30
EN FALLING
395
Buck VIN Supply Current
vs Temperature
40
EN RISING
400
3375 G11
Buck VIN Supply Current
vs Temperature
20
405
380
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G10
50
410
385
450
IDEAL VTEMP
VOUT (V)
VTEMP (mV)
800
IVIN_BURST (µA)
420
ALL REGULATORS DISABLED
VCC = 3.3V
800
1000
–200
Enable Pin Precision Threshold
vs Temperature
Enable Threshold vs Temperature
200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G18
3375fd
For more information www.linear.com/3375
LTC3375
Typical Performance Characteristics
3.32
3.30
3.28
3.26
3.24
3.22
3.20
–50 –25
0
100
6.18
90
6.16
80
6.14
70
6.12
6.10
6.08
20
6.02
10
100
100
90
90
Burst Mode
OPERATION
40
30
20
10
0
1
EFFICIENCY (%)
EFFICIENCY (%)
50
VOUT = 1.8V
fOSC = 2MHz
L = 2.2µH
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
60
50
40
20
10
0
1
10
100
LOAD CURRENT(mA)
70
50
40
30
20
10
0
1000
3A Buck Efficiency vs ILOAD,
VOUT = 2.5V
100
100
90
90
80
50
40
30
20
10
0
1
10
100
LOAD CURRENT(mA)
1000
3375 G25
EFFICIENCY (%)
80
VOUT = 1.8V
fOSC = 2MHz
L = 2.2µH
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
1000
10
100
LOAD CURRENT(mA)
4A Buck Efficiency vs ILOAD,
VOUT = 1.8V
90
60
1
3375 G24
100
Burst Mode
OPERATION
VOUT = 2.5V
fOSC = 2MHz
L = 2.2µH
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
60
3375 G23
3A Buck Efficiency vs ILOAD,
VOUT = 1.8V
70
Burst Mode
OPERATION
80
70
30
1000
10
100
LOAD CURRENT(mA)
90
Burst Mode
OPERATION
3375 G22
EFFICIENCY (%)
2A Buck Efficiency vs ILOAD,
VOUT = 2.5V
100
80
VOUT = 2.5V
fOSC = 2MHz
L = 2.2µH
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
1000
10
100
LOAD CURRENT(mA)
3375 G21
2A Buck Efficiency vs ILOAD,
VOUT = 1.8V
70
1
3375 G20
1A Buck Efficiency vs ILOAD,
VOUT = 2.5V
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G19
80
40
30
0
VOUT = 1.8V
1.8V
fVOSC
OUT==2MHz
= 2MHz
LfOSC
= 2.2µH
LV=IN2.2µH
= 2.25V
VIN = 3.3V
VIN = 5.5V
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
50
6.04
6.00
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
Burst Mode OPERATION
60
6.06
VOUT = 2.5V
fOSC = 2MHz
L = 2.2µH
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
60
50
40
30
20
10
0
80
Burst Mode
OPERATION
70
1
10
100
LOAD CURRENT(mA)
1000
3375 G26
EFFICIENCY (%)
VCC (V)
3.34
6.20
EFFICIENCY (%)
VSHNT CLAMP VOLTAGE (V)
FOR VCC FEEDBACK DIVIDER
3.38 R
TOP = 187k
3.36 RBOT = 107k
EFFICIENCY (%)
3.40
1A Buck Efficiency vs ILOAD,
VOUT = 1.8V
VSHNT Clamp Voltage
vs Temperature
VCC vs Temperature
Burst Mode
OPERATION
70
60
VOUT = 1.8V
fOSC = 2MHz
L = 2.2µH
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
50
40
30
20
10
0
1
10
100
LOAD CURRENT(mA)
1000
3375 G27
3375fd
For more information www.linear.com/3375
9
LTC3375
Typical Performance Characteristics
4A Buck Efficiency vs ILOAD,
VOUT = 2.5V
100
90
90
60
50
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
VIN = 2.7V
VIN = 3.3V
VIN = 5.5V
FORCED CONTINUOUS MODE
40
30
20
10
0
EFFICIENCY (%)
1
1000
10
100
LOAD CURRENT(mA)
VOUT = 2.5V
3375 G28
fOSC = 2MHz
L = 2.2µH
70
50
40
80
ILOAD = 500mA
70
ILOAD = 20mA
60
50
40
30
30
20 V
OUT = 1.8V
10 ILOAD = 100mA
L = 3.3µH
0
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
FREQUENCY (MHz)
20
1A Buck Efficiency vs ILOAD
(Across Operating Frequency)
VOUT = 1.8V
10 VIN = 3.3V
L = 3.3µH
0
1 1.2 1.4 1.6 1.8
3
1A Buck Regulator Load Regulation
(Forced Continuous Mode)
4A Buck Regulator Load Regulation
(Forced Continuous Mode)
1.816
1.816
80
1.812
70
1.808
60
1.804
30
20
10
0
1
VOUT = 1.8V
VIN = 3.3V
10
100
LOAD CURRENT (mA)
1000
VOUT (V)
fOSC = 1MHz, L = 3.3µH
fOSC = 2MHz, L = 2.2µH
fOSC = 3MHz, L = 1µH
fOSC = 1MHz, L = 3.3µH
fOSC = 2MHz, L = 2.2µH
fOSC = 3MHz, L = 1µH
FORCED CONTINUOUS MODE
40
1.8
1.796
1.812
VIN = 5.5V
1.808
1.804
VIN = 3.3V
1.8
1.796
VIN = 2.25V
1.792
1.792
1.788
1.784 fOSC = 2MHz
L = 2.2µH
1.78
1
10
1000
100
3375 G31
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
1.788
DROPOUT
1.784 fOSC = 2MHz
L = 2.2µH
1.78
1
10
DROPOUT
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3375 G33
3375 G32
1A Buck Regulator Line Regulation
(Forced Continuous Mode)
3
3375 G30
90
50
2.2 2.4 2.6 2.8
3375 G29
1.82
Burst Mode OPERATION
2
FREQUENCY (MHz)
1.82
100
EFFICIENCY (%)
VIN = 5.5V
60
VOUT (V)
EFFICIENCY (%)
70
ILOAD = 100mA
90
VIN = 3.3V
80
Burst Mode
OPERATION
100
VIN = 2.25V
EFFICIENCY (%)
100
80
1A Buck Efficiency vs Frequency
(Forced Continuous Mode)
1A Buck Efficiency vs Frequency
(Forced Continuous Mode)
4A Buck Regulator No Load
Startup Transient
(Forced Continuous Mode)
1A Buck Regulator No Load
Startup Transient (Burst Mode)
1.82
1.815
1.81
VOUT (V)
1.805
1.8
ILOAD = 100mA
1.795
ILOAD 500mA
1.79
1.785 f
OSC = 2MHz
L = 2.2µH
1.78
2.25 2.75 3.25
VOUT
500mV/DIV
VOUT
500mV/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
EN
2V/DIV
EN
2V/DIV
200µs/DIV
3.75
4.25
4.75
3375 G35
200µs/DIV
3375 G36
5.25
VIN (V)
3375 G34
10
3375fd
For more information www.linear.com/3375
LTC3375
Typical Performance Characteristics
1A Buck Regulator,
Transient Response
(Forced Continuous Mode)
1A Buck Regulator, Transient
Response (Burst Mode)
VOUT
100mV/DIV
AC-COUPLED
VOUT
100mV/DIV
AC-COUPLED
INDUCTOR
CURRENT
200mA/DIV
INDUCTOR
CURRENT
200mA/DIV
0mA
0mA
3375 G37
50µs/DIV
LOAD STEP = 100mA TO 700mA
VIN = 3.3V, VOUT = 1.8V
50µs/DIV
LOAD STEP = 100mA TO 700mA
VIN = 3.3V, VOUT = 1.8V
4A Buck Regulator,
Transient Response
(Forced Continuous Mode)
4A Buck Regulator, Transient
Response (Burst Mode)
VOUT
100mV/DIV
AC-COUPLED
VOUT
100mV/DIV
AC-COUPLED
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
0mA
0mA
50µs/DIV
LOAD STEP = 400mA TO 2.8A
VIN = 3.3V, VOUT = 1.8V
3375 G38
3375 G39
50µs/DIV
LOAD STEP = 400mA TO 2.8A
VIN = 3.3V, VOUT = 1.8V
3375 G40
3375fd
For more information www.linear.com/3375
11
LTC3375
Pin Functions
FB1 (Pin 1): Buck Regulator 1 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
VIN1 (Pin 2): Buck Regulator 1 Input Supply. Bypass to
GND with a 10µF or larger ceramic capacitor.
SW1 (Pin 3): Buck Regulator 1 Switch Node. External
inductor connects to this pin.
SW2 (Pin 4): Buck Regulator 2 Switch Node. External
inductor connects to this pin.
VIN2 (Pin 5): Buck Regulator 2 Input Supply. Bypass to GND
with a 10µF or larger ceramic capacitor. May be driven by
an independent supply or must be shorted to VIN1 when
buck regulator 2 is combined with buck regulator 1 for
higher current.
FB2 (Pin 6): Buck Regulator 2 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB2 to VIN2 combines buck regulator 2 with
buck regulator 1 for higher current. Up to 4 converters
may be combined in this way.
FB3 (Pin 7): Buck Regulator 3 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB3 to VIN3 combines buck regulator 3 with
buck regulator 2 for higher current. Up to 4 converters
may be combined in this way.
VIN3 (Pin 8): Buck Regulator 3 Input Supply. Bypass to GND
with a 10µF or larger ceramic capacitor. May be driven by
an independent supply or must be shorted to VIN2 when
buck regulator 3 is combined with buck regulator 2 for
higher current.
SW3 (Pin 9): Buck Regulator 3 Switch Node. External
inductor connects to this pin.
SW4 (Pin 10): Buck Regulator 4 Switch Node. External
inductor connects to this pin.
12
VIN4 (Pin 11): Buck Regulator 4 Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor. May be
driven by an independent supply or must be shorted to VIN3
when buck regulator 4 is combined with buck regulator 3
for higher current.
FB4 (Pin 12): Buck Regulator 4 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB4 to VIN4 combines buck regulator 4 with
buck regulator 3 for higher current. Up to 4 converters
may be combined in this way.
EN4 (Pin 13): Buck Regulator 4 Enable Input. Active high.
EN3 (Pin 14): Buck Regulator 3 Enable Input. Active high.
IRQ (Pin 15): Interrupt Pin (Active Low). Open-drain output.
When an undervoltage, die temperature, or unmasked error
condition is detected, this pin is driven LOW.
RST (Pin 16): Reset Pin (Active Low). Open-drain output.
When the regulated output voltage of any unmasked
enabled switching regulator is more than 7.5% below its
programmed level, this pin is driven LOW. Assertion delay
is scaled by the CT capacitor. When all buck regulators
are disabled RST is driven LOW.
CT (Pin 17): Timing Capacitor Pin. A capacitor connected
to GND sets a time constant which is scaled for use by
the ON, KILL, PB, RST and IRQ pins.
SYNC (Pin 18): Oscillator Synchronization Pin. Driving
SYNC with an external clock signal will synchronize all
switchers to the applied frequency. The slope compensation
is automatically adapted to the external clock frequency.
The absence of an external clock signal will enable the
frequency programmed by the RT pin. Do not float. SYNC
should be held at ground if not used.
RT (Pin 19): Oscillator Frequency Pin. This pin provides
two modes of setting the switching frequency. Connecting a
resistor from RT to ground will set the switching frequency
based on the resistor value. If RT is tied to VCC the default
internal 2MHz oscillator will be used. Do not float.
3375fd
For more information www.linear.com/3375
LTC3375
Pin Functions
ON (Pin 20): Open-Drain Output. When the PB pin is
pressed and released, the signal is debounced and the
ON signal is held HIGH for a minimum time period that
is scaled by the CT capacitor. ON is forced low if: a) KILL
is not driven high (by µP) within 10 seconds of the initial
valid PB power turn-on event, b) KILL is driven low during
normal operation, c) PB is pressed and held low for 10
seconds during normal operation, d) a RESET_ALL I2C
command is written. This pin can connect directly to a
DC/DC converter enable pin that provides an internal pullup. Otherwise a pull-up resistor to an external supply is
required. All associated times are scaled by the CT capacitor.
PB (Pin 21): Pushbutton Input. Active low. PB is internally
pulled to VCC through a 420k (typical) resistor.
KILL (Pin 22): Kill Input Pin. Forcing KILL low releases
the ON output which in turn is forced low. While KILL is
low, the buck converters will be forced to power down
and will remain powered down for 1 second (scaled by
the CT capacitor) after KILL returns high. During system
turn-on, this pin is blanked by a 10 second (scaled by
the CT capacitor) (tKILLH) to allow the system to pull KILL
high. If unused, connect to VCC.
EN6 (Pin 23): Buck Regulator 6 Enable Input. Active high.
EN5 (Pin 24): Buck Regulator 5 Enable Input. Active high.
FB5 (Pin 25): Buck Regulator 5 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB5 to VIN5 combines buck regulator 5 with
buck regulator 4 for higher current. Up to 4 converters
may be combined in this way.
VIN5 (Pin 26): Buck Regulator 5 Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor. May be
driven by an independent supply or must be shorted to VIN4
when buck regulator 5 is combined with buck regulator 4
for higher current.
SW5 (Pin 27): Buck Regulator 5 Switch Node. External
inductor connects to this pin.
SW6 (Pin 28): Buck Regulator 6 Switch Node. External
inductor connects to this pin.
VIN6 (Pin 29): Buck Regulator 6 Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor. May be
driven by an independent supply or must be shorted to VIN5
when buck regulator 6 is combined with buck regulator 5
for higher current.
FB6 (Pin 30): Buck Regulator 6 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB6 to VIN6 combines buck regulator 6 with
buck regulator 5 for higher current. Up to 4 converters
may be combined in this way.
FB7 (Pin 31): Buck Regulator 7 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB7 to VIN7 combines buck regulator 7 with
buck regulator 6 for higher current. Up to 4 converters
may be combined in this way.
VIN7 (Pin 32): Buck Regulator 7 Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor. May be
driven by an independent supply or must be shorted to VIN6
when buck regulator 7 is combined with buck regulator 6
for higher current.
SW7 (Pin 33): Buck Regulator 7 Switch Node. External
inductor connects to this pin.
SW8 (Pin 34): Buck Regulator 8 Switch Node. External
inductor connects to this pin.
VIN8 (Pin 35): Buck Regulator 8 Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor. May be
driven by an independent supply or must be shorted to VIN7
when buck regulator 8 is combined with buck regulator 7
for higher current.
FB8 (Pin 36): Buck Regulator 8 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
Connecting FB8 to VIN8 combines buck regulator 8 with
buck regulator 7 for higher current. Up to 4 converters
may be combined in this way.
EN8 (Pin 37): Buck Regulator 8 Enable Input. Active high.
EN7 (Pin 38): Buck Regulator 7 Enable Input. Active high.
3375fd
For more information www.linear.com/3375
13
LTC3375
Pin Functions
WDO (Pin 39): Watchdog Timer Output. Open-drain
output. WDO is pulled low for 200ms during a watchdog
timer failure.
WDI (Pin 40): Watchdog Timer Input. The WDI pin must
be toggled either low to high or high to low every 1.5
seconds. Failure to toggle WDI results in the WDO pin
being pulled low for 200ms.
VCC (Pin 41): Always-On LDO Output Voltage/Internal
Bias Supply. When used as a regulator, VCC should be
connected to the emitter/source of the external LDO NPN/
NFET transistor. VCC serves as a low voltage rail that may
be used to provide power to external circuitry, and is
also used to power the internal top level circuitry of the
LTC3375. Alternatively the VCC pin may be connected to
a 2.7V to 5.5V external power supply. In this case FBVCC
and VSHNT should be tied to ground.
TEMP (Pin 44): Temperature Indication Pin. TEMP outputs a voltage of 150mV (typical) at room temperature.
The TEMP voltage will change by 6.75mV/°C (typical)
giving an external indication of the LTC3375 internal die
temperature.
SCL (Pin 45): Serial Clock Line for I2C Port.
SDA (Pin 46): Serial Data Line for I2C Port. Open-drain
output during read back.
EN2 (Pin 47): Buck Regulator 2 Enable Input. Active high.
EN1 (Pin 48): Buck Regulator 1 Enable Input. Active high.
GND (Exposed Pad Pin 49): Ground. The exposed pad
must be connected to a continuous ground plane on the
printed circuit board directly under the LTC3375 for electrical contact and rated thermal performance.
FBVCC (Pin 42): Always-On LDO Feedback Pin. Receives
feedback by a resistor divider connected across VCC.
VSHNT (Pin 43): Shunt Regulator Base Control Voltage.
VSHNT should be connected to the base/gate of an external
high voltage NPN/NFET transistor and to its collector/drain
through a resistor.
14
3375fd
For more information www.linear.com/3375
LTC3375
Block Diagram
41
VCC
LDO
43
42
18
19
44
2
3
1
48
VSHNT
FBVCC
+
–
TOP LOGIC,
CT OSCILLATOR
TIMING
1.2V
4
6
47
8
9
7
14
11
10
12
13
SDA
RST
IRQ
KILL
SYNC
RT
ON
REF, CLK
CT
TEMP
BANDGAP,
OSCILLATOR,
UV, OT
TEMP MONITOR
PB
WDI
WDO
OUTPUT VOLTAGE, SLEW CONTROL
MODE, PHASE, EN, STATUS BITS
VIN1
VIN8
SW1
SW8
FB1
BUCK REGULATOR 1
1A
BUCK REGULATOR 8
1A
EN1
FB8
EN8
MASTER/SLAVE LINES
5
SCL
I2C
VIN7
SW2
SW7
BUCK REGULATOR 2
1A
BUCK REGULATOR 7
1A
EN2
VIN3
MASTER/SLAVE LINES
VIN6
BUCK REGULATOR 3
1A
BUCK REGULATOR 6
1A
SW6
FB6
EN6
MASTER/SLAVE LINES
15
22
20
17
21
40
39
35
34
36
37
32
33
31
38
29
28
30
23
MASTER/SLAVE LINES
VIN5
SW4
FB4
16
MASTER/SLAVE LINES
EN3
VIN4
FB7
EN7
SW3
FB3
46
MASTER/SLAVE LINES
VIN2
FB2
45
BUCK REGULATOR 4
1A
BUCK REGULATOR 5
1A
EN4
SW5
FB5
EN5
26
27
25
24
MASTER/SLAVE LINES
GND (EXPOSED PAD)
49
3375 BD
3375fd
For more information www.linear.com/3375
15
LTC3375
Operation
Buck Switching Regulators
The LTC3375 contains eight monolithic 1A synchronous
buck switching regulators. All of the switching regulators
are internally compensated and need only external feedback
resistors to set the output voltage. The switching regulators offer two operating modes: Burst Mode operation
(power-up default mode) for higher efficiency at light
loads and forced continuous PWM mode for lower noise
at light loads. In Burst Mode operation at light loads, the
output capacitor is charged to a voltage slightly higher
than its regulation point. The regulator then goes into sleep
mode, during which time the output capacitor provides the
load current. In sleep most of the regulator’s circuitry is
powered down, helping conserve input power. When the
output capacitor droops below its programmed value, the
circuitry is powered on and another burst cycle begins.
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate at constant
frequency PWM mode operation. In forced continuous
mode (selectable via I2C command), the oscillator runs
continuously and the buck switch currents are allowed
to reverse under very light load conditions to maintain
regulation. This mode allows the buck to run at a fixed
frequency with minimal output ripple.
Each buck switching regulator has its own VIN, SW, FB
and EN pin to maximize flexibility. The enable pins have
two different enable threshold voltages that depend on
the operating state of the LTC3375. With all regulators
disabled, the enable pin threshold is set to 730mV (typical).
Once any regulator is enabled, the enable pin thresholds
of the remaining regulators are set to a bandgap-based
400mV and the EN pins are each monitored by a precision
comparator. This precision EN threshold may be used to
provide event-based sequencing via feedback from other
previously enabled regulators. All buck regulators have
forward and reverse-current limiting, soft-start to limit
inrush current during start-up, and short-circuit protection.
Each buck can operate in standalone mode using the EN
pin in its default MODE and FB reference settings, or be
fully controlled using the I2C port. I2C commands may
be used to independently program each buck regulators’
operating mode, oscillator phase, and reference voltage in
16
addition to simple ON/OFF control. Each buck may have its
phase programmed in 90° phase steps via I2C. The phase
step command programs the fixed edge of the switching
sequence, which is when the PMOS turns on. The PMOS
off (NMOS on) phase is subject to the duty cycle demanded
by the regulator. Bucks 1 and 2 default to 0°, bucks 3 and 4
default to 90°, bucks 5 and 6 default to 180°, and bucks 7
and 8 default to 270°. Each buck can have its feedback
voltage independently programmed in 25mV increments
from 425mV to 800mV. All regulators’ feedback voltages
default to 725mV at initial power-up. In cases where power
stages are combined, the register content of the master
program the combined buck regulator’s behavior and the
register contents of the slave are ignored.
Two additional I2C commands act on all the buck switching regulators together. In shutdown, an I2C control bit
keeps all the SW nodes in a high impedance state (default)
or forces all the SW nodes to decay to GND through 1k
(typical) resistors. Also, the slew rate of the SW nodes
may be switched from the default value to a lower value
for reduced radiated EMI at the cost of a small drop in
efficiency.
Each buck regulator may be enabled via its enable pin or
I2C. The buck regulator enable pins may be tied to VOUT
voltages, through a resistor divider, to program powerup sequencing. If a different power-down sequence is
required, the enables can be redundantly written via I2C.
The EN pins can then be ignored via an I2C command,
and the switching regulators may be powered down via
I2C while the EN pins remain tied to the output voltages
of other regulators.
In addition to many programming options, there are also
17 bits of data that may be read back to report fault conditions on the LTC3375, and all I2C commands can be read
back prior to executing.
Buck Regulators with Combined Power Stages
Up to four adjacent buck regulators may be combined
in a master-slave configuration by connecting their SW
pins together, connecting their VIN pins together, and
connecting the higher numbered bucks’ FB pin(s) to the
input supply. The lowest numbered buck is always the
master. In Figure 1, buck regulator 1 is the master. The
3375fd
For more information www.linear.com/3375
LTC3375
Operation
feedback network connected to the FB1 pin programs
the output voltage to 1.2V. The FB2 pin is tied to VIN1/2,
which configures buck regulator 2 as the slave. The SW1
and SW2 pins must be tied together, as must the VIN1 and
VIN2 pins. The register contents of the master program,
the combined buck regulator’s behavior, and the register
contents of the slave are ignored. The slave buck control
circuitry draws no current. The enable of the master buck
(EN1) controls the operation of the combined bucks; the
enable of the slave regulator (EN2) must be tied to ground.
The LTC3375 is in an off state when it is powered up with
all regulators in shutdown. The ON pin is LOW in the off
state. The ON pin will go HIGH if PB is pulled LOW for
200ms. The ON pin stays in its HIGH state for 10 seconds
and then returns LOW unless KILL is asserted HIGH in
this time in which case ON will remain HIGH. If KILL goes
LOW, for longer than a 50ms debounce time, while ON is
HIGH after the 10 second time has expired, ON will again
go to its LOW state. PB being held low causes the KILL
pin to be ignored.
Any combination of 2, 3, or 4 adjacent buck regulators
may be combined to provide either 2A, 3A, or 4A of average output load current. For example, buck regulator 1
and buck regulator 2 may run independently, while buck
regulators 3 and 4 may be combined to provide 2A, while
buck regulators 5 through 8 may be combined to provide
4A. Buck regulator 1 is never a slave, and buck regulator 8
is never a master. 15 unique output power stage configurations are possible to maximize application flexibility.
Once in the “on” state (ON pin is HIGH), the LTC3375
can be powered down in one of three ways that allow for
flexibility between hardware and software system resets.
First, if PB is held LOW for at least 10 seconds, then ON
will be driven LOW. This will not force a hard reset on any
of the buck switching regulators. The ON pin, however, may
be used to either drive the EN pin of the first sequenced
buck converter or that of an upstream high voltage buck
switching regulator. In this case the IRQ pin is latched to
its LOW state to indicate a PB induced reset. Second, if
the PB pin is driven LOW for longer than 50ms but less
than 10 seconds, the IRQ pin will be pulled LOW for as
long as the PB pin remains LOW. If a microcontroller sees
a transient IRQ LOW signal, then this should signal that
the user has pressed the PB. A software power-down may
then be initiated if so desired. Finally, if the KILL input is
driven LOW for longer than 50ms, then a hard reset will
be initiated. All enabled buck switching regulators will
be turned off while KILL is low and will remain powered
down for 1 second after KILL returns high. KILL being
low also forces a hard reset while the pushbutton is in the
“off” state. A hard reset may also be generated by using
the RESET_ALL I2C command that will last for 1 second.
The pushbutton will return to the “off” state. KILL must be
high to power-up using EN pins or I2C. In any hard reset
event all buck regulator I2C bits are set low.
VIN
L1
VIN1
SW1
COUT
BUCK REGULATOR 1
(MASTER)
EN1
VOUT
1.2V
2A
475k
FB1
725k
VIN2
SW2
BUCK REGULATOR 2
(SLAVE)
EN2
FB2
VIN
3375 F01
Figure 1. Buck Regulators Configured as Master-Slave
Pushbutton Interface
The LTC3375 includes a pushbutton interface which can
be used to provide power-up or power-down control for
either the part or the application. The PB, KILL, and ON pins
provide the user with flexibility to power-up or power-down
the part in addition to having I2C control. All PB timing
parameters are scaled using the CT pin. Times described
below apply to a nominal CT capacitor of 0.01µF.
Power-Up and Power-Down Via Pushbutton
The LTC3375 may be turned on and off using the PB,
KILL, and ON pins as shown in Figures 2a and 2b. In
Figures 2a and 2b, pressing PB LOW at time t1, causes
the ON pin to go HIGH at time t2 and stay HIGH for at least
10 seconds after which ON will go LOW unless KILL has
been asserted high. ON can be connected to the EN pin
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17
LTC3375
Operation
t PB_ON
PB
ON
(TIED TO EN1)
tKILLH
KILL = 0
SEQUENCE UP
SEQUENCE DOWN
BUCK1-BUCK8
3375 F02a
HARD RESET
t 1 t2
t3 KILL NOT ASSERTED
BEFORE t3
Figure 2a. Power-Up Using PB (Sequenced Power-Up, Figure 8)
t PB_ON
t PB_OFF
PB
ON
(TIED TO EN1)
t KILLH
KILL
DON’T CARE
BUCK1-BUCK8
SEQUENCE DOWN
SEQUENCE UP
IRQ
HARD RESET
3375 F02b
t1 t2
t3
t4
t5
Figure 2b. Power-Up and Power-Down Using PB (Sequenced Power-Up, Figure 8)
t PB_ON
t KILL
PB
ON
(TIED TO EN1)
t KILLH
KILL
DON’T CARE
SEQUENCE UP
BUCK1-BUCK8
IRQ
HARD RESET
3375 F02c
t1 t2
t3
Figure 2c. Power-Up Using PB and Power-Down Using KILL
18
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t4 t5
3375fd
LTC3375
Operation
t PB_ON
<10 SEC
PB
ON
(TIED TO EN1)
t HR
KILL
BUCK1-BUCK8
SEQUENCE
DOWN
SEQUENCE UP
t PB_LO
IRQ
t KILLLO
HARD RESET
t 1 t2
t3
t4
t5
t6
t7 t8
t9
3375 F02d
Figure 2d. Power-Up Using PB and Power-Down Using a “Soft” Reset
of either an upstream high voltage buck regulator, or any
EN pin causing its associated buck switching regulator
to power-up, which can sequentially power-up the other
buck regulators. The RST pin gets pulled HIGH 230ms
after the last enabled buck is in its PGOOD state. An
application showing sequential regulator start-up is shown
in the Typical Applications section (Figure 8).
In Figure 2b, PB is held LOW at instant t4 for 10 seconds.
This causes ON to return to a LOW state, which can sequence a power-down by either shutting down an upstream
high voltage buck, or by shutting down one of the internal
buck switching regulators.
In Figure 2c, KILL is pulled LOW while the pushbutton is in
the “on” state. This causes a hard reset to be generated at
t4, all regulators are powered down 50ms later at time t5.
An I2C signaled reset will have the same effect as pulling
KILL low momentarily.
In Figure 2d, PB is held LOW at instant t4 for a time
greater than 50ms but less than 10 seconds. This causes
a transient IRQ signal. This unlatched interrupt can be
used to signal a user pushbutton request. In this case a
software reset may be initiated if so desired. In Figure 2d,
the microprocessor initiates the power-down sequencing after the user pushbutton signal at time t6. At time
t7, once all the converters are powered down, the micro
brings KILL LOW. 50ms later at time t8 ON goes LOW. In
this case, a hard reset is issued until 1 second after KILL
returns high at t9.
None of the pushbutton based IRQ signals are reported
in an I2C register. As such, any IRQ signals that are not
revealed by polling the I2C read back may be interpreted
as caused by the pushbutton.
Power-Up and Power-Down Via Enable Pin or I2C
All regulators can be enabled either via its enable pin or
I2C. If the use of the pushbutton interface is not desired PB
and KILL should be tied to VCC, and the user may simply
enable any of the buck switching regulators by asserting
a HIGH signal on any of the EN pins or by writing a buck
switching regulator EN command to the I2C. If no I2C enable has been written, the buck switching regulator may
be powered down by simply returning its EN pin to a LOW
state. If it is wished to power-down the converters via I2C,
an IGNORE_EN command may be written causing the
LTC3375 to treat the state of the EN pin as LOW regardless of its input. Then, the buck switching converters can
be powered down via I2C regardless of their associated
EN pin. Alternatively a RESET_ALL command may be
written that will force all the buck switching regulators to
power-down and remain powered down for a minimum
of one second before they are allowed to be re-enabled.
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19
LTC3375
Operation
ADDRESS
DATA BYTE A
WR
A7
0
1
1
0
1
0
0
0
SDA
0
1
1
0
1
0
0
0
ACK
SCL
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
DATA BYTE B
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
START
STOP
ACK
1
2
3
4
5
6
7
8
9
ACK
1
2
3
4
5
6
7
8
9
SDA
tSU, DAT
tLOW
tSU, STA
tHD, DAT
tHD, STA
tBUF
tSU, STO
3375 F03
SCL
tHIGH
tHD, STA
START
CONDITION
tr
tSP
tf
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 3. I2C Bus Operation
I2C Interface
The LTC3375 may communicate with a bus master using the
standard I2C 2-wire interface. The timing diagram (Figure 3)
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC3375 is both a slave receiver and
slave transmitter. The I2C control signals, SDA and SCL
are scaled internally to the VCC supply.
The I2C port has an undervoltage lockout on the VCC pin.
When VCC is below 1.8V, the I2C serial port is cleared and
the LTC3375 registers are set to their default configurations.
I2C Bus Speed
The I2C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct operation when addressed from the I2C compatible
master device.
I2C Start and Stop Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3375, the master may transmit a STOP condition which
20
commands the LTC3375 to act upon its new command
set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus
is then free for communication with another I2C device.
I2C Byte Format
Each byte sent to or received from the LTC3375 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3375
most significant bit (MSB) first.
I2C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3375 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC3375 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC3375.
An acknowledge (active LOW) generated by the LTC3375
lets the master know that the latest byte of information was
received. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3375 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.
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LTC3375
Operation
Table 1. Summary of I2C Sub-Addresses and Byte Formats. Bits A7, A6, A5, A4 of Sub-Address Need to be 0 to Access Registers
SUB-ADDRESS
A7A6A5A4A3A2A1A0 OPERATION
ACTION
Global Logic
BYTE FORMAT D7D6D5D4D3D2D1D0
DEFAULT
D7D6D5D4D3D2D1D0 COMMENTS
0000 0000 (00h)
Read/Write
RESET_ALL, DT[1], DT[0], IGNORE_EN, 0000 0000
1KPD, SLOW, RD_TEMP, Unused
0000 0001 (01h)
Read/Write Buck1 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0000 1100
0000 0010 (02h)
Read/Write Buck2 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0000 1100
0000 0011 (03h)
Read/Write Buck3 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0001 1100
0000 0100 (04h)
Read/Write Buck4 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0001 1100
0000 0101 (05h)
Read/Write Buck5 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0010 1100
0000 0110 (06h)
Read/Write Buck6 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0010 1100
0000 0111 (07h)
Read/Write Buck7 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0011 1100
0000 1000 (08h)
Read/Write Buck8 Register ENABLE, MODE, PHASE[1], PHASE[0],
DAC[3], DAC[2]. DAC[1], DAC[0]
0011 1100
0000 1001 (09h)
Read/Write
RST Mask
PGOOD[8], PGOOD[7], PGOOD[6],
PGOOD[5], PGOOD[4], PGOOD[3],
PGOOD[2], PGOOD[1]
1111 1111
Fault will pull RST low if the
corresponding bit is ‘1’
0000 1010 (0Ah)
Read/Write
IRQ PGOOD
Mask
PGOOD[8], PGOOD[7], PGOOD[6],
PGOOD[5], PGOOD[4], PGOOD[3],
PGOOD[2], PGOOD[1]
0000 0000
Fault will pull IRQ low if the
corresponding bit is ‘1’
0000 1011 (0Bh)
Read/Write
IRQ UVLO
Mask
UVLO[8], UVLO[7], UVLO[6], UVLO[5], 0000 0000
UVLO[4], UVLO[3], UVLO[2], UVLO[1]
Fault will pull IRQ low if the
corresponding bit is ‘1’
0000 1100 (0Ch)
Read
0000 1101 (0Dh)
Read
UVLO Status
Register
(Latched at
IRQ fault)
0000 1110 (0Eh)
Read
Temp Monitor DT_WARN, TEMP[6], TEMP[5],
TEMP[4], TEMP[3], TEMP[2], TEMP[1],
TEMP[0]
0000 1111 (0Fh)
Write
Clear Interrupt
PGOOD Status PGOOD[8], PGOOD[7], PGOOD[6],
Register
PGOOD[5], PGOOD[4], PGOOD[3],
(Latched at PGOOD[2], PGOOD[1]
IRQ fault)
Read back of PGOOD based
faults. If the corresponding mask
bit is ‘0’, then bit can be used to
read back real time data
UVLO[8], UVLO[7], UVLO[6], UVLO[5],
UVLO[4], UVLO[3], UVLO[2], UVLO[1]
Read back of UVLO based faults.
If the corresponding mask bit is
‘0’, then bit can be used to read
back real time data
TEMP bits read back the TEMP
digital code. DT_WARN bit
latches high if an IRQ fault has
been caused due to a DT Warning
NA
When the LTC3375 is read from, it releases the SDA line
so that the master may acknowledge receipt of the data.
Since the LTC3375 only transmits one byte of data during
a read cycle, a master not acknowledging the data sent
by the LTC3375 has no I2C specific consequence on the
operation of the I2C port.
Bits either act at top level or on all
buck switching regulators at once
Clears the Interrupt Bit, Status
Latches are Unlatched
I2C Slave Address
The LTC3375 responds to a 7-bit address which has been
factory programmed to b’0110100[R/WB]’. The LSB of
the address byte, known as the read/write bit, should
be 0 when writing to the LTC3375 and 1 when reading
data from it. Considering the address as an 8-bit word,
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21
LTC3375
Operation
the write address is 68h and the read address is 69h. The
LTC3375 will acknowledge both its read and write address.
signal is issued is the data transferred to the command
latch and acted on.
I2C Sub-Addressed Writing
I2C Bus Read Operation
The LTC3375 has 13 command registers for control input.
They are accessed by the I2C port via a sub-addressed
writing system.
The LTC3375 has 13 command registers and three status
registers. The contents of any of these registers, except for
the Clear Interrupt (0Fh) register, may be read back via I2C.
A single write cycle of the LTC3375 consists of exactly three
bytes except when a clear interrupt command is written.
The first byte is always the LTC3375’s write address. The
second byte represents the LTC3375’s sub-address. The
sub-address is a pointer which directs the subsequent
data byte within the LTC3375. The third byte consists of
the data to be written to the location pointed to by the
sub-address. The LTC3375 contains 12 control registers
which can be written to.
To read the data of a register, that register’s sub-address
must be provided to the LTC3375. The bus master reads
the status of the LTC3375 with a START condition followed
by the LTC3375 write address followed by the first data
byte (the sub-address of the register whose data needs
to be read) which is acknowledged by the LTC3375. After
receiving the acknowledge signal from the LTC3375 the
bus master initiates a new START condition followed by
the LTC3375 read address. The LTC3375 acknowledges
the read address and then returns a byte of read back
data from the selected register. A STOP command is not
required for the bus read operation.
I2C Bus Write Operation
The master initiates communication with the LTC3375
with a START condition and the LTC3375’s write address.
If the address matches that of the LTC3375, the LTC3375
returns an acknowledge. The master should then deliver
the sub-address. Again the LTC3375 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of
its acknowledge by the LTC3375. This procedure must be
repeated for each sub-address that requires new data.
After one or more cycles of [ADDRESS][SUB-ADDRESS]
[DATA], the master may terminate the communication
with a STOP condition. Multiple sub-addresses may
be written to with a single address command using a
[ADDRESS][SUB-ADDRESS][DATA][SUB-ADDRESS]
[DATA] sequence. Alternatively, a REPEAT-START condition can be initiated by the master and another chip on
the I2C bus can be addressed. This cycle can continue
indefinitely and the LTC3375 will remember the last input
valid data that it received. Once all chips on the bus have
been addressed and sent valid data, a global STOP can
be sent and the LTC3375 will update its command latches
with the data that it had received.
It is important to understand that until a STOP signal is
transmitted, data written to the LTC3375 command registers is not acted on by the LTC3375. Only once a STOP
22
Immediately after writing data to a register, the contents
of that register may be read back if the bus master issues
a START condition followed by the LTC3375 read address.
Error Condition Reporting Via RST and IRQ Pins
Error conditions are reported back via the IRQ and RST
pins. After an error condition is detected, status data can
be read back to a microprocessor via I2C to determine the
exact nature of the error condition.
Figure 4 is a simplified schematic showing the signal path
for reporting errors via the RST and IRQ pins.
All buck switching regulators have an internal power good
(PGOOD) signal. When the regulated output voltage of an
enabled switcher rises above 93.5% of its programmed
value, the PGOOD signal will transition high. When the
regulated output voltage falls below 92.5% of its programmed value, the PGOOD signal is pulled low. If any
internal PGOOD signal is not masked and stays low for
greater than 50µs, then the RST and IRQ pins are pulled
low, indicating to a microprocessor that an error condition
has occurred. The 50µs filter time prevents the pins from
being pulled low due to a transient.
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LTC3375
Operation
RST MASK REGISTER
VCC
EXTERNAL PULL-UP RESISTOR
AND1
REGULATOR
92.5% OF PROGRAMMED VOUT
–
+
RST
OTHER UNMASKED
PGOOD OUTPUTS
VOUT
PGOOD
COMPARATOR
AND2
UNMASKED
PGOOD OUTPUTS
VCC
EXTERNAL PULL-UP RESISTOR
UNMASKED
ERROR
OTHER UNMASKED
ERRORS
IRQ
SET
CLRINT
CLR
IRQ STATUS REGISTER
IRQ MASK REGISTER
3375 F04
Figure 4. Simplified Schematic RST and IRQ Signal Path
An error condition that pulls the RST pin low is not latched.
When the error condition goes away, the RST pin is released and is pulled high if no other error condition exists.
In addition to the PGOOD signals of the regulators the
IRQ pin also indicates the status of the pushbutton, die
temperature, and undervoltage flags. Pushbutton faults
cannot be masked. A fault that causes the IRQ pin to be
pulled low is latched with the exception of a pushbutton
press that is less than 10 seconds (CT = 0.01µF) while ON is
HIGH. In the case of a transient pushbutton press IRQ will
be held LOW for the duration of the button press latching
after the 10 second power-down time has elapsed. In all
other cases when the fault condition is cleared, the IRQ
pin is still maintained in its low state. The user needs to
clear the interrupt by using a CLRINT command.
On start-up, all PGOOD status outputs are unmasked with
respect to RST. While all PGOOD and UVLO status outputs
are masked with respect to IRQ. A power-on reset will
cause RST to be pulled low. Once all enabled regulators
have their output PGOOD for 230ms typical (CT = 0.01µF)
the RST output goes Hi-Z.
By masking a PGOOD signal, the RST or IRQ pin will remain
Hi-Z even though the output voltage of a regulator may be
below its PGOOD threshold. By masking a UVLO signal,
the IRQ pin will remain Hi-Z even though its associated
input voltage may be below its UVLO threshold. However,
when the status registers are read back, the true conditions of PGOOD and UVLO are reported. If a UVLO IRQ is
masked but the associated PGOOD signal is unmasked,
then the IRQ pin may still be pulled low due to a PGOOD
LOW signal that resulted from an input UVLO.
Temperature Monitoring and
Overtemperature Protection
To prevent thermal damage to the LTC3375 and its surrounding components, the LTC3375 incorporates an
overtemperature (OT) function. When the LTC3375 die
temperature reaches 165°C (typical) all enabled buck
switching regulators are shut down and remain in shutdown until the die temperature falls to 155°C (typical).
The LTC3375 also has a die temperature warning function
which warns a user that the die temperature has reached
its programmed alarm threshold which allows the user to
take any corrective action. The die temperature warning
threshold is user programmable as shown in Table 2.
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23
LTC3375
Operation
Table 2. Die Temperature Warning Thresholds
DT[1], DT[0]
DIE TEMPERATURE WARNING THRESHOLD
00 (Default)
Inactive
01
140°C
10
125°C
11
110°C
their previous states. The RESET_ALL bit will also reset
the pushbutton to the powered-down state.
Programming the Operating Frequency
A die temperature warning is reported to the user by pulling
the IRQ pin low. This warning can be read back on the LSB
of the Temp_Monitor register. The die temperature warning
flag is disabled when the DT bits are set to 00 (default).
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output voltage ripple.
The temperature may be read back by the user either
digitally through the I2C Temp_Monitor Register or by
sampling the TEMP pin analog voltage. The temperature,
T, indicated by the TEMP pin voltage is given by:
The operating frequency for all of the LTC3375 regulators
is determined by an external resistor that is connected
between the RT pin and ground. The operating frequency
can be calculated by using the following equation:
T=
VTEMP + 19mV
• 1°C
6.75mV
(1)
The analog voltage can be digitally polled using an internal
A/D converter. In order to digitally read the temperature
voltage the user should first issue a RD_TEMP I2C command to tell the A/D converter to poll the TEMP voltage.
At least 2ms after this command has been written the user
may then poll the TEMP bits in the Temp_Monitor register.
The TEMP bits are related to the TEMP voltage as follows:
VTEMP = 1.3V • (0.08333 + 0.007161 • D)
(2)
where D corresponds to the bit weight of the digital code.
Combining Equation 1 and Equation 2 yields:
T = 18.86°C + 1.379°C • D
(3)
If none of the buck switching regulators are enabled, then
the temperature monitor is shut down to further reduce
quiescent current.
RESET_ALL Functionality
The RESET_ALL bit shuts down all enabled regulators
(enabled either via its enable pin or I2C) for one second.
The RESET_ALL bit is self clearing, and all other I2C bits
(besides the enable bits, which are set low) will remain in
24
fOSC =
8 • 1011 • ΩHz
RT
(4)
While the LTC3375 is designed to function with operating frequencies between 1MHz and 3MHz, it has safety
clamps that will prevent the oscillator from running faster
than 4MHz (typical) or slower than 250kHz (typical). Tying
the RT pin to VCC sets the oscillator to the default internal
operating frequency of 2MHz (typical).
The LTC3375’s internal oscillator can be synchronized,
through an internal PLL circuit, to an external frequency
by applying a square wave clock signal to the SYNC pin.
During synchronization, the top MOSFET turn-on of any
buck switching regulators operating at 0° phase are locked
to the rising edge of the external frequency source. All
other buck switching regulators are locked to the appropriate phase of the external frequency source (see Buck
Switching Regulators). The synchronization frequency
range is 1MHz to 3MHz.
After detecting an external clock on the first rising edge of
the SYNC pin, the PLL starts up at the current frequency
being programmed by the RT pin. The internal PLL then
requires a certain number of periods to gradually settle
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LTC3375
Operation
until the frequency at SW matches the frequency and
phase of SYNC.
When the external clock is removed the LTC3375 needs
approximately 5µs to detect the absence of the external
clock. During this time, the PLL will continue to provide
clock cycles before it recognizes the lack of a SYNC input.
Once the external clock removal has been identified, the
oscillator will gradually adjust its operating frequency to
match the desired frequency programmed at the RT pin.
VCC Shunt Regulator
The LTC3375 has the control circuitry to regulate the output
of an N-type device. The circuit should be connected as
shown in Figures 6a and 6b. The voltage at FBVCC will servo
to 1.20V and VCC can be programmed between 2.7V and
5.5V. The N-type device can be used to regulate a lower
voltage at VCC while being powered from a high voltage
supply. The N-type device must be chosen so that it can
handle the power dissipated in regulating VCC. The internal
circuitry of the LTC3375 can only pull-down on the VSHNT
node. A pull-up resistor is required for positive gate drive.
If VCC is incorrectly programmed or a current load at VCC
causes VSHNT to go above 6.1V (typical), then VSHNT will
be internally clamped and VCC may lose regulation.
If the use of the VCC regulator is not desired, then VCC
should be tied to an external DC voltage source and a
decoupling capacitor. FBVCC and VSHNT should be tied
to ground.
Watchdog Timer
The watchdog circuit monitors a microprocessor’s activity.
The microprocessor is required to change the logic state
of the WDI pin at least once every 1.5 seconds (typical)
in order to clear the watchdog timer and prevent the WDO
pin from signaling a timeout.
The watchdog timer begins running immediately after a
power-on reset. The watchdog timer will continue to run
until a transition is detected on the WDI input. During this
time WDO will be in a Hi-Z state. Once the watchdog timer
times out, WDO will be pulled low and the reset timer is
started. WDO being pulled low may be used to force a reset
on the controlling microprocessor. If no WDI transition
is received when the reset timer times out, after 200ms
(typical), WDO will again become Hi-Z and the 1.5 seconds
watchdog reset time will begin again. If a transition is
received on the WDI input during the watchdog timeout
period, then WDO will become Hi-Z immediately after the
WDI transition and the 1.5 seconds watchdog reset time
will begin at that point.
3375fd
For more information www.linear.com/3375
25
LTC3375
Applications Information
Buck Switching Regulator Output Voltage and
Feedback Network
The output voltage of the buck switching regulators is
programmed by a resistor divider connected from the
switching regulator’s output to its feedback pin and is
given by VOUT = VFB(1 + R2/R1) as shown in Figure 5.
Typical values for R1 range from 40k to 1M. The buck
regulator transient response may improve with optional
capacitor CFF that helps cancel the pole created by the
feedback resistors and the input capacitance of the FB
pin. Experimentation with capacitor values between 2pF
and 22pF may improve transient response.
VOUT
BUCK
SWITCHING
REGULATOR
CFF
R2
FB
+
The input supply needs to be decoupled with a 10µF
capacitor while the output needs to be decoupled with a
22µF capacitor. Refer to Capacitor Selection for details on
selecting a proper capacitor.
Each buck regulator can be programmed via I2C. To program
buck regulator 1 use sub-address 01h, buck regulator 2
sub-address 02h, buck regulator 3 sub-address 03h, buck
regulator 4 sub address 04h, buck regulator 5 sub-address
05h, buck regulator 6 sub-address 06h, buck regulator 7
sub-address 07h, and buck regulator 8 sub-address 08h.
The bit format is explained in Table 7.
Combined Buck Regulators
A single 2A buck regulator is available by combining two
adjacent 1A buck regulators together. Likewise a 3A or 4A
buck regulator is available by combining any three or four
adjacent buck regulators respectively. Tables 4, 5, and 6
show recommended inductors for these configurations.
COUT
(OPTIONAL)
R1
3375 F05
Figure 5. Feedback Components
Buck Regulators
All eight buck regulators are designed to be used with
inductors ranging from 1µH to 3.3µH depending on the
lowest switching frequency that the buck regulator must
operate at. To operate at 1MHz a 3.3µH inductor should
be used, while to operate at 3MHz a 1µH inductor may be
used. Table 3 shows some recommended inductors for
the buck regulators.
The input supply needs to be decoupled with a 22µF capacitor while the output needs to be decoupled with a 47µF
capacitor for a 2A combined buck regulator. Likewise for
3A and 4A configurations the input and output capacitance
must be scaled up to account for the increased load. Refer
to Capacitor Selection in the Applications Information section for details on selecting a proper capacitor.
In many cases, any extra unused buck converters may be
used to increase the efficiency of the active regulators.
In general the efficiency will improve for any regulators
running close to their rated load currents. If there are
unused regulators, the user should look at their specific
applications and current requirements to decide whether
to add extra stages.
Table 3. Recommended Inductors for 1A Buck Regulators
PART NUMBER
L (µH)
MAX IDC (A)
MAX DCR (MΩ)
SIZE IN mm (L × W × H)
1.0
3
38
3 × 3.6 × 1.2
1239AS-H-1R0N
1
2.5
65
2.5 × 2.0 × 1.2
XFL4020-222ME
2.2
3.5
23.5
4 × 4 × 2.1
1277AS-H-2R2N
2.2
2.6
84
3.2 × 2.5 × 1.2
IHLP1212BZER2R2M-11
2.2
3
46
3 × 3.6 × 1.2
XFL4020-332ME
3.3
2.8
38.3
4 × 4 × 2.1
IHLP1212BZER3R3M-11
3.3
2.7
61
3 × 3.6 × 1.2
IHLP1212ABER1R0M-11
26
MANUFACTURER
Vishay
Toko
Coilcraft
Toko
Vishay
Coilcraft
Vishay
3375fd
For more information www.linear.com/3375
LTC3375
Applications Information
Table 4. Recommended Inductors for 2A Buck Regulators
PART NUMBER
L (µH)
MAX IDC (A)
MAX DCR (mΩ)
SIZE IN mm (L × W × H)
XFL4020-102ME
1.0
5.1
11.9
4 × 4 × 2.1
74437324010
1
5
27
4.45 × 4.06 × 1.8
XAL4020-222ME
2.2
5.6
38.7
4 × 4 × 2.1
FDV0530-2R2M
2.2
5.3
15.5
6.2 × 5.8 × 3
IHLP2020BZER2R2M-11
2.2
5
37.7
5.49 × 5.18 × 2
XAL4030-332ME
3.3
5.5
28.6
4 × 4 × 3.1
FDV0530-3R3M
3.3
4.1
34.1
6.2 × 5.8 × 3
MANUFACTURER
Coilcraft
Würth Elektronik
Coilcraft
Toko
Vishay
Coilcraft
Toko
Table 5. Recommended Inductors for 3A Buck Regulators
PART NUMBER
L (µH)
MAX IDC (A)
MAX DCR (mΩ)
SIZE IN mm (L × W × H)
MANUFACTURER
XAL4020-102ME
1.0
8.7
14.6
4 × 4 × 2.1
FDV0530-1R0M
1
8.4
11.2
6.2 × 5.8 × 3
XAL5030-222ME
2.2
9.2
14.5
5.28 × 5.48 × 3.1
IHLP2525CZER2R2M-01
2.2
8
20
6.86 × 6.47 × 3
Vishay
74437346022
2.2
6.5
20
7.3 × 6.6 × 2.8
Würth Elektronik
XAL5030-332ME
3.3
8.7
23.3
5.28 × 5.48 × 3.1
SPM6530T-3R3M
3
7.3
27
7.1 × 6.5 × 3
MAX DCR (mΩ)
SIZE IN mm (L × W × H)
Coilcraft
Toko
Coilcraft
Coilcraft
TDK
Table 6. Recommended Inductors for 4A Buck Regulators
PART NUMBER
L (µH)
MAX IDC (A)
1.2
12.5
9.4
5.28 × 5.48 × 3.1
1
14.1
7.81
7.1 × 6.5 × 3
XAL5030-222ME
2.2
9.2
14.5
5.28 × 5.48 × 3.1
SPM6530T-2R2M
2.2
8.4
19
7.1 × 6.5 × 3
IHLP2525EZER2R2M-01
2.2
13.6
20.9
6.86 × 6.47 × 5
XAL6030-332ME
3.3
8
20.81
6.36 × 6.56 × 3.1
FDVE1040-3R3M
3.3
9.8
10.1
11.2 × 10 × 4
XAL5030-122ME
SPM6530T-1R0M120
MANUFACTURER
Coilcraft
TDK
Coilcraft
TDK
Vishay
Coilcraft
Toko
Table 7. Global Buck Regulator Program Register Bit Format
Bit7
ENABLE
Default is ‘0’ which disables the part. A buck regulator can also be enabled via its enable pin. When enabled via
pin, the contents of the I2C register program its functionality.
Bit6
MODE
Default is ‘0’ which is Burst Mode operation. A ‘1’ programs the regulator to operate in forced continuous mode.
Bit5(PHASE1)
Bit4(PHASE0)
Phase Control
Default varies per converter. ‘00’ programs a SW HIGH transition to coincide with the internal clock rising edge.
‘01’ programs a 90° offset, ’10’ programs a 180° offset, and ‘11’ programs a 270° offset.
Bit3(DAC3)
Bit2(DAC2)
Bit1(DAC1)
Bit0(DAC0)
DAC Control
These bits are used to program the feedback regulation voltage. Default is ‘1100’ which programs a voltage of
725mV. Bits ‘0000’ program the lowest feedback regulation of 425mV, and ‘1111’ programs a full-scale voltage
of 800mV. An LSB (DAC0) has a bit weight of 25mV.
3375fd
For more information www.linear.com/3375
27
LTC3375
Applications Information
VCC Shunt Regulator
If load steps seen on VCC are of great concern, then the
compensation capacitor should be tied from VCC to ground
as shown in Figure 6a. If load steps are not of a concern,
but instead smaller compensation components are desired
then the compensation capacitor should be tied from VSHNT
to ground as shown in Figure 6b.
301k
VSHNT
VCC
1Ω
1.02M
FBVCC
22µF
576k
1.2V
+
–
3375 F06a
Figure 6a. VCC Regulator Compensated from the VCC Pin
301k
VSHNT
VCC
576k
1.2V
+
–
VCC REGULATOR
3375 F06b
Figure 6b. VCC Regulator Compensated from the VSHNT Pin
The exact components used in the VCC shunt regulator are
dependent on the specific conditions used in the application. Care should be taken to make sure that the power
dissipation limits of the specific N-type device used are
not exceeded, because damage to the external device can
lead to damage to the LTC3375.
28
VSUPPLY(MINIMUM) −(VCC + VBE )
•β
IVCC(MAX)
Where VSUPPLY(MINIMUM) is the lowest possible collector
voltage, VBE and β are specific to the NPN in the application, and IVCC(MAX) is the maximum desired load current
from VCC.
Likewise RPULLUP may be sized such to current limit IVCC
from an NPN device to prevent damage to the circuit
from a short on the VCC pin, and to prevent the NPN from
exceeding its safe operating current:
VSUPPLY(MAXIMUM) −(VCC + VBE )
•β
IVCC(LIMIT)
Where VCC = 0V in the case of a grounded output.
Alternatively, the current may be limited by adding a resistor between VCC and the emitter of the NPN such that:
RLIM =
1.02M
FBVCC
RPULLUP <
RPULLUP >
VCC REGULATOR
2.2µF
For an NPN device the pull-up resistor between VSHNT and
the supply voltage should be sized such that:
6.1V −(VCC + VBE )
IVCC(LIMIT)
In this case when IVCC exceeds IVCC(LIMIT) VCC will start to
collapse. The NPN should be sized to be able to survive
at least:
IVCC(MAX) =
6.1V − VBE
RLIM
for the given supply voltage, where 6.1V is the maximum
VSHNT voltage (typical).
The user should verify that the circuit is stable over the
specific conditions of the desired application. In general
increasing the value of the compensation capacitor used or
increasing RPULLUP can improve stability. The user should
keep in mind that increasing RPULLUP also decreases
IVCC(MAX). In general the highest VSUPPLY at IVCC(MAX)
yields the worst stability for the circuit in Figure 6a, while
the highest VSUPPLY at no load on VCC yields the worst
stability for the circuit in Figure 6b.
3375fd
For more information www.linear.com/3375
LTC3375
Applications Information
In general the circuit in 6a is recommended if the application needs to drive any external circuitry with VCC or if
the larger compensation capacitor is tolerable. If VCC is
only needed to drive the LTC3375 and smaller component
sizes are critical, then the circuit in Figure 6b may be used.
Programming the Global Register
Input and Output Decoupling Capacitor Selection
Programming the RST and IRQ Mask Registers
The LTC3375 has individual input supply pins for each buck
switching regulator. Each of these pins must be decoupled
with low ESR capacitors to GND. These capacitors must be
placed as close to the pins as possible. Ceramic dielectric
capacitors are a good compromise between high dielectric
constant and stability versus temperature and DC bias.
Note that the capacitance of a capacitor deteriorates at
higher DC bias. It is important to consult manufacturer
data sheets and obtain the true capacitance of a capacitor
at the DC bias voltage it will be operated at. For this reason, avoid the use of Y5V dielectric capacitors. The X5R/
X7R dielectric capacitors offer good overall performance.
The input supply voltage Pins 2, 5, 8, 11, 26, 29, 32 and
35 all need to be decoupled with at least 10µF capacitors.
Choosing the CT Capacitor
The CT capacitor may be used to program the timing
parameters associated with the pushbutton. For a given
CT capacitor the timing parameters may be calculated as
below. CT is in units of µF.
tPB_LO = 5000 • CT ms
tPB_ON = 20000 • CT ms
tPB_OFF = 1000 • CT seconds
tHR = 100 • CT seconds
tIRQ_PW = 5000 • CT ms
tKILLH = 1000 • CT seconds
tKILLL = 5000 • CT ms
tRST = 23000 • CT ms
The Global Register contains functions that either act on
the LTC3375 top level or act on all buck switching regulators at once. These functions are described in Table 8. The
default structure is ‘0000 0000b’.
The RST mask register can be programmed by the user
at sub-address 09h and its format is shown in Table 9.
If a bit is set to ‘1’, then the corresponding regulator’s
PGOOD will pull RST low if a PGOOD fault were to occur.
The default for this register is FFh.
The IRQ mask registers have the same bit format as the
RST mask register. The IRQ mask registers are located
at sub-addresses 0Ah and 0Bh and their default contents
are 00h.
Status Byte Read Back
When either the RST or IRQ pin is pulled low, it indicates
to the user that a fault condition has occurred. To find out
the exact nature of the fault, the user can read the status
registers. There are three registers that contain status
information. The register at sub-address 0Ch provides
PGOOD fault condition reporting, while the register at
sub-address 0Dh provides UVLO fault condition reporting.
These bits are all latched at interrupt. If any of the bits
are disabled via masking, then their real time, unlatched
status information is still available. Bit7 of the register
at sub-address 0Eh provides latched information on the
status of the DT Warning. Figure 4 shows the operation
of the status registers. The contents of the IRQ status
register are cleared when a CLRINT signal is issued. A
PGOOD bit is a ‘0’ if the regulator’s output voltage is more
than 7.5% below its programmed value. A UVLO bit is a
‘0’ if the associated VIN is above its input UVLO threshold.
The format for the status registers is shown in Table 10.
A write operation cannot be performed to any of these
status registers.
3375fd
For more information www.linear.com/3375
29
LTC3375
Applications Information
Table 8. Global Control Program Register Bit Format
Bit7
RESET_ALL
Default is ‘0’. When asserted all buck converters will power down for 1 second after which the bit will clear itself.
Bit6(DT1)
Bit5(DT0)
DT WARNING
CONTROL
Default is ‘00’ which deactivates the DT warning. ‘01’ programs –140°, ‘10’ programs –125°,
and ‘11’ programs –110°.
Bit4
IGNORE_EN
Default is ‘0’ which allows the EN pins to power on the buck converters. When written to ‘1’ the enable pins will be
ignored. This allows power-down sequencing via I2C even if the EN pins are tied to a logic HIGH voltage source.
Bit3
1KPD
Default is ‘0’ in which the SW node remains in a high impedance state when the regulator is in shutdown. A ‘1’ pulls
the SW node to GND through a 1k resistor. This bit acts on all buck converters at once.
Bit2
SLOW EDGE
This bit controls the slew rate of the switch node. Default is ‘0’ which enables the switch node to slew at a faster
rate, than if the bit were programmed a ‘1’. This bit acts on all buck converters at once.
Bit1
RD_TEMP
Default is ‘0’. This bit commands the temperature A/D to sample the voltage present at the TEMP pin. After a read is
complete this bit will clear itself.
Bit0
Unused
This bit is unused and must be written to “0”
Table 9
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
PGOOD[8]
PGOOD[7]
PGOOD[6]
PGOOD[5]
PGOOD[4]
PGOOD[3]
PGOOD[2]
PGOOD[1]
Table 10
SubAddress
0Ch
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
PGOOD[8] PGOOD[7] PGOOD[6] PGOOD[5] PGOOD[4] PGOOD[3] PGOOD[2]
BIT0
PGOOD[1]
0Dh
UVLO[8]
UVLO[7]
UVLO[6]
UVLO[5]
UVLO[4]
UVLO[3]
UVLO[2]
UVLO[1]
0Eh
DT_WARN
TEMP[6]
TEMP[5]
TEMP[4]
TEMP[3]
TEMP[2]
TEMP[1]
TEMP[0]
PCB Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3375:
1. The exposed pad of the package (Pin 49) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. All the input supply pins should each have a decoupling
capacitor.
3. The connections to the switching regulator input supply
pins and their respective decoupling capacitors should
be kept as short as possible. The GND side of these
capacitors should connect directly to the ground plane
of the part. These capacitors provide the AC current
to the internal power MOSFETs and their drivers. It is
important to minimize inductance from these capacitors
to the VIN pins of the LTC3375.
30
4. The switching power traces connecting SW1, SW2,
SW3, SW4, SW5, SW6, SW7 and SW8 to their respective inductors should be minimized to reduce radiated
EMI and parasitic coupling. Due to the large voltage
swing of the switching nodes, high input impedance
sensitive nodes, such as the feedback nodes, should
be kept far away or shielded from the switching nodes
or poor performance could result.
5. The GND side of the switching regulator output capacitors should connect directly to the thermal ground plane
of the part. Minimize the trace length from the output
capacitor to the inductor(s)/pin(s).
6. In a combined buck regulator application the trace length
of switch nodes to the inductor must be kept equal to
ensure proper operation.
3375fd
For more information www.linear.com/3375
LTC3375
Typical Applications
3.3V TO 5.5V
2.2µH
10µF 3.3V
1A
22µF
VIN1
VIN8
SW1
SW8
FB1
FB8
1.02M
649k
287k
3V TO 5.5V
10µF
22µF
22µF
1.8V
1A
10µF
1.5V
1A
10µF
1.2V
1A
10µF
1V
1A
10µF
432k
2.2µH
3V
1A
2.25V TO 5.5V
2.2µH
VIN2
VIN7
SW2
SW7
FB2
FB7
2.25V TO 5.5V
2.2µH
1.07M
464k
340k
22µF
432k
LTC3375
2.5V TO 5.5V
2.2µH
10µF 2.5V
1A
22µF
VIN3
VIN6
SW3
SW6
FB3
FB6
1.02M
422k
412k
2.25V TO 5.5V
10µF
22µF
VIN4
VIN5
SW4
SW5
2.25V TO 5.5V
2.2µH
732k
280k
FB4
22µF
FB5
412k
VCC
22µF
649k
2.2µH
2V
1A
2.25V TO 5.5V
2.2µH
732k
1µF
I2C
CONTROL
SCL
SDA
HIGH VOLTAGE > 4.0V
301k
WDI
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
KILL
SYNC
RT
MICROPROCESSOR
CONTROL
VSHNT
2.2µF
VCC
1.02M
FBVCC
576k
402k
IRQ
RST
WDO
ON
TEMP
CT
0.01µF
PUSH BUTTON
PB
MICROPROCESSOR
CONTROL
EXPOSED PAD
3375 F07
Figure 7. Detailed Front Page Application Circuit
3375fd
For more information www.linear.com/3375
31
LTC3375
Typical Applications
VIN
5.5V TO 60V
CIN
22µF
100k
INTVCC
VIN
INTVCC
2.2µF
PGOOD
PLLIN/MODE
ILIM
PGND
D1
TG
470pF
FREQ
34.8k
0.1µF
ITH
2.2µH
1.2V
1A
22µF
L1
8µH
SW
SENSE+
–
TRACK/SS SENSE
EXTVCC
SGND
VFB
2.5V
1A
22µF
5V
6A
100k
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-802KL
COUT: SANYO 10TPE330M
D1: DFLS1100
VIN1
VIN8
SW1
SW8
FB1
FB8
19.1k
10µF
2.2µH
422k
2.2µH
COUT
330µF
1nF
422k
649k
10µF
RSENSE
7mΩ
MBOT
BG
SGND
10µF
MTOP
0.1µF
LTC3891
RUN
BOOST
1.2V
1A
22µF
649k
VIN2
VIN7
SW2
SW7
10µF
2.2µH
1.02M
1.02M
FB2
2.5V
1A
22µF
FB7
412k
412k
LTC3375
10µF
2.2µH
1.8V
1A
22µF
VIN3
VIN6
SW3
SW6
649k
649k
FB3
432k
VIN4
2.2µH
1.6V
1A
22µF
VIN5
SW4
SW5
511k
511k
FB4
422k
HIGH VOLTAGE
5.5V TO 60V
47k
VSHNT
SCL
SDA
FZT6928
215Ω
KILL
SYNC
WDI
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
RT
MICROPROCESSOR
CONTROL
1.6V
1A
22µF
FB5
1µF
I2C
CONTROL
10µF
2.2µH
422k
VCC
1.8V
1A
22µF
FB6
432k
10µF
10µF
2.2µH
VCC
1.02M
FBVCC
576k
3.3V
5mA
1Ω
22µF
402k
IRQ
RST
WDO
TEMP
ON
CT
0.01µF
PUSH BUTTON
PB
MICROPROCESSOR
CONTROL
EXPOSED PAD
3375 F08
Figure 8. Buck Regulators with Sequenced Start-Up Driven from a High Voltage Upstream Buck Converter
32
3375fd
For more information www.linear.com/3375
LTC3375
Typical Applications
2.7V TO 5.5V
10µF
2.5V
4A
2.2µH
100µF
1.02M
VIN1
VIN6
SW1
SW2
SW3
SW4
FB1
SW8
SW7
SW6
2.2µH
422k
68µF
1.2V
3A
10µF
FB6
412k
649k
10µF
VIN2
VIN7
FB2
FB7
10µF
LTC3375
10µF
10µF
VIN3
VIN8
FB3
FB8
VIN4
VIN5
SW5
10µF
2.2µH
511k
FB4
22µF
1.6V
1A
10µF
FB5
422k
1µF
I2C
CONTROL
SCL
SDA
WDI
EN1
EN5
EN6
KILL
SYNC
RT
EN2
EN3
EN4
EN7
EN8
MICROPROCESSOR
CONTROL
VSHNT
VCC
IRQ
RST
WDO
ON
TEMP
CT
0.01µF
PUSH BUTTON
10µF
FBVCC
PB
MICROPROCESSOR
CONTROL
EXPOSED PAD
3375 F09
Figure 9. Combined Buck Regulators with Common Input Supply
3375fd
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33
LTC3375
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
0.70 ±0.05
5.15 ±0.05
5.50 REF
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
5.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
47 48
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.50 REF
(4-SIDES)
5.15 ±0.10
5.15 ±0.10
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
34
For more information www.linear.com/3375
(UK48) QFN 0406 REV C
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
3375fd
LTC3375
Revision History
REV
DATE
DESCRIPTION
A
03/13
Clarified VCC input supply current specification
PAGE NUMBER
Clarified RST pin functionality
Clarified Buck Regulators with Combined Power Stages
B
07/13
C
10/13
D
06/15
4
12
16, 17
Clarified Table 6 Recommended Inductor Ratings
27
Modified SYNC pin description
12
Changed units on VIL specification
5
Modified Bit 3 conditions in Global Control Program Register Bit Format Table
30
Modified Typical Application circuit
1
Added condition to VPGOOD specification
4
Changed typical values of RPMOS and RNMOS specifications
Modified various Typical Performance curves
5
8–11
Modified 2A inductor table
27
Modified Related Parts
36
3375fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
Forofmore
information
www.linear.com/3375
35
LTC3375
Typical Application
Combined Bucks with 3MHz Switch Frequency, Sequenced Power Up, and KILL Based Hardware Override Shut Down
2.25V TO 5.5V
10µF
10µF
VIN1
VIN8
FB8
VIN2
VIN7
3.3V TO 5.5V
10µF
10µF
FB2
VIN3
10µF
1µH
SW7
FB3
SW8
1µH
1.8V
3A
68µF
SW1
SW2
SW3
649k
22µF
2.5V TO 5.5V
VIN6
FB6
10µF
VIN5
LTC3375
VIN4
1µH
1.2V
1A
10µF
1µH
SW5
SW4
SW6
422k
FB4
1.02M
HIGH VOLTAGE >4.0V
301k
VSHNT
SDA
SCL
WDI
EN1
EN4
EN5
EN7
EN2
EN3
EN6
EN8
1.02M
FBVCC
576k
IRQ
RST
WDO
TEMP
SYNC
ON
267k
CT
MICROPROCESSOR
CONTROL
KILL
PB
PUSH BUTTON
2.2µF
VCC
RT
0.01µF
2.5V
2A
412k
1µF
I2C
CONTROL
47µF
FB5
649k
VCC
3.3V
2A
287k
432k
10µF
47µF
FB7
FB1
2.25V TO 5.5V
1.02M
EXPOSED PAD
PAPER CLIP HOLE
PUSH BUTTON
3375 TA02
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTC3374
8-Channel Synchronous Buck, Programmable
Configurable 1A DC/DC
Can Connect Up to Four Power Stages in Parallel to Make a Single Inductor,
Output (4A Max), 15 Output Configurations Possible,
38-Lead (5mm × 7mm × 0.75mm) QFN and TSSOP Packages
LTC3370,
LTC3371
4-Channel Synchronous Buck, Configurable DC/DC 8 × 1A Power Stages. Can Connect Up to Four Power Stages in Parallel to Make a
with 8 × 1A Power Stages
Single Inductor, Output (4A Max), 8 Output Configurations Possible, 32-Lead or
38-Lead (5mm × 7mm × 0.75mm) QFN and TSSOP Packages
LTC3675
7-Channel Configurable High Power PMIC
Four Parallelable Buck DC/DCs (1A, 1A, 500mA, 500mA), 1A Boost, 1A Buck-Boost,
25mA LDO, Dual String LED Driver, Pushbutton, I2C Control
LTC3589/
LTC3589-1
8-Output Regulator with Sequencing and I2C
Three Buck DC/DCs, Three 250mA LDOs, 25mA LDO, 1.2A Buck-Boost,
Pushbutton, I2C Control
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/3375
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear.com/3375
3375fd
LT 0615 REV D • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013