[ /Title (CD74 HC365 , CD74 HCT36 5, CD74 HC366 , CD74 HCT36 6) /Subject (High Speed CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Data sheet acquired from Harris Semiconductor SCHS180 November 1997 High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting Features Description • Buffered Inputs The Harris CD74HC365, CD74HCT365, CD74HC366, and CD74HCT366 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. • High Current Bus Driver Outputs • Typical Propagation Delay tPLH, tPHL = 8ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC The CD74HC365 and CD74HCT365 are non-inverting buffers, whereas the CD74HC366 and CD74HCT366 are inverting buffers. These devices have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates. • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs The CD74HCT365 and CD74HCT366 logic families are speed, function and pin compatible with the standard 74LS logic family. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Ordering Information PART NUMBER • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) PKG. NO. PACKAGE CD74HC365E -55 to 125 16 Ld PDIP E16.3 CD74HCT365E -55 to 125 16 Ld PDIP E16.3 CD74HC366E -55 to 125 16 Ld PDIP E16.3 CD74HC365M -55 to 125 16 Ld SOIC M16.15 CD74HCT365M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 (PDIP, SOIC) TOP VIEW OE1 1 16 VCC 1A 2 15 OE2 14 6A (1Y) 1Y 3 13 6Y (6Y) 2A 4 (2Y) 2Y 5 12 5A 11 5Y (5Y) 3A 6 10 4A (3Y) 3Y 7 9 4Y (4Y) GND 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 1 File Number 1539.1 CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Functional Diagrams CD74HC365, CD75HCT365 OE1 1A 1Y 2A 2Y 1 16 2 15 3 14 4 13 5 12 6 11 GND OE1 VCC 1A OE2 1Y 6A 3A 3Y CD74HC366, CD75HCT366 7 10 8 9 2A 6Y 2Y 5A 3Y GND 4Y TRUTH TABLE OUTPUTS (Y) OE1 OE2 A HC/HCT365 HC/HCT366 L L L L H L L H H L X H X Z Z H X X Z Ζ NOTE: H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance (OFF) State 2 16 2 15 3 14 4 13 5 12 6 11 3A 5Y 4A INPUTS 1 7 10 8 9 VCC OE2 6A 6Y 5A 5Y 4A 4Y CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Logic Diagram VCC 16 ONE OF SIX IDENTICAL CIRCUITS 2 1A 3 (NOTE) 1Y GND 8 1 OE1 4 15 5 2A 2Y OE2 6 7 3A 3Y 10 4A 9 4Y 12 5A 11 5Y 14 6A 13 6Y NOTE: Inverter not included in HC/HCT365. FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC/HCT366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.) 3 CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER 25oC IO (mA) VCC (V) MIN TYP -40oC TO 85oC MAX MIN MAX -55oC TO 125oC MIN MAX UNITS HC TYPES - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC SYMBOL VI (V) IO (mA) VCC (V) IOZ VIL or VIH VO = VCC or GND High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Three-State Leakage Current -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.5 - ±5.0 - ±10 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5.0 - ±10 µA Input Leakage Current Quiescent Device Current NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS OE1 0.6 All Others 0.55 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications - HC/HCT365 PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 105 130 160 ns 4.5 - 21 26 32 ns 6 - 18 22 27 ns 5 8 - - - ns HC TYPES Propagation Delay, Data to Outputs HC/HCT365 CL = 15pF 5 CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Switching Specifications - HC/HCT365 PARAMETER Propagation Delay, Data to Outputs HC/HCT366 Propagation Delay, Output Enable and Disable to Outputs Output Transition Time Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 110 140 165 ns 4.5 - 22 28 33 ns 6 - 19 24 28 ns CL = 15pF 5 9 - - - ns CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 60 75 90 ns 4.5 - 12 15 18 ns 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 5, 6) CPD - 5 40 - - - pF CL = 50pF 4.5 - 25 31 38 ns CL = 15pF 5 9 - - - ns HCT TYPES Propagation Delay, Data to Outputs HC/HCT365 tPLH, tPHL Propagation Delay, Data to Outputs HC/HCT366 tPLH, tPHL Propagation Delay, Output Enable and Disable to Outputs tPLH, tPHL Output Transition Time tTLH, tTHL CL = 50pF 4.5 - 27 34 41 ns CL = 15pF 5 11 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 12 15 18 ns Input Capacitance CIN - - - 10 10 10 pF Three-State Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 5, 6) CPD - 5 42 - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per buffer. 6. PD = VCC2fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 CD74HC365, CD74HCT365, CD74HC366, CD74HCT366 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 4. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 3V tPZL tPLZ 50% OUTPUTS ENABLED 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT HIGH TO OFF 6ns tr VCC 90% tPLH FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT LOW TO OFF 1.3V 10% INVERTING OUTPUT FIGURE 2. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 50% tTLH 90% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL OUTPUT DISABLE tf = 6ns tr = 6ns VCC 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 5. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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