CS5340
101 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
General Description
Advanced Multi-bit Delta-Sigma Architecture
The CS5340 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
24-bit Conversion
Supports All Audio Sample Rates Including
192 kHz
The CS5340 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
101 dB Dynamic Range at 5 V
-94 dB THD+N
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 1.8 V and 5 V
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
The CS5340 is available in a 16-pin TSSOP package
for Commercial (-10° to +70° C) and Automotive grades
(-40° to +85° C). The CDB5340 Customer Demonstration Board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 22 for complete ordering
information.
The CS5340 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications.
Pin Compatible with CS5341
VA
3.3 V to 5 V
Single-Ended
Analog Input
AINL
VD
3.3 V to 5 V
Switch-Cap
ADC
VL
1.8 V to 5 V
Auto-detect
MCLK Divider
Low-Latency
Digital Filters
Master Clock
FILT+
VQ
Serial Port
High-Pass
Filter
Internal
Reference
Voltages
SCLK
Slave Mode
Auto-detect
LRCK
SDOUT
M0
M1
Single-Ended
Analog Input
AINR
Switch-Cap
ADC
http://www.cirrus.com
High-Pass
Filter
Low-Latency
Digital Filters
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
Mode
Configuration
Reset
APRIL '06
DS601F1
CS5340
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4
ANALOG CHARACTERISTICS - COMMERCIAL GRADE .................................................................... 5
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 6
DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10
DIGITAL CHARACTERISTICS ............................................................................................................. 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 11
2. PIN DESCRIPTION .............................................................................................................................. 13
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14
4. APPLICATIONS ................................................................................................................................... 15
4.1 Single-, Double-, and Quad-Speed Modes ..................................................................................... 15
4.2 Operation as Either a Clock Master or Slave ................................................................................. 15
4.2.1 Operation as a Clock Master ................................................................................................. 16
4.2.2 Operation as a Clock Slave with Auto-Detect ....................................................................... 16
4.2.3 Master Clock ......................................................................................................................... 17
4.3 Serial Audio Interface ..................................................................................................................... 17
4.4 Power-Up Sequence ...................................................................................................................... 18
4.5 Analog Connections ....................................................................................................................... 18
4.6 Grounding and Power Supply Decoupling ...................................................................................... 18
4.7 Synchronization of Multiple Devices ............................................................................................... 18
4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................ 19
5. PARAMETER DEFINITIONS ................................................................................................................ 20
6. PACKAGE DIMENSIONS ................................................................................................................... 21
THERMAL CHARACTERISTICS .......................................................................................................... 21
7. ORDERING INFORMATION ................................................................................................................ 22
8. REVISION HISTORY ............................................................................................................................ 22
2
DS601F1
CS5340
LIST OF FIGURES
Figure 1.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 2.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8
Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8
Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9
Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9
Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9
Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9
Figure 12.Quad-Speed Mode Passband Ripple ......................................................................................... 9
Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12
Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12
Figure 15.Master Mode, I²S SAI ................................................................................................................ 12
Figure 16.Slave Mode, I²S SAI .................................................................................................................. 12
Figure 17.Typical Connection Diagram ..................................................................................................... 14
Figure 18.CS5340 Master Mode Clocking ................................................................................................ 16
Figure 19.I²S Serial Audio Interface .......................................................................................................... 17
Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17
Figure 21.CS5340 Recommended Analog Input Buffer ............................................................................ 18
Figure 22.CS5340 THD+N versus Frequency .......................................................................................... 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 15
Table 2. CS5340 Mode Control ................................................................................................................. 15
Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
DS601F1
3
CS5340
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Parameter
Power Supplies
Ambient Operating Temperature
Symbol
Min
Typ
Max
Unit
Analog
Digital
Logic
VA
VD
VL
3.1
3.1
1.7
(Note 1)
3.3
3.3
5.25
5.25
5.25
V
V
V
Commercial
Automotive
TAC
TAC
-10
-40
-
70
85
°C
°C
Notes:
1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics - Commercial Grade and Analog Characteristics - Automotive Grade, below, for details.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 2)
Parameter
Symbol
Min
Max
Units
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 3)
Iin
-10
+10
mA
Analog Input Voltage
(Note 4)
VIN
GND-0.7
VA+0.7
V
Digital Input Voltage
(Note 4)
VIND
-0.7
VL+0.7
V
DC Power Supplies:
Ambient Operating Temperature (Power Applied)
Storage Temperature
TA
-50
+95
°C
Tstg
-65
+150
°C
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SRC latch-up.
4. The maximum over/under voltage is limited by the input current.
4
DS601F1
CS5340
ANALOG CHARACTERISTICS - COMMERCIAL GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Dynamic Performance for Commercial Grade
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
Double-Speed Mode
Dynamic Range
(Note 5)
-1 dB
-20 dB
-60 dB
Fs = 96 kHz
40 kHz bandwidth
Quad-Speed Mode
(Note 5)
-1 dB
-20 dB
-60 dB
-1 dB
Fs = 192 kHz
Symbol
40 kHz bandwidth
(Note 5)
-1 dB
-20 dB
-60 dB
-1 dB
Min
Typ
Max
Min
Typ
Max
Unit
95
92
101
98
-
92
89
98
95
-
dB
dB
-
-94
-78
-38
-88
-
-
-91
-75
-35
-85
-
dB
dB
dB
Min
Typ
Max
Min
Typ
Max
Unit
95
92
-
101
98
95
-
92
89
-
98
95
92
-
dB
dB
dB
-
-94
-78
-38
-91
-88
-
-
-91
-75
-35
-85
-85
-
dB
dB
dB
dB
Min
Typ
Max
Min
Typ
Max
Unit
95
92
-
101
98
95
-
92
89
-
98
95
92
-
dB
dB
dB
-
-94
-78
-38
-91
-88
-
-
-91
-75
-35
-85
-85
-
dB
dB
dB
dB
THD+N
Symbol
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
VA = 3.3 V
THD+N
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
Dynamic Range
Symbol
VA = 5 V
THD+N
Min
Typ
Max
Unit
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-5
-
+5
%
Gain Drift
-
±100
-
ppm/°C
0.53*VA
0.56*VA
0.59*VA
Vpp
-
25
-
kΩ
Dynamic Performance All Modes
Interchannel Isolation
DC Accuracy
Analog Input Characteristics
Full-Scale Input Voltage
Input Impedance
5. Referred to the typical full-scale input voltage
DS601F1
5
CS5340
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Dynamic Performance for Automotive Grade
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
Double-Speed Mode
Dynamic Range
(Note 5)
-1 dB
-20 dB
-60 dB
Fs = 96 kHz
40 kHz bandwidth
Quad-Speed Mode
(Note 5)
-1 dB
-20 dB
-60 dB
-1 dB
Fs = 192 kHz
Symbol
40 kHz bandwidth
(Note 5)
-1 dB
-20 dB
-60 dB
-1 dB
Min
Typ
Max
Min
Typ
Max
Unit
93
90
101
98
-
90
87
98
95
-
dB
dB
-
-94
-78
-38
-86
-
-
-91
-75
-35
-83
-
dB
dB
dB
Min
Typ
Max
Min
Typ
Max
Unit
93
90
-
101
98
95
-
90
87
-
98
95
92
-
dB
dB
dB
-
-94
-78
-38
-91
-86
-
-
-91
-75
-35
-85
-83
-
dB
dB
dB
dB
Min
Typ
Max
Min
Typ
Max
Unit
93
90
-
101
98
95
-
90
87
-
98
95
92
-
dB
dB
dB
-
-94
-78
-38
-91
-86
-
-
-91
-75
-35
-85
-83
-
dB
dB
dB
dB
THD+N
Symbol
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
VA = 3.3 V
THD+N
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
Dynamic Range
Symbol
VA = 5 V
THD+N
Min
Typ
Max
Unit
-
90
-
dB
-
0.1
-
dB
Gain Error
-10
-
+10
%
Gain Drift
-
±100
-
ppm/°C
0.50*VA
0.56*VA
0.62*VA
Vpp
-
25
-
kΩ
Dynamic Performance All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Analog Input Characteristics
Full-Scale Input Voltage
Input Impedance
6. Referred to the typical full-scale input voltage
6
DS601F1
CS5340
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
(Note 7)
0
-
0.4895
Fs
-0.035
-
0.035
dB
(Note 7)
0.5687
-
-
Fs
70
-
-
dB
-
12/Fs
-
s
(Note 7)
0
-
0.4895
Fs
-0.025
-
0.025
dB
(Note 7)
0.5604
-
-
Fs
69
-
-
dB
-
9/Fs
-
s
0
-
0.2604
Fs
-0.025
-
0.025
dB
Single-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
Double-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
Quad-Speed Mode
Passband
(-0.1 dB)
(Note 7)
Passband Ripple
Stopband
(Note 7)
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
0.5
-
-
Fs
60
-
-
dB
-
5/Fs
-
s
-
1
20
-
Hz
Hz
-
10
-
Deg
-
-
0
dB
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 8)
@ 20 Hz
(Note 8)
Passband Ripple
7. Filter characteristics scale precisely with Fs
8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
DS601F1
7
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Amplitude (dB)
Amplitude (dB)
CS5340
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
0
0.10
-1
0.08
-2
0.06
-3
-4
-5
-6
-7
0.58
0.60
0.02
0.00
-0.02
-0.04
-0.06
-9
-0.08
-0.10
0.46 0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0
0.55
Amplitude (dB)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Figure 4. Single-Speed Mode Passband Ripple
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.05
Frequency (norm alized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Amplitude (dB)
0.56
0.04
-8
Frequency (norm alized to Fs)
0.9
1.0
Frequency (norm alized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
8
0.54
Figure 2. Single-Speed Mode Stopband Rejection
Amplitude (dB)
Amplitude (dB)
Figure 1. Single-Speed Mode Stopband Rejection
0.0
0.52
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
-10
0.45
0.46 0.48 0.50
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Figure 6. Double-Speed Mode Stopband Rejection
DS601F1
0
0.10
-1
0.08
-2
0.06
Amplitude (dB)
Amplitude (dB)
CS5340
-3
-4
-5
-6
-7
0.04
0.02
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-10
0.46
0.47
0.48
0.49
0.50
0.51
-0.10
0.00 0.05
0.52
Frequency (norm alized to Fs)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.15
0.20 0.25 0.30 0.35 0.40 0.45 0.50
Figure 8. Double-Speed Mode Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 7. Double-Speed Mode Transition Band (Detail)
0.0
0.10
Frequency (norm alized to Fs)
0.9
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 9. Quad-Speed Mode Stopband Rejection
Figure 10. Quad-Speed Mode Stopband Rejection
0
0.10
-1
0.08
0.06
-3
Amplitude (dB)
Amplitude (dB)
-2
-4
-5
-6
-7
-8
0.00
-0.02
-0.04
-0.08
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (norm alized to Fs)
Figure 11. Quad-Speed Mode Transition Band (Detail)
DS601F1
0.02
-0.06
-9
-10
0.10
0.04
-0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Figure 12. Quad-Speed Mode Passband Ripple
9
CS5340
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode)
Parameter
Symbol
Min
Typ
Max
Unit
Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.1
3.1
1.7
-
5.25
5.25
5.25
V
V
V
VA = 5 V
VA = 3.3 V
VL,VD = 5 V
VL,VD = 3.3 V
IA
IA
ID
ID
-
21
18.2
15
9
25.5
22.5
18.5
10
mA
mA
mA
mA
VA = 5 V
VL,VD=5 V
IA
ID
-
1.5
0.4
-
mA
mA
VL, VD, VA = 5 V
VL, VD, VA = 3.3 V
(Power-Down Mode)
-
-
180
90
9.5
220
107.2
-
mW
mW
mW
PSRR
-
65
-
dB
VQ Nominal Voltage
Output Impedance
-
VA÷2
25
-
V
kΩ
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
VA
36
0.01
-
V
kΩ
mA
DC Power Supplies:
Power Supply Current
(Normal Operation)
Power Supply Current
(Power-Down Mode) (Note 9)
Power Consumption
(Normal Operation)
Power Supply Rejection Ratio (1 kHz)
(Note 10)
9. Power Down Mode is defined as RST = Low, with all clocks and data lines held static at a valid logic
levels.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram, Figure 17 on page 14.
DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
(% of VL)
VIH
70%
-
-
V
Low-Level Input Voltage
(% of VL)
VIL
-
-
30%
V
High-Level Output Voltage at Io = 100 µA
(% of VL)
VOH
70%
-
-
V
Low-Level Output Voltage at Io =100 µA
(% of VL)
VOL
-
-
15%
V
Iin
-10
-
+10
µA
Input Leakage Current
10
DS601F1
CS5340
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
tclkw
39
-
45
ns
78
-
1953
ns
40
-
60
%
-20
-
20
ns
Double-Speed
-20
-
20
ns
Quad-Speed
-8
-
8
ns
-
-
32
ns
MCLK Specifications
MCLK Period
MCLK Pulse Duty Cycle
Master Mode
SCLK falling to LRCK
Single-Speed
SCLK falling to SDOUT valid.
SCLK Duty Cycle.
tmslr
tsdo
Single-Speed
-
50
-
%
Double-Speed
-
50
-
%
Quad-Speed
-
33
-
%
40
50
60
%
156
-
-
ns
45
50
55
%
Slave Mode
Single-Speed (Note 11)
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
40
50
60
%
156
-
-
ns
45
50
55
%
Double-Speed (Note 11)
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK edge.
tslrd
-20
-
20
ns
40
50
60
%
78
-
-
ns
29.7
33
50
%
Quad-Speed (Note 11)
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK edge.
tslrd
-8
-
8
ns
11. For a description of speed modes, please refer to Table 1 on page 15.
DS601F1
11
CS5340
SCLK output
LRCK input
t mslr
t sclkw
t slrd
SCLK input
LRCK output
t stp thld
t sdo
MSB
S DOUT
MSB-1
Figure 13. Master Mode, Left-Justified SAI
SDOUT
MSB
MSB-1
Figure 14. Slave Mode, Left-Justified SAI
SCLK output
LRCK input
t mslr
t slrd
LRCK output
tsclkw
SCLK input
t sdo
MSB
S DOUT
Figure 15. Master Mode, I²S SAI
12
t stp thld
SDOUT
MSB
Figure 16. Slave Mode, I²S SAI
DS601F1
CS5340
2. PIN DESCRIPTION
M0
MCLK
VL
SDOUT
GND
VD
SCLK
LRCK
Pin Name
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M1
FILT+
REF_GND
VA
AINR
VQ
AINL
RST
#
Pin Description
M0
M1
1
16
Mode Selection (Input) - Determines the operational mode of the device.
MCLK
2
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VL
3
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
4
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
GND
5,14
Ground (Input) - Ground reference. Must be connected to analog ground.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
SCLK
7
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
8
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.
RST
9
Reset (Input) - The device enters a low power mode when low.
AINL
AINR
10
12
Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specification table.
VQ
11
Quiescent Voltage (Output) - Filter connection for the internal quiescent
reference voltage.
VA
13
Analog Power (Input) - Positive power supply for the analog section.
FILT+
15
Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
DS601F1
13
CS5340
3. TYPICAL CONNECTION DIAGRAM
3.3V to 5V
+
1 µF
0.1 µF
0.1 µF
+
1 µF
1.8 V to 5V
**
3.3V to 5V
+
1 µF
5.1Ω
0.1 µF
VA
0.1 µF
VL
VD
FILT+
*** +
1 µF
0.1 µF
REFGND
+
1µF
0.1 µF
VQ
CS5340
RST
M0
M1
Power Down
and Mode
Settings
VL or GND
A/D CONVERTER
10kΩ
AINL
SDOUT
Analog Input Buffer
Figure 21
*
Audio Data
Processor
AINR
MCLK
LRCK
Timing Logic
and Clock
SCLK
GND
14
*** Capacitor value affects
* Pull-up to VL for I2S
Pull-down to GND for LJ low frequency distortion
performance as described
** Resistor may only be
in Section 4.8
used if VD is derived from
VA. If used, do not drive
any other logic from VD
DS601F1
CS5340
4. APPLICATIONS
4.1
Single-, Double-, and Quad-Speed Modes
The CS5340 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Speed Mode
MCLK/LRCK
Ratio
Output Sample Rate Range (kHz)
512x
43 - 50
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
256x
2 - 50
256x
86 - 100
128x
50 - 100
128x
172 - 200
64x*
100 - 200
* Quad-Speed Mode, 64x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK
pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16)
0
0
1
1
M0 (Pin 1)
0
1
0
1
MODE
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Clock Master, Quad-Speed Mode
Clock Slave, All Speed Modes
Table 2. CS5340 Mode Control
DS601F1
15
CS5340
4.2.1
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
÷1
÷ 256
Single
Speed
00
÷ 128
Double
Speed
01
÷ 64
Quad
Speed
10
0
M1
MCLK
÷2
LRCK Output
(Equal to Fs)
M0
1
Auto-Select
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
SCLK Output
Figure 18. CS5340 Master Mode Clocking
4.2.2
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed
Modes, respectively). Please refer to Table 1 for supported sample rate ranges.
16
DS601F1
CS5340
4.2.3
Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.
Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respectively).
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
256x, 512x
128x, 256x
64x*,128x
MCLK/LRCK Ratio
* Quad Speed, 64x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)
MCLK (MHz)
32
44.1
8.192
11.2896
22.5792
12.288
24.576
8.192
11.2896
22.5792
12.288
24.576
12.288
24.576
48
64
88.2
96
192
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3
Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pulldown to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified
audio formats. Please see Figures 13 through 16, for more information on the required timing for the two
serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio
interface formats.
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. I²S Serial Audio Interface
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 20. Left-Justified Serial Audio Interface
DS601F1
17
CS5340
4.4
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power-glitch-related issues.
4.5
Analog Connections
The analog modulator samples the input at half of the MCLK frequency, or nominally 6.144 MHz. The digital
filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the input sampling frequency (n × 6.144 MHz), where n=0,1,2,... Refer to Figure 21 which
shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the
optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoided since these can degrade signal linearity.
634 Ω
VA
100 kΩ
470 pF
C0G
4.7 µF
91 Ω
CS5340 AINx
AINx
2700 pF
100 kΩ
Figure 21. CS5340 Recommended Analog Input Buffer
4.6
Grounding and Power Supply Decoupling
As with any high-resolution converter, achieving optimal performance from the CS5340 requires careful attention to power supply and grounding arrangements. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the
system logic supply or may be powered from the analog supply via a resistor. In this case, no additional
devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with
the low-value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from
the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from FILT+ and
REF_GND. Furthermore, all ground pins on CS5340 should be referenced to the same ground reference.
The CDB5340 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.7
Synchronization of Multiple Devices
In systems where multiple ADCs are required, the user can achieve simultaneous sampling if the MCLK and
LRCK signals are the same for all of the CS5340’s in the system. If only one master clock source is needed,
one solution is to place one CS5340 in Master mode, and slave all of the other CS5340’s to the one master.
If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same
external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will ensure that all
converters begin sampling on the same clock edge.
18
DS601F1
CS5340
4.8
Capacitor Size on the Reference Pin (FILT+)
The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger
capacitor values used to optimize low frequency distortion performance. This plot was taken using the
CDB5340 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.
1 uF
2.2 uF
3.3 uF
4.7 uF
5.6 uF
6.8 uF
10 uF
22 uF
47 uF
100 uF
Figure 22. CS5340 THD+N versus Frequency
DS601F1
19
CS5340
5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
20
DS601F1
CS5340
6. PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
b2
e
SIDE VIEW
A1
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
µ
INCHES
NOM
-0.004
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
4°
MIN
-0.002
0.03346
0.00748
0.193
0.248
0.169
-0.020
0°
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
4.90
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
5.00
6.40
4.40
0.65 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
Parameter
Symbol
Allowable Junction Temperature
Junction to Ambient Thermal Impedance
DS601F1
θJA
Min
Typ
Max
Unit
-
-
135
°C
-
75
-
°C/W
21
CS5340
7. ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range Container
Bulk
101 dB, 192 kHz, Multi-Bit
CS5340
16-TSSOP
YES
Commercial -10° to +70° C
Audio A/D Converter
Tape & Reel
Bulk
101 dB, 192 kHz, Multi-Bit
CS5340
16-TSSOP
YES
Automotive -40° to +85° C
Audio A/D Converter
Tape & Reel
CDB5340 CS5340 Evaluation Board
-
Order #
CS5340-CZZ
CS5340-CZZR
CS5340-DZZ
CS5340-DZZR
CDB5340
8. REVISION HISTORY
Release
Changes
A1
Initial Advance release
A2
Updated serial port timing specifications
PP1
Change value of capacitors in analog input buffer diagram
Update Sample Rate range
Added Applications section on FILT+ filter capacitor
Add CS5340-CZZ as part number
Replace available part number CS5340-DZ with CS5340-DZZ
Initial Preliminary product release
PP2
Add lead-free option to ordering information
PP3
Remove CS5340-CZ from Ordering Information
Redefine Serial Audio Port Switching Characteristics
Correct dimension “e” under Package Dimensions
Update Output Sample Rate Range
F1
Update maximum current and power specifications
Update Filt+ output impedance specification
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
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I²C is a registered trademark of Philips Semiconductor.
22
DS601F1