[AKD4122A-A] AKD4122A-A Evaluation board Rev.0 for AK4122A GENERAL DESCRIPTION The AKD4122A-A is an evaluation board for the digital sample rate converter, the AK4122A with built-in digital audio interface receiver (DIR). The AKD4122A-A has the digital audio interface and can achieve the interface with digital audio system via opt-connector. Ordering guide AKD4122A-A --- Evaluation board for AK4122A (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.) FUNCTION • DIR/DIT with optical input/output • 10pin Header for AKM AD/DA evaluation board • BNC connector for an external clock input • 10pin Header for serial control mode AVDD, DVDD +5V Opt In AGND, DGND AK4 114 AK4114 Opt Out REG 3.3V DSP Data 10 pin Head er 10pi n Header DSP D ata AK4122A MCLK In BICK In Cl ock Divider Digi tal In 10 pin Header Control D ata Opt In MCLK In Clock Di vi der 10pin H eader AK4114 Opt In Opt Out DSP Data Figure 1. AKD4122A-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM099400> 2009/03 -1- [AKD4122A-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. [AVDD] (red) = 3.0 ∼ 3.6V (typ. 3.3V, AVDD pin) [DVDD] (red) = 3.0 ∼ 3.6V (typ. 3.3V, DVDD pin) [+5V] (orange) = +5V (for regulator) [VCC] (blue) = 3.0 ∼ 3.6V (typ. 3.3V, for digital logic) [AGND] (black) = 0V [DGND] (black) = 0V Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4122A should be reset once bringing SW6 (PDN) “L” upon power-up. Evaluation mode I/O ports and jumper pins on the board should be set according to the following explanation in order to evaluate each pass of the AK4122A. The block diagram is shown in Figure 2. MCKO RX1 RX2 RX3 RX4 INT0 INT1 INT2 R FILT RX1 RX2 OPS1-0 TX RX3 TX RX4 PDN IPS1-0 DIR SMUTE PORT3 PORT1 BICK1 LRCK1 SDTI BICK1 BICK2 LRCK2 SDTIO BICK2 LRCK1 SDTI Serial Audio I/F ISEL1-0 De-em Filter PORT2 LRCK2 SDTIO OSEL SRC BYPS LRCK BICK SDTO LRCK BICK SDTO OMCLK PLL Serial Audio I/F M/S2 M/S3 Control Register MCLK2 AVDD AVSS Serial Audio I/F DVDD DVSS MCKE CDTO CDTI CCLK CSN Figure 2. AK4122A Block Diagram <KM099400> 2009/03 -2- [AKD4122A-A] (1) AK4122A PORT1 → SRC → AK4122A PORT3 Refer to page 5 for input port setting, and page 15 ∼ 18 for output port setting. PORT4 DIR 1 PORT 10 U12 AK4114 U14 AK4114 D IT3 AK4122A BICK BI CK1 LRCK PORT 5 DSP1 PORT 9 DSP3 LRCK1 SDTO SDT I OMCLK J3 EXT3 Divider J4 EXT1 Figure 3. AK4122A PORT1 → SRC → AK4122A PORT3 (2) AK4122A PORT2 → SRC → AK4122A PORT3 Refer to page 6 ∼ 9 for input port setting, and page 15 ∼ 18 for output port setting. PORT6 DIR 2 PORT 10 U13 AK4114 U14 AK4114 D IT3 AK4122A PORT 7 DSP2 BI CK2 BICK LRCK2 LRCK SDT IO SDTO MCLK2 OMCLK PORT 9 DSP3 J2 EXT2 Divider J3 EXT3 Divider Figure 4. AK4122A PORT2 → SRC → AK4122A PORT3 (3) AK4122A DIR → SRC → AK4122A PORT3 Refer to page 10 for input port setting, and page 15 ∼ 18 for output port setting. PORT10 U14 AK4114 DIT3 AK4122A PORT3 RX1 BIC K RX2 LRC K RX3 SDT O RX4 OMCLK DI R J1 RX PORT9 DSP3 Divider J3 EXT 3 Figure 5. AK4122A DIR → SRC → AK4122A PORT3 <KM099400> 2009/03 -3- [AKD4122A-A] (4) AK4122A PORT1 → SRC → AK4122APORT2 Refer to page 5 for input port setting, and page 11 ∼ 14 for output port setting. PORT4 DIR 1 PORT8 U12 AK4114 U13 AK4114 D IT2 AK4122A BICK2 BI CK1 PORT 5 DSP1 LRCK2 PORT 7 DSP2 LRCK1 SDT IO SDT I MCLK2 J2 EXT2 Divider J4 EXT1 Figure 6. AK4122A PORT1 → SRC → AK4122A PORT2 (5) AK4122A DIR → SRC → AK4122A PORT2 Refer to page 10 for input port setting, and page 11 ∼ 14 for output port setting. POR T8 U13 AK4114 DIT2 AK4122A PORT3 RX1 BICK2 RX2 LRCK2 RX3 SDTIO RX4 MCLK2 DI R J1 RX PORT7 DSP2 Divider J2 EXT 2 Figure 7. AK4122A DIR → SRC → KA4122 PORT2 (6) Bypass Mode Refer to page 5 ∼ 10 for input port setting, and output port setting should be master mode. The bypass mode of the AK4122A is set by the register. In bypass mode, the DIT function of the AK4114 can not be used as the output port. 10pin PORT should be used instead. Input BICK, LRCK, and DATA are output from the output port side in the bypass mode. <KM099400> 2009/03 -4- [AKD4122A-A] (1) Setting for Input port (AK4122A PORT1) (1-1) Slave Mode 1. When using DIR function of AK4114 (U12) When using PORT4 (DIR1), nothing should be connected to J4 (EXT1) and PORT5 (DSP1). JP12 (EXT1) should be short. JP11 BICK1 DIR JP12 EXT1 JP13 SDTO JP14 LRCK1 EXT • SW2 setting (See Table 1,Table 2) Upper-side is “H” and lower-side is “L”. SW2 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2 ON (“H”) OFF (“L”) Fixed to “L” AK4114 Audio Format Setting Refer to Table 2 Table 1. SW2 setting Mode Audio I/F Format 0 1 2 3 16bit, LSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, LSB justified DIF2 0 1 1 0 AK4114 DIF1 0 0 0 1 DIF0 0 0 1 1 AK4122A DIF1 DIF0 0 0 0 1 1 0 1 1 Default Table 2. AK4114 Audio interface format setting * DIF1-0 of the AK4122A is set by the register. 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT5 (DSP1), nothing should be connected to PORT4 (DIR1). BICK is input from J4 (EXT1), and the LRCK and SDTI are supplied from UPD. JP12 (EXT1) should be open. JP11 BICK1 DIR JP12 EXT1 JP13 SDTO JP14 LRCK1 EXT 3. All clocks are fed through the 10pin port When using PORT5 (DSP1), nothing should be connected to J4 (EXT1) and PORT4 (DIR1). JP12 (EXT1) should be short. JP11 JP12 JP13 JP14 BICK1 EXT1 SDTO LRCK1 DIR EXT <KM099400> 2009/03 -5- [AKD4122A-A] (2) Setting for Input port (AK4122A PORT2) (2-1) Slave mode 1. When using DIR function of AK4114 (U13) When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122A. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT DIR EXT • SW3 setting (See Table 3,Table 4,Table 5) Upper-side is “H” and lower-side is “L”. SW3 No. Name 1 OCKS 2 3 4 DIF0 DIF1 DIF2 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 4 AK4114 Audio Format Setting Refer to Table 5 Table 3. SW3 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Default Table 4. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 2 3 16bit, LSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, LSB justified DIF2 0 1 1 0 AK4114 DIF1 0 0 0 1 DIF0 0 0 1 1 AK4122A IDIF1 IDIF0 0 0 0 1 1 0 1 1 Default Table 5. AK4114 Audio interface format setting * IDIF1-0 of the AK4122A is set by the register. <KM099400> 2009/03 -6- [AKD4122A-A] 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2), BICK is supplied by using the clock dividing circuit on this evaluation board and the LRCK and SDTI are supplied from UPD. Set JP18 (MCLK2) to the “EXT” when MCLK is supplied to the AK4122A. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT DIR EXT • Clock Setting MCLK is input from J2 (EXT2), BICK is supplied by using the clock dividing circuit. JP4 (DIV2) and JP5 (CLK2) are set by referring to Table 6. JP6 (BCFS) selects the frequency of BICK. JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 fs 8kHz 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 384 64fs JP7 EXT2 32fs 768 512 256 256 JP6 BCFS MCLK 256fs = 2.048MHz 384fs = 3.072MHz 512fs = 4.096MHz 768fs = 6.144MHz 256fs = 8.192MHz 384fs = 12.288MHz 512fs = 16.384MHz 768fs = 24.576MHz 256fs = 11.2896MHz 384fs = 16.9344MHz 512fs = 22.5792MHz 768fs = 33.8688MHz 256fs = 12.288MHz 384fs = 18.432MHz 512fs = 24.576MHz 768fs = 36.864MHz 256fs = 22.5792MHz 384fs = 33.8688MHz 256fs = 24.576MHz 384fs = 36.864MHz JP4(DIV2) 256 Open 512 768 256 Open 512 768 256 Open 512 768 256 Open 512 768 256 Open 256 Open JP5(CLK2) 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 384 Table 6. Example for Clock setting <KM099400> 2009/03 -7- [AKD4122A-A] 3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 DIR EXT EXT (2-2) Master mode MCLK must be provided in the master mode. 1. When using DIR function of AK4114 (U13) When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18 (MCLK2) to the “DIR” in order to supply MCLK to the AK4122A. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 DIR EXT EXT • SW3 setting (See Table 7,Table 8,Table 9) Upper-side is “H” and lower-side is “L”. SW3 No. Name 1 OCKS 2 3 4 DIF0 DIF1 DIF2 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 8 AK4114 Audio Format Setting Refer to Table 9 Table 7. SW3 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Table 8. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 24bit, MSB justified 24bit, I2S Compatible DIF2 1 1 AK4114 DIF1 1 1 DIF0 0 1 AK4122A IDIF1 IDIF0 0 1 1 0 Table 9. AK4114 Audio interface format setting * IDIF1-0 of the AK4122A is set by the register. <KM099400> 2009/03 -8- [AKD4122A-A] 2. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. MCLK is supplied to the AK4122A, and the DATA that synchronizes with BICK and LRCK output from the AK4122A is supplied to the AK4122A. JP15 SDTIO JP16 BICK2 DIR EXT JP17 LRCK2 DIR EXT JP18 MCLK2 DIR EXT (2-3) SW1 setting Set SW1 according to the mode of the AK4122A PORT2. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON (“H”) OFF (“L”) Master Mode Slave Mode Master Mode Slave Mode Fixed to “L” Default L L L Table 10. SW1 setting <KM099400> 2009/03 -9- [AKD4122A-A] (3) Setting for Input port (AK4122A DIR) (3-1) Setting for DIR input The signal source of AK4122A’s DIR can be set by JP2 (RX) and JP3 (RX1-4). VCC L1 47u PORT3 VCC GND OUT 3 2 1 C6 0.1u DIR OPT R24 470 JP3 JP2 RX J1 RX R25 75 RX1 RX2 RX3 RX4 RX1-4 BNC C11 0.1u RX1 RX2 RX3 RX4 Figure 8. DIR input circuit JP2 RX JP2 RX RX BNC Optical RX BNC Coaxial Figure 9. JP2 setting JP3 RX1-4 JP3 RX1-4 JP3 RX1-4 JP3 RX1-4 RX1 RX1 RX1 RX1 RX2 RX2 RX2 RX2 RX3 RX3 RX3 RX3 RX4 RX4 RX4 RX4 RX1 RX2 RX3 RX4 Figure 10. JP3 setting (3-2) Setting for DIR through signal DIR through signal of the AK4122A is output to TX pin via PORT2 (TX). VCC 3 2 TX C1 0.1u 1 PORT2 IN VCC GND TX Figure 11. DIR through signal <KM099400> 2009/03 - 10 - [AKD4122A-A] (4) Setting for Output port (AK4122A PORT2) (4-1) Slave mode 1. When using DIT function of AK4114 (U13) When using X’tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7 (DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122A. When MCLK frequency is changed, the value of X’tal (X1) frequency should be changed according to MCLK frequency. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR EXT JP18 MCLK2 DIR EXT • SW3 setting (See Table 11,Table 12,Table 13) Upper-side is “H” and lower-side is “L”. SW3 No. Name 1 OCKS 2 3 4 DIF0 DIF1 DIF2 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 12 AK4114 Audio Format Setting Refer to Table 13 Table 11. SW3 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Default Table 12. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 2 3 24bit, MSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, MSB justified DIF2 1 1 1 1 AK4114 DIF1 0 0 0 0 DIF0 0 0 1 0 AK4122A IDIF1 IDIF0 0 0 0 1 1 0 1 1 Default Table 13. AK4114 Audio interface format setting * IDIF1-0 of the AK4122A is set by the register. <KM099400> 2009/03 - 11 - [AKD4122A-A] 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2), BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122A. Set JP18 (MCLK2) to the “EXT” when MCLK is supplied to the AK4122A. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT DIR EXT • Clock Setting MCLK is input from J2 (EXT2), BICK and LRCK are generated by using the clock dividing circuit. JP4 (DIV2) and JP5 (CLK2) are set by referring to Table 14. JP6 (BCFS) selects the frequency of BICK. JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 fs 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 384 64fs JP7 EXT2 32fs 768 512 256 256 JP6 BCFS MCLK 256fs = 8.192MHz 384fs = 12.288MHz 512fs = 16.384MHz 768fs = 24.576MHz 256fs = 11.2896MHz 384fs = 16.9344MHz 512fs = 22.5792MHz 768fs = 33.8688MHz 256fs = 12.288MHz 384fs = 18.432MHz 512fs = 24.576MHz 768fs = 36.864MHz 256fs = 22.5792MHz 384fs = 33.8688MHz 256fs = 24.576MHz 384fs = 36.864MHz JP4(DIV2) 256 Open 512 768 256 Open 512 768 256 Open 512 768 256 Open 256 Open JP5(CLK2) 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 384 Table 14. Example for Clock setting 3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. JP15 SDTIO JP16 BICK2 DIR EXT JP17 LRCK2 DIR <KM099400> EXT JP18 MCLK2 DIR EXT 2009/03 - 12 - [AKD4122A-A] (4-2) Master mode MCLK must be provided in the master mode. 1. When using DIT function of AK4114 (U13) When using X’tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7 (DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122A. When MCLK frequency is changed, the value of X’tal (X1) frequency should be changed according to MCLK frequency. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR EXT JP18 MCLK2 DIR EXT • SW3 setting (See Table 15,Table 16,Table 17) Upper-side is “H” and lower-side is “L”. SW3 No. Name 1 OCKS 2 3 4 DIF0 DIF1 DIF2 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 16 AK4114 Audio Format Setting Refer to Table 17 Table 15. SW3 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Table 16. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 24bit, MSB justified 24bit, I2S Compatible DIF2 1 1 AK4114 DIF1 1 1 DIF0 0 1 AK4122A IDIF1 IDIF0 0 1 1 0 Table 17. AK4114 Audio interface format setting * IDIF1-0 of the AK4122A is set by the register. <KM099400> 2009/03 - 13 - [AKD4122A-A] 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2) and PORT8 (DIT2). MCLK is input from J2 (EXT2), BICK LRCK, and DATA are supplied from the AK4122A. Set JP18 (MCLK2) to the “EXT” in order to supply MCLK to the AK4122A. JP15 SDTIO JP16 BICK2 DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT DIR EXT • Clock Setting MCLK is input from J2 (EXT2). JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 384 64fs JP7 EXT2 32fs 768 512 256 256 JP6 BCFS 3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2), PORT6 (DIR2) and PORT8 (DIT2). JP7 (EXT2) should be short. MCLK is supplied to the AK4122A, and BICK, LRCK and DATA are supplied from the AK4122A. JP15 SDTIO JP16 BICK2 DIR EXT JP17 LRCK2 DIR EXT JP18 MCLK2 DIR EXT (4-3) SW1 setting Set SW1 according to the mode of the AK4122A PORT2. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON (“H”) OFF (“L”) Master Mode Slave Mode Master Mode Slave Mode Fixed to “L” Default L L L Table 18. SW1 setting <KM099400> 2009/03 - 14 - [AKD4122A-A] (5) Setting for Output port (AK4122A PORT3) (5-1) Slave mode 1. When using DIT function of AK4114 (U14) When using X’tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Please set JP21 (OMCLK) to the “DIT” when MCLK is supplied to the AK4122A. When MCLK frequency is changed, the value of X’tal (X2) frequency should be changed according to MCLK frequency. JP19 BICK DIT JP20 LRCK EXT DIT JP21 OMCLK EXT DIT JP25 TST EXT OMCK TST • SW4 setting (See Table 19,Table 20,Table 21) Upper-side is “H” and lower-side is “L”. SW4 No. Name 1 OCKS 2 DIF0 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 20 AK4114 Audio Format Setting Refer to Table 21 Table 19. SW4 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Default Table 20. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 24bit, MSB justified 24bit, I2S Compatible AK4114 DIF0 0 1 AK4122A ODIF 0 1 Default Table 21. AK4114 Audio interface format setting * ODIF of the AK4122A is set by the register. <KM099400> 2009/03 - 15 - [AKD4122A-A] 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3 (EXT3), BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122A. Set JP21 (OMCLK) to the “EXT” when MCLK is supplied to the AK4122A. JP19 BICK DIT JP20 LRCK EXT DIT JP21 OMCLK EXT DIT JP25 TST EXT OMCK TST • Clock Setting MCLK is input from J3 (EXT3), BICK and LRCK are generated by using the clock dividing circuit. JP8 (DIV3) and JP9 (CLK3) are set by referring to Table 22. JP10 (EXT3) should be open. JP8 DIV3 JP9 CLK3 fs MCLK 256fs = 8.192MHz 384fs = 12.288MHz 512fs = 16.384MHz 768fs = 24.576MHz 256fs = 11.2896MHz 384fs = 16.9344MHz 512fs = 22.5792MHz 768fs = 33.8688MHz 256fs = 12.288MHz 384fs = 18.432MHz 512fs = 24.576MHz 768fs = 36.864MHz 256fs = 22.5792MHz 384fs = 33.8688MHz 256fs = 24.576MHz 384fs = 36.864MHz 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 384 768 512 256 256 JP10 EXT3 JP8(DIV3) 256 Open 512 768 256 Open 512 768 256 Open 512 768 256 Open 256 Open JP9(CLK3) 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 384 Table 22. Example for Clock setting 3. All clocks are fed through the 10pin port When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). Set JP25 (TST) to the “OMCK” when MCLK is supplied to the AK4122A. JP10 (EXT3) should be short. JP19 BICK DIT EXT JP20 LRCK DIT JP21 OMCLK EXT <KM099400> DIT EXT JP25 TST OMCK TST 2009/03 - 16 - [AKD4122A-A] (5-2) Master mode MCLK must be provided in the master mode. 1. When using DIT function of AK4114 (U14) When using X’tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Set JP21 (OMCLK) to the “DIT” in order to supply MCLK to the AK4122A. When MCLK frequency is changed, the value of X’tal (X2) frequency should be changed according to MCLK frequency. JP20 LRCK JP19 BICK DIT EXT DIT JP21 OMCLK EXT DIT EXT JP25 TST OMCK TST • SW4 setting (See Table 23,Table 24,Table 25) Upper-side is “H” and lower-side is “L”. SW4 No. Name 1 OCKS 2 DIF0 ON (“H”) OFF (“L”) AK4114 Master Clock Output Setting Refer to Table 24 AK4114 Audio Format Setting Refer to Table 25 Table 23. SW4 setting Mode 0 1 OCKS 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs fs ∼ 96kHz ∼ 48kHz Table 24. AK4114 MCKO1 setting Mode Audio I/F Format 0 1 24bit, MSB justified 24bit, I2S Compatible AK4114 DIF0 0 1 AK4122A ODIF 0 1 Table 25. AK4114 Audio interface format setting * ODIF of the AK4122A is set by the register. <KM099400> 2009/03 - 17 - [AKD4122A-A] 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3 (EXT3), BICK LRCK, and DATA are supplied from the AK4122A. Set JP21 (OMCLK) to the “EXT” in order to supply MCLK to the AK4122A. JP20 LRCK JP19 BICK DIT EXT DIT JP21 OMCLK EXT DIT JP25 TST EXT OMCK TST • Clock Setting MCLK is input from J3 (EXT3). JP10 (EXT3) should be open. JP8 DIV3 JP9 CLK3 384 768 512 256 256 JP10 EXT3 3. All clocks are fed through the 10pin port When using PORT9 (DSP3), nothing should be connected to J3 (EXT3) and PORT10 (DIT3). Set JP25 (TST) to the “OMCK” in order to supply MCLK to the AK4122A. JP10 (EXT3) should be short. MCLK is supplied to the AK4122A, and BICK, LRCK and DATA are supplied from the AK4122A. JP19 BICK DIT EXT JP20 LRCK DIT JP21 OMCLK EXT DIT EXT JP25 TST OMCK TST (5-3) SW1 setting Set SW1 according to the mode of the AK4122A PORT3. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON (“H”) OFF (“L”) Master Mode Slave Mode Master Mode Slave Mode Fixed to “L” Default L L L Table 26. SW1 setting <KM099400> 2009/03 - 18 - [AKD4122A-A] Other jumper pins set up 1. JP1 (GND) : Analog ground and Digital ground OPEN: Separated. SHORT: Common. (The connector “DGND” can be open.) <Default> 2. JP22 (VDD2) : DVDD and VCC OPEN: Separated. SHORT: Common. (The connector “VCC” can be open.) <Default> 3. JP23 (VDD1) : AVDD and DVDD OPEN: Separated. SHORT: Common. (The connector “DVDD” can be open.) <Default> 4. JP24 (REG) : +5V and AVDD OPEN: Separated. SHORT: Common. (The connector “AVDD” can be open.) <Default> The regulator can be supplied 3.3V to all circuits by shorting JP22, 23 and 24 and supplying 5V to +5V connector. The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW5] (SMUTE): Soft mute of AK4122A [SW6] (PDN): Resets the AK4122A. Keep “H” during normal operation. The AK4122A should be resets once bringing “L” upon power-up. [SW7] (PDN1): Resets the AK4114 (U12). Keep “H” during normal operation. The AK4114 (U12) should be resets once bringing “L” upon power-up. Keep “L” when AK4114 (U12) is not used. [SW8] (PDN2): Resets the AK4114 (U13). Keep “H” during normal operation. The AK4114 (U13) should be resets once bringing “L” upon power-up. Keep “L” when AK4114 (U13) is not used. [SW9] (PDN3): Resets the AK4114 (U14). Keep “H” during normal operation. The AK4114 (U14) should be resets once bringing “L” upon power-up. Keep “L” when AK4114 (U14) is not used. <KM099400> 2009/03 - 19 - [AKD4122A-A] Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114 (U12). LED turns on when unlock or parity error occurs. [LED2] (ERF): Monitor INT0 pin of the AK4114 (U13). LED turns on when unlock or parity error occurs. [LED3] (INT0): Monitor INT0 pin of the AK4122A. [LED4] (INT1): Monitor INT1 pin of the AK4122A. [LED5] (INT2): Monitor INT2 pin of the AK4122A. Serial Control The AK4122A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1 (CTRL) with PC by 10 wire flat cable packed with the AKD4122A-A. 1 10 CSN Connect CCLK PC CDTI AKD4122A-A CDTO 10 Wire Flat Cable 5 10pin Connector 6 10pin Header Figure 12. Connection of 10 wire flat cable <KM099400> 2009/03 - 20 - [AKD4122A-A] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4122A-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4122A-A by 10-line type flat cable (packed with AKD4122A-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4122A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD4122A-A.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Setup” button. 3. Click “Write default” button. Then set up the dialog and input data. Explanation of each buttons 1. [Port Setup] : 2. [Write default] : 3. [All Read] : 4. [Function1] : 5. [Write] : 6. [Read] : Set up the printer port. Initialize the register of AK4122A. Read the all register of AK4122A. Dialog to write data by keyboard operation. Dialog to write data by mouse operation. Read each register data by mouse operation. Explanation of each dialog 1. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal. If you want to write the input data to AK4122A, click “OK” button. If not, click “Cancel” button. 2. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4122A, click “OK” button. If not, click “Cancel” button. <KM099400> 2009/03 - 21 - [AKD4122A-A] Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM099400> 2009/03 - 22 - [AKD4122A-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : Audio Precision, System Two Cascade • Power Supply : AVDD = DVDD = 3.3V • Band width : 10Hz ∼ FSO/2 • Temperature : Room • Measurement Path : AK4122A PORT1 → SRC → AK4122A PORT3 [Measurement Result] SRC Characteristics THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 48kHz/8kHz) Dynamic Range (Input = 1kHz, −60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 32kHz/44.1kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz <KM099400> Result Unit 113.5 113.4 114.2 113.2 111.7 dB dB dB dB dB 115.1 115.1 115.3 115.2 115.5 dB dB dB dB dB 117.2 dB 2009/03 - 23 - [AKD4122A-A] [Plots] AK4122A THD + N vs Input Level FSI = 44.1kHz, SFO = 48kHz, fin = 1kHz -100 -102 -104 -106 -108 -110 -112 d B F S -114 -116 -118 -120 -122 -124 -126 -128 -130 akd4122a.at27 Figure 13. THD+N vs. Input Level AK4122A THD + N vs Input Frequency FSI = 44.1kHz, SFO = 48kHz, Input = 0dBFS -80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 d B F S -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 akd4122a.at27 Figure 14. THD+N vs. Input Frequency (Input = 0dBFS) <KM099400> 2009/03 - 24 - [AKD4122A-A] AK4122A THD + N vs Input Frequency FSI = 44.1kHz, SFO = 48kHz, Input = -60dBFS -80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 d B F S -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 akd4122a.at27 Figure 15. THD+N vs. Input Frequency (Input = -60dBFS) AK4122A Linearity FSI = 44.1kHz, SFO = 48kHz, fin = 1kHz +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 akd4122a.at27 Figure 16. Linearity <KM099400> 2009/03 - 25 - [AKD4122A-A] AK4122A Frequency Response FSI = 44.1kHz, SFO = 48kHz, Input = 0dBFS +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 d B F S -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 -3.2 -3.4 -3.6 -3.8 -4 akd4122a.at27 Figure 17. Frequency Response AK4122A FFT FSI = 44.1kHz, SFO = 48kHz, Input = 0dBFS, fin = 1kHz +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 akd4122a.at27 Figure 18. FFT Plot (Input = 0dBFS) <KM099400> 2009/03 - 26 - [AKD4122A-A] AK4122A FFT FSI = 44.1kHz, SFO = 48kHz, Input = -60dBFS, fin = 1kHz +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 akd4122a.at27 Figure 19. FFT Plot (Input = -60dBFS) <KM099400> 2009/03 - 27 - [AKD4122A-A] REVISION HISTORY Date (yy/mm/dd) 09/03/10 Manual Revision KM099400 Board Revision 0 Reason Page Contents First Edition IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM099400> 2009/03 - 28 - A B C 18 17 16 15 14 13 12 11 INT1 SDTO BICK INT0 E VCC R7 51 R8 51 R9 51 R10 51 R11 51 R12 51 PORT2 C1 0.1u 3 2 IN VCC 1 GND TX 37 48 74LVC541 38 CN1 G1 G2 39 1 19 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 40 CTRL A1 A2 A3 A4 A5 A6 A7 A8 41 2 3 4 5 6 7 8 9 LRCK OMCLK U1 470 470 470 42 R4 R5 R6 43 R3 47k 44 R2 47k 45 R1 47k CSN CCLK CDTI CDTO 46 E 10 9 8 7 6 47 PORT1 E DVDD VCC 1 2 3 4 5 D R13 51 1 1 37 D CN3 INT0 38 INT1 39 TX 40 SDTO 41 BICK 42 LRCK 43 OMCLK 44 DVSS 45 C3 0.1u DVDD 46 BVSS CCLK 48 U2 CN2 CSN D 47 + C2 10u R14 51 CDTI SDTIO 36 SDTIO 36 R15 51 R16 51 2 2 CDTO BICK2 35 BICK2 35 R17 51 TST1 3 3 TST1 LRCK2 34 LRCK2 34 R18 51 INT2 4 4 INT2 MCLK2 33 5 5 TST2 DVDD 32 MCLK2 33 VCC C SW1 M/S2 1 M/S3 2 TST4 3 PORT3-DIF1 4 5 6 AK4122 R68 R69 R70 32 C4 0.1u + 47K 47K 47K 6 6 TST3 7 7 M/S2 AK4122A C5 10u C DVSS 31 31 SDTI 30 30 R19 51 SDTI R20 51 8 8 M/S3 BICK1 29 BICK1 29 R21 51 SMUTE 9 9 10 10 11 11 12 12 LRCK1 28 28 LRCK1 TST4 PDN 27 27 PDN TST5 AVSS 26 26 R 25 SMUTE VCC B B L1 47u OPT RX1 RX2 RX3 RX4 RX1-4 R25 75 C11 0.1u TST11 24 TST10 23 RX4 22 TST9 21 RX3 20 TST8 19 RX2 18 TST7 17 RX1 16 TST6 15 Analog Ground A RX4 RX3 RX2 RX1 AVDD Title Size A3 Date: A Digital Ground 24 23 22 21 20 19 CN4 BNC 18 J1 RX A JP1 GND C10 10u + JP2 RX RX1 RX2 RX3 RX4 25 R22 12k C9 0.1u 17 JP3 C8 2.2u 16 R24 470 R23 470 15 DIR C7 2.2n 14 C6 0.1u 14 2 1 AVSS GND OUT 13 3 13 VCC AVDD FILT PORT3 B C - 29 - D AKD4122A-A Document Number Rev AK4122A Monday, March 16, 2009 Sheet E 0 1 of 6 A B C D E VCC A A 256 512 768 9 Q CLK CLK CL DIV2 Q 5 Q 6 256 U5 JP5 CLK2 10 11 384 CLK RST 8 Q 13 R26 51 3 JP4 PR D 11 D CL 12 2 U3 U4A 74AC74 1 J2 EXT2 U4B 74AC74 PR 10 4 For AK4122A PORT2 JP7 EXT2 B U6 3 4 5 6 7 10 2 9 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 64fs 32fs JP6 BCFS 1 1G VCC 14 2 1A GND 7 4 2G 1Y 3 5 EXT-MCLK2 2A 10 3G 2Y 6 EXT-BICK2 9 3A 3Y 8 EXT-LRCK2 4Y 11 fs 13 4G 12 4A C12 0.1u 74VHC125 74HC4040 A B C D VCC B 14 13 12 11 15 QA QB QC QD RCO ENP ENT CLK LOAD CLR 74AC163 2 1 U16A 74HC14 C C VCC VCC D 11 CLK 3 CLK JP8 DIV3 CL D Q 5 Q 6 U10 JP9 CLK3 10 11 384 8 Q JP10 EXT3 U11 3 4 5 6 7 10 2 9 1 A B C D 1 1G VCC 14 2 1A GND 7 4 2G 1Y 3 5 EXT-MCLK3 2A 10 3G 2Y 6 EXT-BICK3 9 3A 3Y 8 EXT-LRCK3 4Y 11 256 13 R27 51 D 256 512 768 9 Q 2 CL 12 U9B 74AC74 1 J3 EXT3 PR 10 For AK4122A PORT3 PR 4 U8 U9A 74AC74 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 64fs fs 13 12 C13 0.1u D 4G 4A 74VHC125 74HC4040 QA QB QC QD RCO 14 13 12 11 15 ENP ENT CLK LOAD CLR 74AC163 E E 4 3 U16B 74HC14 Title Size A3 Date: A B C - 30 - D AKD4122A-A Document Number Rev External Clock Monday, March 16, 2009 Sheet E 2 0 of 6 A B C D E VCC VCC E 1 2 E L2 47u GND OUT 2 1 11 L H 3 3 + VCC C15 0.1u C14 10u C61 0.1u SW7 PDN1 10 9 U7E 74HC14 8 4114-PDN1 U7D 74HC14 2 DIR1 1 PORT4 R63 10k D3 HSU119 R28 470 C16 0.1u C17 0.47u R29 18k + 37 INT1 38 AVDD R 39 40 VCOM 42 41 AVSS NC RX0 43 44 RX1 45 TEST1 NC RX2 48 RX3 1 46 D U12 47 D IPS0 U7C INT0 36 5 R30 1k 6 LED1 ERF 2 74HC14 2 PORT1-DIF0 NC 3 DIF0 4 OCKS0 R31 100 1 BICK1 PORT5 35 R32 100 OCKS1 34 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 7 DIF2 XTI 30 8 IPS1 XTO 29 PORT1-OCKS1 LRCK1 BICK1 LRCK1 SDTI 1 2 3 4 5 R33 100 PORT1-DIF2 AK4114 R34 220k P/SN DAUX R35 220k R36 220k C 4114-PDN1 U7B 74HC14 EXT 9 4 U7A 74HC14 3 2 XTL0 28 R37 51 MCKO2 27 BICK 26 SDTO 25 DIR JP12 EXT1 B 11 XTL1 12 VIN J4 EXT1 1 JP11 BICK1 10 DSP1 SDTI C PORT1-DIF1 C21 10u B VCC LRCK OCKS DIF0 DIF1 DIF2 JP14 LRCK1 24 MCKO1 23 22 DVSS DVDD C20 10u + 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 TX0 15 14 C19 0.1u + 13 TVDD DVSS JP13 SDTO C18 0.1u 10 9 8 7 6 SW2 1 2 3 4 8 7 6 5 PORT1 R71 R72 R73 R74 47K 47K 47K 47K PORT1-OCKS1 PORT1-DIF0 PORT1-DIF1 PORT1-DIF2 U7F A A 13 12 74HC14 Title Size AKD4122A-A Document Number A3 Date: A B C - 31 - D Monday, March 16, 2009 Rev PORT1 Sheet E 0 3 of 6 A B C D E VCC VCC E E 2 2 1 C23 0.1u DIR2 C22 10u R38 470 1 3 D4 HSU119 H 3 L IPS0 2 NC 3 DIF0 4 5 10 9 U16E 74HC14 4114-PDN2 38 2 C62 0.1u 8 U16D 74HC14 37 INT1 R 39 40 VCOM 42 41 AVSS NC RX0 43 44 RX1 46 45 TEST1 NC RX2 47 48 RX3 PORT2-DIF0 1 SW8 PDN2 R39 18k AVDD C25 0.47u + U13 D R64 10k 11 C24 0.1u 1 VCC GND OUT + L3 47u PORT6 U16C 74HC14 INT0 36 OCKS0 35 5 R40 1k 6 D LED2 ERF 2 1 R41 100 OCKS1 34 TEST2 CM1 33 DIF1 CM0 32 MCLK2 PORT2-OCKS1 R42 100 PORT2-DIF1 BICK2 MCLK2 BICK2 LRCK2 SDTIO R43 100 LRCK2 7 PORT2-DIF2 AK4114 NC PDN 31 R44 100 4114-PDN2 C26 22p DIF2 XTI 30 R45 220k IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 12 VIN SDTO 25 C DSP2 R46 220k R47 220k R48 220k 2 X1 11.2896MHz 8 10 9 8 7 6 SDTIO 1 6 C PORT7 1 2 3 4 5 C27 22p JP15 SDTIO JP16 BICK2 C31 10u LRCK EXT A 3 2 GND 1 DIT2 8 7 6 5 B EXT-BICK2 R75 R76 R77 R78 DIR 47K 47K 47K 47K PORT2-OCKS1 PORT2-DIF0 PORT2-DIF1 PORT2-DIF2 JP17 LRCK2 EXT PORT8 IN VCC VCC SW3 1 2 3 4 PORT2 24 MCKO1 23 22 DVSS DVDD C30 10u + 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 TX0 15 14 C29 0.1u + 13 TVDD DVSS B C28 0.1u OCKS DIF0 DIF1 DIF2 DIR EXT-LRCK2 DIR C32 0.1u JP18 MCLK2 A U16F 74HC14 13 EXT EXT-MCLK2 12 Title Size AKD4122A-A Document Number A3 Date: A B C - 32 - D Monday, March 16, 2009 Rev PORT2 Sheet E 0 4 of 6 A B C D E VCC VCC E E 2 + 1 C33 10u C34 0.1u D5 HSU119 1 IPS0 2 2 3 U15A 74HC14 C63 0.1u 4 4114-PDN3 U15B 74HC14 37 TST1 INT1 38 2 SW9 PDN3 AVDD R 39 40 VCOM 42 41 AVSS NC RX0 43 44 RX1 46 45 TEST1 NC RX2 47 48 RX3 1 R49 18k 1 H 3 L C35 0.47u + U14 D R65 10k TST INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 D JP25 TST OMCK PORT3-DIF0 R50 100 PORT3-OCKS1 OMCLK R51 100 PORT3-DIF1 BICK OMCLK BICK LRCK SDTO R52 100 LRCK 7 AK4114 NC PDN 31 XTI 30 R54 220k IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 12 VIN SDTO 25 C DSP3 R55 220k R56 220k R57 220k 2 X2 24.576MHz 8 10 9 8 7 6 SDTO C36 22p DIF2 R53 100 4114-PDN3 1 6 C PORT9 1 2 3 4 5 C37 22p C40 10u C41 10u LRCK EXT A 3 2 GND 1 DIT3 OCKS 1 DIF0 2 EXT-BICK3 VCC SW4 B 4 3 PORT3 R66 R67 DIT 47K 47K PORT3-OCKS1 PORT3-DIF0 JP20 LRCK EXT PORT10 IN VCC JP19 BICK 24 MCKO1 23 22 DVSS DVDD C39 0.1u + 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 TX0 15 14 C38 0.1u + 13 TVDD DVSS B DIT EXT-LRCK3 DIT C42 0.1u JP21 OMCLK A EXT EXT-MCLK3 Title Size A3 Date: A B C - 33 - D AKD4122A-A Document Number Rev PORT3 Monday, March 16, 2009 0 Sheet E 5 of 6 A B A C D E A 1 2 VCC D1 HSU119 R58 10k 5 1 H 3 L C43 0.1u 9 8 SMUTE U15D 74HC14 VCC 2 SW5 SMUTE 6 U15C 74HC14 LED3 INT0 1 R59 1k 2 2 1 INT0 U17A 74HC14 B LED4 INT1 1 2 4 LED5 INT2 1 2 1 D2 HSU119 1 C44 0.1u SW6 PDN 6 5 INT2 U17C 74HC14 H 3 INT1 R62 1k 2 R61 10k 13 12 U15F 74HC14 11 10 PDN U15E 74HC14 C 2 C 3 U17B 74HC14 VCC L B R60 1k VCC DVDD AVDD U17D 74HC14 +5V 9 For 74HC14 x 4, 74HC4040 x 2, 74AC74 x 2, 74AC163 x 2, 74LVC541 x 1 L4 (short) JP22 VDD2 JP23 VDD1 L5 (short) OUT DVDD C64 0.1u C48 0.1u C49 0.1u C50 0.1u C51 0.1u C52 0.1u C53 0.1u C54 0.1u C55 0.1u C56 0.1u C57 0.1u C58 47u + AVDD C59 47u + C60 + 47u 11 IN D 10 U17F 74HC14 C46 C47 0.1u 47u C45 0.1u 8 U17E 74HC14 T1 TA48M33F JP24 REG GND D 13 + 12 E E Title Size A3 Date: A B C - 34 - D Document Number AKD4122A-A Rev 0 Power Supply Monday, March 16, 2009 Sheet E 6 of 6 - 35 - - 36 - - 37 -