TI CD74HC195E High-speed cmos logic 4-bit parallel access register Datasheet

[ /Title
(CD74
HC195
)
/Subject
(High
Speed
CMOS
Logic
4-Bit
Parallel
Access
Register)
/Autho
CD54HC195, CD74HC195
Data sheet acquired from Harris Semiconductor
SCHS165E
High-Speed CMOS Logic
4-Bit Parallel Access Register
September 1997 - Revised October 2003
Features
Description
• Asynchronous Master Reset
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
• J, K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
The two modes of operation, shift right (Q0-Q1) and parallel
load, are controlled by the state of the Parallel Enable (PE)
input. Serial data enters the first flip-flop (Q0) via the J and K
inputs when the PE input is high, and is shifted one bit in the
direction Q0-Q1-Q2-Q3 following each Low to High clock
transition. The J and K inputs provide the flexibility of the JKtype input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the PE input is Low. After the Low to High clock
transition, data on the parallel inputs (D0-D3) is transferred
to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2)
can be achieved by tying the Qn outputs to the Dn-1 inputs
and holding the PE input low.
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical fMAX = 50MHz at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The ’HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operations, other
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (MR) input sets all Q outputs Low,
independent of any other input condition.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
Ordering Information
PInout
PART NUMBER
CD54HC195
(CERDIP)
CD74HC195
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
MR 1
TEMP. RANGE
(oC)
CD54HC195F3A
-55 to 125
16 Ld CERDIP
CD74HC195E
-55 to 125
16 Ld PDIP
CD74HC195M
-55 to 125
16 Ld SOIC
CD74HC195NSR
-55 to 125
16 Ld SOP
CD74HC195PW
-55 to 125
16 Ld TSSOP
CD74HC195PWR
-55 to 125
16 Ld TSSOP
CD74HC195PWT
-55 to 125
16 Ld TSSOP
16 VCC
J 2
15 Q0
K 3
14 Q1
D0 4
13 Q2
D1 5
12 Q3
D2 6
11 Q3
D3 7
10 CP
GND 8
9 PE
NOTE: When ordering, use the entire part number. The suffix R
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
PACKAGE
1
CD54HC195, CD74HC195
Functional Diagram
PE D0 D1 D2 D3
9
4
5
6
7
2
J
10
CP
11
Q3
3
K
1
MR
15
14
13
12
Q0 Q1 Q2 Q3
TRUTH TABLE
INPUTS
OPERATING MODES
OUTPUT
MR
CP
PE
J
K
Dn
Q0
Q1
Q2
Q3
Q3
Asynchronous Reset
L
X
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
↑
h
h
h
X
H
q0
q1
q2
q2
Shift, Reset First Stage
H
↑
h
l
l
X
L
q0
q1
q2
q2
Shift, Toggle First Stage
H
↑
h
h
l
X
q0
q0
q1
q2
q2
Shift, Retain First Stage
H
↑
h
l
h
X
q0
q0
q1
q2
q2
Parallel Load
H
↑
l
X
X
dn
d0
d1
d2
d3
d2
H = High Voltage Level
L = Low Voltage Level,
X = Don’t Care
↑ = Transition from Low to High Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,
dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock
Transition.
2
CD54HC195, CD74HC195
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
25oC
VCC (V)
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD54HC195, CD74HC195
Prerequisite For Switching Function
PARAMETER
SYMBOL
Clock Frequency
fMAX
MR Pulse Width
-
tw
Clock Pulse Width
Removal Time,
MR to Clock
Switching Specifications
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
5
-
4
-
MHz
30
-
25
-
20
-
MHz
35
-
29
-
23
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
-
tREM
-40oC TO 85oC -55oC TO 125oC
6
-
tH
25oC
4.5
-
tSU
Hold Time
J, K, PE to Clock
2
-
tw
Set-up Time
J, K, PE to Clock
PARAMETER
TEST
CONDITIONS VCC (V)
2
3
-
3
-
3
-
ns
4.5
3
-
3
-
3
-
ns
6
5
-
3
-
3
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
-
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
HC TYPES
Propagation Delay, CP to
Output
Propagation Delay,
MR toOutput
Output Transition Times
(Figure 1)
Input Capacitance
CP to Qn Propagation Delay
tPLH, tPHL
tTLH, tTHL
CIN
CL = 50pF
CL = 50pF
-
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
-
-
10
10
10
pF
tPLH, tPHL
CL = 15pF
5
14
-
-
-
ns
MR to Qn
tPHL
CL = 15pF
5
13
-
-
-
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 2, 3)
CPD
CL = 15pF
45
-
-
-
pF
NOTES:
2. CPD is used to determine the dynamic power consumption, per flip-flop.
3. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
4
CD54HC195, CD74HC195
Test Circuit and Waveforms
tW
RESET
tr
CLOCK V
S
GND
tf
VCC
90%
10%
tW
Q
GND
90%
10%
tTLH
tPLH
0.5 VCC
tPHL
l/fMAX
tPLH tPHL
Q OR Q
VCC
VS
Q
VS
tREM
0.5 VCC
CLOCK
tTHL
0.5 VCC
VCC
GND
FIGURE 2. MASTER RESET PREREQUISITE AND
PROPAGATION DELAYS
FIGURE 1. CLOCK PREREQUISITE AND PROPAGATION
DELAYS AND OUTPUT TRANSITION TIMES
VALID
PE, K
VCC
VS
J
GND
th
tSU
CLOCK
0.5 VCC
GND
FIGURE 3. J, K, OR PARALLEL ENABLE PREREQUISITE TIMES
5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
CD54HC195F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC195E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC195EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC195M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195ME4
ACTIVE
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC195PWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Package
Drawing
Pins Package Eco Plan (2)
Qty
40
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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