AD AD8137YRZ-REEL7 Low cost, low power 12-bit differential adc driver Datasheet

Low Cost, Low Power 12-Bit
Differential ADC Driver
AD8137
FEATURES
12-bit ADC drivers
Portable instrumentation
Battery-powered applications
Single-ended-to-differential converters
Differential active filters
Video amplifiers
Level shifters
8
+IN
VOCM 2
7
PD
VS+ 3
6
VS–
+OUT 4
5
–OUT
04771-0-001
–IN 1
Figure 1.
3
G=1
2
1
0
–1
G=5
–2
–3
G=2
–4
–5
G = 10
–6
–7
–8
–9
04771-0-002
APPLICATIONS
AD8137
NORMALIZED CLOSED-LOOP GAIN (dB)
Fully differential
Extremely low power with power-down feature
2.6 mA quiescent supply current @ 5 V
450 µA in power-down mode @ 5 V
High speed
110 MHz large signal 3 dB bandwidth @ G = 1
450 V/µs slew rate
12-bit SFDR performance @ 500 kHz
Fast settling time: 100 ns to 0.02%
Low input offset voltage: ±2.6 mV max
Low input offset current: 0.45 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Externally adjustable gain
Wide supply voltage range: 2.7 V to 12 V
Available in small SOIC package
FUNCTIONAL BLOCK DIAGRAM
–10
RG = 1kΩ
VO, dm = 0.1V p-p
–11
–12
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 2. Small Signal Response for Various Gains
GENERAL DESCRIPTON
The AD8137 is a low cost differential driver with a rail-to-rail
output that is ideal for driving 12-bit ADCs in systems that are
sensitive to power and cost. The AD8137 is easy to apply, and its
internal common-mode feedback architecture allows its output
common-mode voltage to be controlled by the voltage applied
to one pin. The internal feedback loop also provides inherently
balanced outputs as well as suppression of even-order harmonic
distortion products. Fully differential and single-ended-todifferential gain configurations are easily realized by the
AD8137. External feedback networks consisting of four resistors
determine the amplifier’s closed-loop gain. The power-down
feature is beneficial in critical low power applications.
The AD8137 is manufactured on Analog Devices’ proprietary
second generation XFCB process, enabling it to achieve high
levels of performance with very low power consumption.
The AD8137 is available in the small 8-lead SOIC package and
3 mm × 3 mm LFCSP. It is rated to operate over the extended
industrial temperature range of −40°C to +125°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8137
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
Absolute Maximum Ratings............................................................ 6
8/04—Data Sheet Changed from a Rev. 0 to Rev. A.
Added 8-Lead LFCSP.........................................................Universal
Changes to Layout ..............................................................Universal
Changes to Product Title..................................................................1
Changes to Figure 1...........................................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings ........................................6
Changes to Figure 4 and Figure 5....................................................7
Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48,
and Figure 58; Renumbered Successive Figures............................7
Changes to Figure 32...................................................................... 12
Changes to Figure 40...................................................................... 13
Changes to Figure 55...................................................................... 16
Changes to Table 7 and Figure 63................................................. 18
Changes to Equation 19................................................................. 19
Changes to Figure 64 and Figure 65............................................. 20
Changes to Figure 66...................................................................... 22
Added Driving an ADC with Greater Than 12-Bit
Performance Section ...................................................................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 24
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 17
Applications..................................................................................... 18
Analyzing a Typical Application with Matched RF and RG
Networks...................................................................................... 18
Estimating Noise, Gain, and Bandwith with Matched
Feedback Networks .................................................................... 18
Driving an ADC with Greater Than 12-Bit Performance..... 22
Outline Dimensions ....................................................................... 24
Ordering Guide........................................................................... 24
5/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8137
SPECIFICATIONS
Table 1. VS = ±5 V, VOCM = 0 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Settling Time to 0.02%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current, Disabled
PSRR
PD PIN
Threshold Voltage
Input Current
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 2 V Step
VO, dm = 3.5 V Step
G = 2, VI, dm = 12 V p-p Triangle Wave
64
79
76
110
450
100
85
MHz
MHz
V/µs
ns
ns
90
76
8.25
1
dB
dB
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 500 kHz
VO, dm = 2 V p-p, fC = 2 MHz
f = 50 kHz to 1 MHz
f = 50 kHz to 1 MHz
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−2.6
±0.7
3
0.5
0.1
91
−4
Differential
Common-Mode
Common-Mode
∆VICM = ±1 V
66
Each Single-Ended Output, RL, dm = 1 kΩ
VS− + 0.55
f = 1 MHz
VO, cm = 0.1 V p-p
VO, cm = 0.5 V p-p
0.992
−28
∆VO, dm/∆VOCM, ∆VOCM = ±0.5 V
62
79
VS+ − 0.55
20
−64
V
mA
dB
58
63
1.000
MHz
V/µs
V/V
Rev. A | Page 3 of 24
1.008
+4
35
±11
18
0.3
75
3.2
750
91
150/210
−40
mV
µV/°C
µA
µA
dB
V
KΩ
KΩ
pF
dB
VS− + 0.7
Power-Down = High/Low
1
0.45
Unit
+4
+2.7
Power-Down = Low
∆VS = ±1 V
+2.6
800
400
1.8
79
−4
f = 100 kHz to 1 MHz
Max
+28
1.1
V
kΩ
mV
nV/√Hz
µA
dB
±6
3.6
900
V
mA
µA
dB
VS− + 1.7
170/240
+125
V
µA
°C
AD8137
Table 2. VS = 5 V, VOCM = 2.5 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Settling Time to 0.02%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current, Disabled
PSRR
PD PIN
Threshold Voltage
Input Current
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 2 V Step
VO, dm = 3.5 V Step
G = 2, VI, dm = 7 V p-p Triangle Wave
63
76
75
107
375
110
90
MHz
MHz
V/µs
ns
ns
89
73
8.25
1
dB
dB
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 500 kHz
VO, dm = 2 V p-p, fC = 2 MHz
f = 50 kHz to 1 MHz
f = 50 kHz to 1 MHz
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−2.7
±0.7
3
0.5
0.1
89
1
Differential
Common-Mode
Common-Mode
∆VICM = ±1 V
64
Each Single-Ended Output, RL, dm = 1 kΩ
VS− + 0.45
f = 1 MHz
VO, cm = 0.1 V p-p
VO, cm = 0.5 V p-p
0.980
−25
∆VO, dm /∆VOCM, ∆VOCM = ±0.5 V
62
79
VS+ − 0.45
20
−64
V
mA
dB
60
61
1.000
MHz
V/µs
V/V
Rev. A | Page 4 of 24
1.020
4
35
±7.5
18
0.25
75
2.6
450
91
50/110
−40
mV
µV/°C
µA
µA
dB
V
KΩ
KΩ
pF
dB
VS− + 0.7
Power-Down = High/Low
0.9
0.45
Unit
4
+2.7
Power-Down = Low
∆VS = ±1 V
+2.7
800
400
1.8
90
1
f = 100 kHz to 5 MHz
Max
+25
0.9
V
kΩ
mV
nV/√Hz
µA
dB
±6
2.8
600
V
mA
µA
dB
VS− + 1.5
60/120
+125
V
µA
°C
AD8137
Table 3. VS = 3 V, VOCM = 1.5 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Slew Rate
Settling Time to 0.02%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current, Disabled
PSRR
PD PIN
Threshold Voltage
Input Current
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 2 V Step
VO, dm = 3.5 V Step
G = 2, VI, dm = 5 V p-p Triangle Wave
61
62
73
93
340
110
100
MHz
MHz
V/µs
ns
ns
89
71
8.25
1
dB
dB
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 500 kHz
VO, dm = 2 V p-p, fC = 2 MHz
f = 50 kHz to 1 MHz
f = 50 kHz to 1 MHz
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−2.75
±0.7
3
0.5
0.1
87
1
Differential
Common-Mode
Common-Mode
∆VICM = ±1 V
64
Each Single-Ended Output, RL, dm = 1 kΩ
VS− + 0.37
f = 1 MHz
VO, cm = 0.1 V p-p
VO, cm = 0.5 V p-p
0.96
−25
∆VO, dm /∆VOCM, ∆VOCM = ±0.5 V
62
78
VS+ − 0.37
20
−64
V
mA
dB
61
59
1.00
MHz
V/µs
V/V
Rev. A | Page 5 of 24
1.04
2.0
35
±5.5
18
0.3
74
2.3
345
90
8/65
−40
mV
µV/°C
µA
µA
dB
V
MΩ
MΩ
pF
dB
VS− + 0.7
Power-Down = High/Low
0.9
0.4
Unit
2
+2.7
Power-Down = Low
∆VS = ±1 V
+2.75
800
400
1.8
80
1.0
f = 100 kHz to 5 MHz
Max
+25
0.7
V
kΩ
mV
nV/√Hz
µA
dB
±6
2.5
460
V
mA
µA
dB
VS− + 1.5
10/70
+125
V
µA
°C
AD8137
ABSOLUTE MAXIMUM RATINGS
Table 4.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Rating
12 V
VS+ to VS−
See Figure 3
VS+ to VS−
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W) and LFCSP (θJA = 70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
3.0
MAXIMUM POWER DISSIPATION (W)
θJA is specified for the worst-case conditions, i.e., θJA is specified
for the device soldered in a circuit board in still air.
Table 5. Thermal Resistance
Package Type
SOIC-8/2-Layer
SOIC-8/4-Layer
LFCSP/4-Layer
θJA
157
125
70
θJC
56
56
56
Unit
°C/W
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8137 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses
that the package exerts on the die, permanently shifting the
parametric performance of the AD8137. Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices potentially causing failure.
2.5
LFCSP
2.0
1.5
1.0
SOIC-8
0.5
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
04771-0-022
Parameter
Supply Voltage
VOCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. A | Page 6 of 24
AD8137
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
+IN
VOCM 2
7
PD
VS+ 3
6
VS–
+OUT 4
5
–OUT
04771-0-001
AD8137
–IN 1
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
3
4
5
6
7
8
VS+
+OUT
−OUT
VS−
PD
+IN
Description
Inverting Input.
An internal feedback loop drives the
output common-mode voltage to be
equal to the voltage applied to the VOCM
pin, provided the amplifier’s operation
remains linear.
Positive Power Supply Voltage.
Positive Side of the Differential Output.
Negative Side of the Differential Output.
Negative Power Supply Voltage.
Power Down.
Noninverting Input.
RF
50Ω
VTEST
CF
RG = 1kΩ
52.3Ω
MIDSUPPLY
AD8137
VOCM
52.3Ω
TEST
SIGNAL
SOURCE
–
+
RL, dm 1kΩ
–
50Ω
RG = 1kΩ
VO, dm
+
CF
04771-0-023
Name
−IN
VOCM
RF
Figure 5. Basic Test Circuit
RF = 1kΩ
50Ω
52.3Ω
VTEST
RG = 1kΩ
MIDSUPPLY
VOCM
52.3Ω
TEST
SIGNAL
SOURCE
50Ω
RS
–
+
AD8137
CL, dm
–
+
RS
RG = 1kΩ
RF = 1kΩ
Figure 6. Capacitive Load Test Circuit, G = 1
Rev. A | Page 7 of 24
RL, dm VO, dm
04771-0-062
Pin No.
1
2
AD8137
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Diff. Gain = 1, RG = RF = RL, dm = 1 kΩ, VS = 5 V, TA = 25°C, VOCM = 2.5V. Refer to the basic test circuit in Figure 5
for the definition of terms.
3
3
G=1
–1
G=2
G=5
–2
–3
–4
–5
G = 10
–6
–7
–8
–9
–10
–11
–12
0.1
RG = 1kΩ
VO, dm = 0.1V p-p
1
10
FREQUENCY (MHz)
100
1000
Figure 7. Small Signal Frequency Response for Various Gains
–2
–3
G=2
G=5
–4
–5
G = 10
–6
–7
–8
–9
–10
RG = 1kΩ
–11
VO, dm = 2.0V p-p
–12
0.1
1
10
FREQUENCY (MHz)
100
1000
4
VS = +5
2
VS = +3
3
1
0
VS = +5
2
VS = +3
1
VS = ±5
–1
CLOSED-LOOP GAIN (dB)
–2
–3
–4
–5
–6
–7
–8
–9
0
VS = ±5
–1
–2
–3
–4
–5
–6
–7
–11
–12
VO, dm = 0.1V p-p
1
10
100
FREQUENCY (MHz)
–9
–10
–11
1000
VO, dm = 2.0V p-p
1
Figure 8. Small Signal Frequency Response for Various Power Supplies
04771-0-005
04771-0-003
–8
–10
10
100
FREQUENCY (MHz)
1000
Figure 11. Large Signal Frequency Response for Various Power Supplies
3
4
2
3
1
2
0
T = +25°C
CLOSED-LOOP GAIN (dB)
1
–1
T = +85°C
–2
–3
T = +25°C
–4
T = +125°C
–5
T = –40°C
–6
–7
–8
–9
0
–1
T = +85°C
–2
–3
–4
T = +125°C
–5
–6
–7
04771-0-006
–8
–10
–11
VO, dm = 0.1V p-p
–12
1
10
100
FREQUENCY (MHz)
T = –40°C
04771-0-007
CLOSED-LOOP GAIN (dB)
–1
Figure 10. Large Signal Frequency Response for Various Gains
3
CLOSED-LOOP GAIN (dB)
G=1
1
0
04771-0-004
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1
0
04771-0-002
NORMALIZED CLOSED-LOOP GAIN (dB)
2
–9
–10
VO, dm = 2.0V p-p
–11
1000
1
Figure 9. Small Signal Frequency Response at Various Temperatures
10
100
FREQUENCY (MHz)
1000
Figure 12. Large Signal Frequency Response at Various Temperatures
Rev. A | Page 8 of 24
AD8137
3
3
RL, dm = 1kΩ
2
RL, dm = 500Ω
2
1
1
0
RL, dm = 2kΩ
–1
CLOSED-LOOP GAIN (dB)
–2
–3
–4
–5
–6
–7
–8
–11
–12
VO, dm = 0.1V p-p
1
–4
–5
–6
–7
RL, dm = 2kΩ
–8
RL, dm = 500Ω
10
100
FREQUENCY (MHz)
–10
RL, dm = 1kΩ
–11
–12
1000
VO, dm = 2V p-p
1
Figure 13. Small Signal Frequency Response for Various Loads
10
100
FREQUENCY (MHz)
1000
Figure 16. Large Signal Frequency Response for Various Loads
3
3
2
1
0
–2
–3
CLOSED-LOOP GAIN (dB)
CF = 1pF
–1
CF = 0pF
2
CF = 0pF
1
0
CF = 2pF
–4
–5
–6
–7
–8
–9
CF = 1pF
–1
–2
–3
CF = 2pF
–4
–5
–6
–7
–8
04771-0-008
–9
–10
–11
–12
VO, dm = 0.1V p-p
1
10
100
FREQUENCY (MHz)
04771-0-009
CLOSED-LOOP GAIN (dB)
–3
04771-0-043
–10
–10
–11
–12
1000
VO, dm = 2.0V p-p
1
10
100
FREQUENCY (MHz)
1000
Figure 14. Small Signal Frequency Response for Various CF
Figure 17. Large Signal Frequency Response for Various CF
2
3
VOCM = 4V
1
VOCM = 2.5V
2
0
1
–1
0
–2
CLOSED-LOOP GAIN (dB)
VOCM = 1V
–3
–4
–5
–6
–7
–8
–9
–10
–1
0.5V p-p
–2
–3
–4
–5
–6
–7
2V p-p
–8
–9
04771-0-042
CLOSED-LOOP GAIN (dB)
–2
–9
04771-0-041
–9
–1
–11
–12
–13
VO, dm = 0.1V p-p
1
10
100
FREQUENCY (MHz)
0.1V p-p
–10
1V p-p
–11
–12
1000
1
Figure 15. Small Signal Frequency Response at Various VOCM
10
100
FREQUENCY (MHz)
Figure 18. Frequency Response for Various Output Amplitudes
Rev. A | Page 9 of 24
04771-0-044
CLOSED-LOOP GAIN (dB)
0
1000
4
3
3
2
2
1
1
RF = 500Ω
RF = 2kΩ
–2
–3
RF = 1kΩ
–4
–5
–6
–7
–8
G=1
VS = ±5V
VO, dm = 0.1V p-p
–9
–10
–11
1
10
100
FREQUENCY (MHz)
RF = 500Ω
–4
RF = 1kΩ
–5
–6
–7
–8
1000
G=1
VO, dm = 2V p-p
1
10
100
FREQUENCY (MHz)
1000
Figure 22. Large Signal Frequency Response for Various RF
–40
G=1
VO, dm = 2V p-p
–50
–75
VS = +3V
–80
VS = +5V
–85
G=1
VO, dm = 2V p-p
–60
DISTORTION (dBc)
VS = ±5V
–90
VS = +3V
–70
VS = +5V
–80
VS = ±5V
–90
–95
–100
04771-0-045
–100
–105
0.1
1
FREQUENCY (MHz)
04771-0-063
DISTORTION (dBc)
RF = 2kΩ
–3
–9
–65
–110
0.1
10
Figure 20. Second Harmonic Distortion vs. Frequency and Supply Voltage
1
FREQUENCY (MHz)
10
Figure 23. Third Harmonic Distortion vs. Frequency and Supply Voltage
–50
–55
–2
–10
–11
Figure 19. Small Signal Frequency Response for Various RF
–70
0
–1
04771-0-036
0
–1
CLOSED-LOOP GAIN (dB)
4
04771-0-037
CLOSED-LOOP GAIN (dB)
AD8137
–50
FC = 500kHz
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE
–55
–60
VS = +3V
–60
DISTORTION (dBc)
VS = +5V
–70
–75
VS = +3V
–80
VS = +3V
–85
–70
–75
–80
VS = +5V
–85
VS = +3V
VS = +5V
–90
04771-0-027
–90
–95
–100
0.25
–65
1.25
2.25
3.25
4.25 5.25 6.25
VO, dm (V p-p)
7.25
8.25
FC = 2MHz
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE
–95
–100
0.25
9.25
Figure 21. Harmonic Distortion vs. Output Amplitude and Supply, FC = 500 kHz
1.25
2.25
3.25
4.25 5.25 6.25
VO, dm (V p-p)
7.25
8.25
04771-0-026
DISTORTION (dBc)
VS = +5V
–65
9.25
Figure 24. Harmonic Distortion vs. Output Amplitude and Supply, FC = 2 MHz
Rev. A | Page 10 of 24
AD8137
–40
–40
VO, dm = 2V p-p
–50
–50
–60
–60
DISTORTION (dBc)
RL, dm = 200Ω
–70
–80
RL, dm = 1kΩ
RL, dm = 500Ω
–90
–80
RL, dm = 1kΩ
–90
1
FREQUENCY (MHz)
RL, dm = 500Ω
–100
04771-0-032
–100
–110
0.1
RL, dm = 200Ω
–70
–110
0.1
10
Figure 25. Second Harmonic Distortion at Various Loads
04771-0-033
DISTORTION (dBc)
VO, dm = 2V p-p
1
FREQUENCY (MHz)
10
Figure 28. Third Harmonic Distortion at Various Loads
–40
–40
VO, dm = 2V p-p
RG = 1kΩ
VO, dm = 2V p-p
RG = 1kΩ
–50
–50
–70
G=1
–80
–60
–70
G=2
–80
G=1
–90
–90
–100
–100
–110
0.1
1
FREQUENCY (MHz)
–110
0.1
10
1
FREQUENCY (MHz)
10
Figure 29. Third Harmonic Distortion at Various Gains
Figure 26. Second Harmonic Distortion at Various Gains
–40
–40
VO, dm = 2V p-p
G=1
VO, dm = 2V p-p
G=1
–50
DISTORTION (dBc)
–60
RF = 500Ω
–70
–80
RF = 2kΩ
–60
–70
–80
–90
–90
RF = 1kΩ
–110
0.1
–100
04771-0-030
–100
1
FREQUENCY (MHz)
RF = 500Ω
–110
0.1
10
RF = 2kΩ
RF = 1kΩ
1
FREQUENCY (MHz)
Figure 30. Third Harmonic Distortion at Various RF
Figure 27. Second Harmonic Distortion at Various RF
Rev. A | Page 11 of 24
04771-0-031
–50
DISTORTION (dBc)
G=5
04771-0-035
DISTORTION (dBc)
G=5
04771-0-034
DISTORTION (dBc)
G=2
–60
10
AD8137
–50
–50
FC = 500kHz
VO, dm = 2V p-p
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE
–60
DISTORTION (dBc)
–70
–80
–90
–110
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–80
–90
–100
04771-0-028
–100
–70
–110
0.5
4.5
04771-0-029
DISTORTION (dBc)
–60
FC = 500kHz
VO, dm = 2V p-p
SECOND HARMONIC SOLID LINE
THIRD HARMONIC DASHED LINE
0.7
0.9
1.1
VOCM (V)
Figure 31. Harmonic Distortion vs. VOCM, VS = +5 V
1.5
1.7
VOCM (V)
1.9
2.1
2.3
2.5
Figure 34. Harmonic Distortion vs. VOCM, VS = +3 V
1000
1
10
04771-0-046
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100
10
1
10
100M
04771-0-047
VOCM NOISE (nV/√Hz)
100
INPUT VOLTAGE NOISE (nV/√Hz)
1.3
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 35. VOCM Voltage Noise vs. Frequency
Figure 32. Input Voltage Noise vs. Frequency
–10
20
VIN, cm = 0.2V p-p
INPUT CMRR = ∆VO, cm/∆VIN, cm
10
VO, cm = 0.2V p-p
VOCM CMRR = ∆VO, dm/∆VOCM
–20
0
–30
VOCM CMRR (dB)
–20
–30
–40
–50
–40
–50
–60
–70
–80
1
10
FREQUENCY (MHz)
04771-0-012
–60
–70
04771-0-013
CMRR (dB)
–10
–80
1
100
10
FREQUENCY (MHz)
Figure 36. VOCM CMRR vs. Frequency
Figure 33. CMRR vs. Frequency
Rev. A | Page 12 of 24
100
AD8137
2.0
8
INPUT × 2
1.0
AMPLITUDE (V)
4
2
0
–2
0.5
0
ERROR = VO, dm - INPUT
–0.5
TSETTLE = 110ns
–1.0
–6
250ns/DIV
–8
04771-0-016
–4
–1.5
50ns/DIV
–2.0
ERROR (V) 1DIV = 0.02%
CF = 0pF
VO, dm = 3.5V p-p
INPUT
OUTPUT
VOLTAGE (V)
VO, dm
1.5
6
04771-0-040
G=2
TIME (ns)
TIME (ns)
Figure 40. Settling Time (0.02%)
Figure 37. Overdrive Recovery
100
1.5
75
CF = 0pF
CF = 1pF
CF = 0pF
CF = 1pF
25
1V p-p
VO, dm (V)
0.5
0
–25
CF = 1pF
0
–0.5
–75
VO, dm = 100mV p-p
10ns/DIV
–100
04771-0-015
–50
–1.0
20ns/DIV
–1.5
TIME (ns)
04771-0-014
CF = 0pF
VO, dm (mV)
2V p-p
1.0
50
TIME (ns)
Figure 38. Small Signal Transient Response for Various Feedback Capacitances
Figure 41. Large Signal Transient Response for Various Feedback Capacitances
100
1.5
75
RS = 111, CL = 5pF
1.0
50
RS = 111, CL = 5pF
0.5
VO, dm (V)
0
–25
RS = 60.4, CL = 15pF
RS = 60.4, CL = 15pF
0
–0.5
–75
20ns/DIV
–100
04771-0-039
–50
–1.0
20ns/DIV
–1.5
TIME (ns)
04771-0-038
VO, dm (V)
25
TIME (ns)
Figure 39. Small Signal Transient Response for Various Capacitive Loads
Figure 42. Large Signal Transient Response for Various Capacitive Loads
Rev. A | Page 13 of 24
AD8137
1000
–5
PSRR = ∆VO, dm/∆VS
–15
100
OUTPUT IMPEDANCE (Ω)
PSRR (dB)
–25
–35
–PSRR
–45
+PSRR
–55
–65
10
1
–85
0.1
1
10
FREQUENCY (MHz)
04771-0-061
04771-0-011
0.1
–75
0.01
0.01
100
Figure 43. PSRR vs. Frequency
0.1
1
10
FREQUENCY (MHz)
100
Figure 46. Single-Ended Output Impedance vs. Frequency
4.0
1
0
3.5
2V p-p
–3
3.0
–4
–5
VO, cm (V)
–6
–7
VS = +5
V S = ±5
–8
1V p-p
2.5
2.0
–9
VS = +3
–12
–13
–14
VO, dm = 0.1V p-p
1
1.5
04771-0-010
–11
10
100
FREQUENCY (MHz)
20ns/DIV
1.0
1000
TIME (ns)
Figure 47. VOCM Large Signal Transient Response
Figure 44. VOCM Small Signal Frequency Response for Various Supply Voltages
700
350
–300
345
–305
500
VOP SWING FROM RAIL (mV)
VS+ – VOP
400
300
200
100
0
VS = +5V
VS = +3V
–100
–200
–300
VON – VS–
–400
–500
–600
–700
200
1k
RESISTIVE LOAD (Ω)
VON – VS–
340
–310
335
–315
VS+ – VOP
330
–320
325
320
–40
10k
–325
–330
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 48. Output Saturation Voltage vs. Temperature
Figure 45. Output Saturation Voltage vs. Output Load
Rev. A | Page 14 of 24
VON SWING FROM RAIL (mV)
600
04771-0-049
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
04771-0-050
–10
04771-0-065
CLOSED-LOOP GAIN (dB)
–1
–2
AD8137
10
2.55
VOS, dm
0
0
–0.1
5
–0.2
10
–0.3
–40
VOS, cm (mV)
5
VOS, dm (mV)
0.1
–15
–20
0
20
40
60
TEMPERATURE (°C)
80
100
2.50
2.45
2.40
2.35
2.30
–40
120
Figure 49. Offset Voltage vs. Temperature
04771-0-051
VOS, cm
2.60
04771-0-052
0.2
15
SUPPLY CURRENT (mA)
0.3
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 52. Supply Current vs. Temperature
1.2
70
1.0
INPUT BIAS CURRENT (µA)
50
0.8
30
IVOCM (µA)
0.6
0.4
0.2
10
–10
–30
04771-0-059
0
–0.4
0.50
1.50
2.50
VACM (V)
3.50
–50
04771-0-056
–0.2
–70
4.50
0
Figure 50. Input Bias Current vs. Input Common-Mode Voltage, VACM
0.40
1.0
1.5
2.0
2.5
3.0
VOCM (V)
3.5
4.0
4.5
5.0
Figure 53. VOCM Bias Current vs. VOCM Input Voltage
3
0.35
0.5
–0.1
2
IBIAS
0
IOS
0.20
–1
0.15
–2
IOS (nA)
0.25
–0.3
–0.4
–3
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–0.5
–40
120
Figure 51. Input Bias and Offset Current vs. Temperature
04771-0-054
0.10
–40
04771-0-053
IBIAS (µA)
1
VOCM CURRENT (µA)
–0.2
0.30
–20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 54. VOCM Bias Current vs. Temperature
Rev. A | Page 15 of 24
120
AD8137
1.5
VS = +5V
VS = ±2.5V
G = 1 (RF = RG = 1kΩ)
RL, dm = 1kΩ
INPUT = 1Vp-p @ 1MHz
4
1.0
SUPPLY CURRENT (mA)
3
2
VS = +3V
VO, cm
1
0
–1
VS = ±5V
–2
–3
–5
–5
–4
–3
–2
–1
0
VOCM
1
2
3
4
0
–0.5
–1.0
04771-0-060
–4
VO, dm
0.5
–0.5V
PD
2µs/DIV
–2.0V
–1.5
04771-0-066
5
5
TIME (µs)
Figure 55. VO, cm vs. VOCM Input Voltage
Figure 58. Power-Down Transient Response
40
3.6
20
3.2
PD (0.8V TO 1.5V)
2.8
SUPPLY CURRENT (mA)
–20
–40
–60
–80
2.4
2.0
1.6
1.2
04771-0-057
0.8
–100
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
PD VOLTAGE (V)
3.5
4.0
4.5
0.4
100ns/DIV
0
04771-0-024
PD CURRENT (µA)
0
5.0
TIME (ns)
Figure 59. Power-Down Turn-On Time
Figure 56. PD Current vs. PD Voltage
3.4
3
PD (1.5V TO 0.8V)
IS+
3.0
0
–1
–2
IS –
–3
0
0.5
1.0
1.5
2.0
2.5
3.0
PD VOLTAGE (V)
3.5
4.0
4.5
2.6
2.2
1.8
1.4
1.0
0.6
40ns/DIV
0.2
5.0
TIME (ns)
Figure 60. Power-Down Turn-Off Time
Figure 57. Supply Current vs. PD Voltage
Rev. A | Page 16 of 24
04771-0-025
SUPPLY CURRENT (mA)
1
04771-0-058
SUPPLY CURRENT (mA)
2
AD8137
THEORY OF OPERATION
100
The AD8137 is a low power, low cost, fully differential voltage
feedback amplifier that features a rail-to-rail output stage,
common-mode circuitry with an internally derived commonmode reference voltage, and bias shutdown circuitry. The amplifier uses two feedback loops to separately control differential
and common-mode feedback. The differential gain is set with
external resistors as in a traditional amplifier while the output
common-mode voltage is set by an internal feedback loop,
controlled by an external VOCM input. This architecture makes it
easy to arbitrarily set the output common-mode voltage level
without affecting the differential gain of the amplifier.
80
60
40
20
OPEN-LOOP GAIN (dB)
0
–20
–40
–60
–80
–100
PHASE (DEGREES)
–120
04771-0-021
–140
–160
–180
–200
0.0001
VOCM
0.001
0.01
0.1
1
FREQUENCY (MHz)
10
100
Figure 62. Open-Loop Gain and Phase
ACM
–OUT
CP +IN
+OUT
CC
04771-0-017
CC
–IN CN
Figure 61. Block Diagram
From Figure 61, the input transconductance stage is an
H-bridge whose output current is mirrored to high impedance
nodes CP and CN. The output section is traditional H-bridge
driven circuitry with common emitter devices driving nodes
+OUT and −OUT. The 3 dB point of the amplifier is defined as
BW =
gm
2π × CC
where gm is the transconductance of the input stage and CC is
the total capacitance on node CP/CN (capacitances CP and CN
are well matched). For the AD8137, the input stage gm is
~1 mA/V and the capacitance CC is 3.5 pF, setting the crossover
frequency of the amplifier at 41 MHz. This frequency generally
establishes an amplifier’s unity gain bandwidth, but with the
AD8137, the closed-loop bandwidth depends upon the
feedback resistor value as well (see Figure 19). The open-loop
gain and phase simulations are shown in Figure 62.
In Figure 61, the common-mode feedback amplifier ACM
samples the output common-mode voltage, and by negative
feedback forces the output common-mode voltage to be equal
to the voltage applied to the VOCM input. In other words, the
feedback loop servos the output common-mode voltage to the
voltage applied to the VOCM input. An internal bias generator
sets the VOCM level to approximately midsupply, therefore, the
output common-mode voltage will be set to approximately
midsupply when the VOCM input is left floating. The source resistance of the internal bias generator is large and can be overridden easily by an external voltage supplied by a source with a
relatively small output resistance. The VOCM input can be driven
to within approximately 1 V of the supply rails while maintaining linear operation in the common-mode feedback loop.
The common-mode feedback loop inside the AD8137 produces
outputs that are highly balanced over a wide frequency range
without the requirement of tightly matched external components because it forces the signal component of the output
common-mode voltage to be zeroed. The result is nearly
perfectly balanced differential outputs of identical amplitude
and exactly 180° apart in phase.
Rev. A | Page 17 of 24
AD8137
APPLICATIONS
ANALYZING A TYPICAL APPLICATION WITH
MATCHED RF AND RG NETWORKS
Typical Connection and Definition of Terms
Figure 63 shows a typical connection for the AD8137, using
matched external RF/RG networks. The differential input
terminals of the AD8137, VAP and VAN, are used as summing
junctions. An external reference voltage applied to the VOCM
terminal sets the output common-mode voltage. The two
output terminals, VOP and VON, move in opposite directions in a
balanced fashion in response to an input signal.
Output balance is measured by placing a well matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differentialmode voltage:
Output Balance =
VAN = VAP
RF
VIP
VAP
VOCM
VIN
VON
+
AD8137
RG
VAN
–
+
04771-0-055
RF
CF
(4)
The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two internal
common-mode tap resistors in Figure 61, to equal the voltage
set at the VOCM terminal. This ensures that
RL, dm VO, dm
VOP
–
(3)
∆VO , dm
The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other.
CF
RG
∆VO , cm
VOP = VOCM +
VO , dm
(5)
2
Figure 63. Typical Connection
and
The differential output voltage is defined as
VO, dm = VOP − VON
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
VO , cm =
VOP + VON
2
VON = VOCM −
(1)
VO , dm
(6)
2
ESTIMATING NOISE, GAIN, AND BANDWITH WITH
MATCHED FEEDBACK NETWORKS
Estimating Output Noise Voltage and Bandwidth
(2)
Output Balance
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180 degrees
out of phase with each other. It is the internal common-mode
feedback loop that forces the signal component of the output
common-mode towards zero, resulting in the near perfectly
balanced differential outputs of identical amplitude and exactly
180 degrees out of phase. The output balance performance does
not require tightly matched external components, nor does it
require that the feedback factors of each loop be equal to each
other. Low frequency output balance is limited ultimately by the
mismatch of an on-chip voltage divider.
The total output noise is the root-sum-squared total of several
statistically independent sources. Since the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 7 lists
recommended resistor values and estimates of bandwidth and
output differential voltage noise for various closed-loop gains.
For most applications, 1% resistors are sufficient.
Table 7. Recommended Values of Gain-Setting Resistors, and
Voltage Gain for Various Closed-Loop Gains
Gain
1
2
5
10
RG (Ω)
1k
1k
1k
1k
RF (Ω)
1k
2k
5k
10 k
3 dB
Bandwidth (MHz)
72
40
12
6
Total Output
Noise (nV/√Hz)
18.6
28.9
60.1
112.0
The differential output voltage noise contains contributions
from the AD8137’s input voltage noise and input current noise
as well as those from the external feedback networks.
Rev. A | Page 18 of 24
AD8137
The contribution from the input voltage noise spectral density
is computed as
⎛ R ⎞
Vo_n 1 = vn ⎜1 + F ⎟ , or equivalently, vn/β
⎝ RG ⎠
(7)
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
The contribution from the input current noise of each input is
computed as
Vo_n 2 = in (RF )
(8)
where in is defined as the input noise current of one input. Each
input needs to be treated separately since the two input currents
are statistically independent processes.
β≡
Input Common-Mode Voltage
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Since VAN and VAP are
essentially equal to each other, they are both equal to the amplifier’s input common-mode voltage. Their range is indicated in
the specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure 63
can be expressed as
VAN = VAP = VACM =
(V + VIN ) ⎞ ⎛ RG
⎛ RF
⎞
× IP
× VOCM ⎟
⎜
⎟+⎜
2
⎝ RF + RG
⎠ ⎝ RF + RG
⎠
⎛R ⎞
Vo_n 3 = 4 kTRG ⎜ F ⎟
⎝ RG ⎠
(9)
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
(15)
where VACM is the common-mode voltage present at the amplifier input terminals.
Using the β notation, Equation (15) can be written as
VACM = βVOCM + (1 − β )VICM
The contribution from each RF is computed as
(10)
The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the signal
definitions and Figure 63. Referring to Figure 63, (CF = 0) and
setting VIN = 0 one can write:
VIP − VAP VAP − VON
=
RG
RF
(11)
⎡ RG ⎤
VAN = VAP = VOP ⎢
⎥
⎣ RF + RG ⎦
(12)
(16)
or equivalently,
VACM = VICM + β(VOCM − VICM )
Voltage Gain
(17)
where VICM is the common-mode voltage of the input signal, i.e.,
VIP + VIN
.
VICM ≡
2
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
Calculating Input Impedance
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
R
VOP − VON = VO, dm = F Vi
RG
(14)
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
The contribution from each RG is computed as
Vo_n 4 = 4 kTRF
RG
RF + RG
The input impedance of the circuit in Figure 63 will depend on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input signals,
the differential input impedance (RIN, dm) is simply
RIN, dm = 2RG
(18)
(13)
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
For a single-ended signal (for example, when VIN is grounded,
and the input signal drives VIP), the input impedance becomes
Feedback Factor Notation
When working with differential drivers, it is convenient to introduce the feedback factor β, which is defined as
Rev. A | Page 19 of 24
R IN =
RG
RF
1−
2(RG + RF )
(19)
AD8137
5V
0.1µF
0.1µF
1kΩ
1kΩ
VOCM
3
8
2
1
VIN
1.0nF
5
+
VDD
VIN–
AD8137
–
AD7450A
4
6
VREFB
2.5V
1kΩ
1kΩ
50Ω
VIN+
GND
1.0nF
VREF
2.5kΩ
+1.88V
+1.25V
+0.63V
VACM WITH
VREFB = 0
ADR525A
2.5V SHUNT
VREFA REFERENCE
04771-0-018
+2.5V
GND
–2.5V
50Ω
Figure 64. AD8137 Driving AD7450A, 12-Bit A/D Converter
5V
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to the
increased input resistance.
0.1µF
VIN
0V TO 5V
1kΩ
3
1kΩ
8
VOCM
2
1
Input Common-Mode Swing Considerations
5
+
AD8137
–
4
6
1kΩ
1kΩ
TO
AD7450A
VREF
5V
0.1µF
0.1µF
Consider the case in Figure 64, where VIN is 5 V p-p swinging
about a baseline at ground and VREFB is connected to ground.
The input signal to the AD8137 is originating from a source
with a very low output resistance.
The circuit has a differential gain of 1.0 and β = 0.5. VICM has an
amplitude of 2.5 V p-p and is swinging about ground. Using the
results in Equation 16, the common-mode voltage at the AD8137’s
inputs, VACM, is a 1.25 V p-p signal swinging about a baseline of 1.25
V. The maximum negative excursion of VACM in this case is 0.63 V,
which exceeds the lower input common-mode voltage limit.
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V, and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM is
calculated to be equal to VICM because VOCM = VICM. Therefore,
VICM swings from 1.25 V to 3.75 V, which is well within the input
common-mode voltage limits of the AD8137. Another benefit
seen by this example is that since VOCM = VACM = VICM, no wasted
common-mode current flows. Figure 65 illustrates a way to
provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider will suffice
to develop the input voltage to the buffer.
10µF
+
+
AD8031
0.1µF
–
10kΩ
ADR525A
2.5V SHUNT
REFERENCE
04771-0-019
In some single-ended-to-differential applications when using a
single-supply voltage, attention must be paid to the swing of the
input common-mode voltage, VACM.
Figure 65. Low-Z Bias Source
Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8137. In this case,
the biasing circuitry is not required.
Bandwidth Versus Closed-Loop Gain
The AD8137’s 3 dB bandwidth will decrease proportionally to
increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
f −3dB , VO, dm =
RG
× (72MHz)
RG + R F
(20)
or equivalently, β(72 MHz).
This estimate assumes a minimum 90 degree phase margin for
the amplifier loop, a condition approached for gains greater
than 4. Lower gains will show more bandwidth than predicted
by the equation due to the peaking produced by the lower phase
margin.
Rev. A | Page 20 of 24
AD8137
Estimating DC Errors
Driving a Capacitive Load
Primary differential output offset errors in the AD8137 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
A purely capacitive load will react with the bondwire and pin
inductance of the AD8137, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance. The resistor and load
capacitance will form a first-order, low-pass filter, so the resistor
value should be as small as possible. In some cases, the ADCs
require small series resistors to be added on their inputs.
The first output error component is calculated as
⎛ R + RG ⎞
Vo_e1 = VIO ⎜ F
⎟ , or equivalently as VIO/β
⎝ RG ⎠
(21)
Layout Considerations
where VIO is the input offset voltage.
The second error is calculated as
⎛ R + RG ⎞⎛ RG RF ⎞
Vo_e 2 = I IO ⎜ F
⎟ = I IO (RF )
⎟⎜
⎝ RG ⎠⎝ RF + RG ⎠
(22)
where IIO is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
Vo_e 3 = ∆enr × (VICM − VOCM )
Figure 39 and Figure 42 illustrate transient response versus capacitive load, and were generated using series resistors in each
output and a differential capacitive load.
(23)
where Δenr is the fractional mismatch between the two feedback resistors.
The total differential offset error is the sum of these three error
sources.
Additional Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network will still force
the output voltages to remain balanced, even when the RF/RG
feedback networks are mismatched. The mismatch will, however, cause a gain error proportional to the feedback network
mismatch.
Ratio-matching errors in the external resistors will degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors will also produce a differential output component that is
equal to the VOCM input voltage times the difference between the
feedback factors (βs). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.
Standard high speed PCB layout practices should be adhered to
when designing with the AD8137. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to the
summing nodes should be removed. Small amounts of stray
summing-node capacitance will cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section
deals with how to properly terminate a single-ended input to
the AD8137.
The input resistance presented by the AD8137 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires solution of several simultaneous algebraic equations and is beyond the scope of this data
sheet. An iterative solution is also possible and is simpler,
especially considering the fact that standard resistor values are
generally used.
Figure 66 shows the AD8137 in a unity-gain configuration, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
Rev. A | Page 21 of 24
AD8137
+5V
the gain reduction produced by the increase in RG is essentially
cancelled by the increase in the Thevenin voltage caused by RT
being greater than the output resistance of the signal source. In
general, as RF and RG become smaller in terminated applications,
RF needs to be increased to compensate for the increase in RG.
0.1µF
1kΩ
2V p-p
VIN
SIGNAL
SOURCE
RT
52.3Ω
0V
1kΩ
–
8
VOCM
2
1
5
+
When generating the typical performance characteristics data,
the measurements were calibrated to take the effects of the
terminations on closed-loop gain into account.
AD8137
–
4
6
1.02kΩ
Power Down
+
04771-0-020
1kΩ
0.1µF
–5V
The AD8137 features a PD pin that can be used to minimize the
quiescent current consumed when the device is not being used.
PD is asserted by applying a low logic level to Pin 7. The
threshold between high and low logic levels is nominally 1.1 V
above the negative supply rail. See the Specification tables for
the threshold limits.
Figure 66. AD8137 with Terminated Input
The 52.3 Ω termination resistor, RT, in parallel with the 1 kΩ
input resistance of the AD8137 circuit, yields an overall input
resistance of 50 Ω that is seen by the signal source. In order to
have matched feedback loops, each loop must have the same RG
if they have the same RF. In the input (upper) loop, RG is equal
to the 1 kΩ resistor in series with the (+) input plus the parallel
combination of RT and the source resistance of 50 Ω. In the
upper loop, RG is therefore equal to 1.03 kΩ. The closest standard value is 1.02 kΩ and is used for RG in the lower loop.
DRIVING AN ADC WITH GREATER THAN 12-BIT
PERFORMANCE
Since the AD8137 is suitable for 12-bit systems, it is desirable to
measure the performance of the amplifier in a system with
greater than 12-bit linearity. In particular, the effective number
of bits, ENOB, is most interesting. The AD7687, 16-bit,
250 KSPS ADC’s performance makes it an ideal candidate for
showcasing the 12-bit performance of the AD8137.
Things get more complicated when it comes to determining the
feedback resistor values. The amplitude of the signal source
generator VIN is two times the amplitude of its output signal
when terminated in 50 Ω. Therefore, a 2 V p-p terminated
amplitude is produced by a 4 V p-p amplitude from VS. The
Thevenin equivalent circuit of the signal source and RT must be
used when calculating the closed-loop gain because RG in the
upper loop is split between the 1 kΩ resistor and the Thevenin
resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output
voltage when terminated in 50 Ω because RT must always be
greater than 50 Ω. In this case, RT is 52.3 Ω and the Thevenin
voltage and resistance are 2.04 V p-p and 25.6 Ω, respectively.
Now the upper input branch can be viewed as a 2.04 V p-p
source in series with 1.03 kΩ. Since this is to be a unity-gain
application, a 2 V p-p differential output is required, and RF
must therefore be 1.03 kΩ × (2/2.04) = 1.01 kΩ ≈ 1 kΩ. This
example shows that when RF and RG are large compared to RT,
For this application, the AD8137 is set in a gain of 2 and driven
single-ended through a 20 kHz band-pass filter, while the output
is taken differentially to the input of the AD7687 (see Figure 67).
This circuit has mismatched RG impedances and, therefore, has a
dc offset at the differential output. It is included as a test circuit to
illustrate the performance of the AD8137. Actual application
circuits should have matched feedback networks.
For an AD7687 input range up to −1.82 dBFS, the AD8137 power
supply is a single 5 V applied to VS+ with VS− tied to ground. To
increase the AD7687 input range to −0.45 dBFS, the AD8137
supplies are increased to +6 V and −1 V. In both cases, the VOCM
pin is biased with 2.5 V and the PD pin is left floating. All voltage
supplies are decoupled with 0.1 µF capacitors. Figure 68 and
Figure 69 show the performance of the −1.82 dBFS setup and the
−0.45 dBFS setup, respectively.
VS+
1.0kΩ
20kHz
V+
GND
33Ω
499Ω
VIN
+
BPF
VOCM
1nF
AD8137
GND
–
33Ω
499Ω
1.0kΩ
+2.5
VDD
AD7687
VS–
Figure 67. AD8137 Driving AD7687, 16-Bit 250 KSPS ADC
Rev. A | Page 22 of 24
1nF
04771-0-067
50Ω
3
0
–10
AMPLITUDE (dB OF FULL SCALE)
THD = –93.63dBc
SNR = 91.10dB
SINAD = 89.74dB
ENOB = 14.6
0
20
40
60
80
FREQUENCY (kHz)
100
120
140
THD = –91.75dBc
SNR = 91.35dB
SINAD = 88.75dB
ENOB = 14.4
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
04771-0-069
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
04771-0-068
AMPLITUDE (dB OF FULL SCALE)
AD8137
0
Figure 68. AD8137 Performance on Single 5 V Supply, −1.82 dBFS
20
40
60
80
FREQUENCY (kHz)
100
120
140
Figure 69. AD8137 Performance on +6 V, −1 V Supplies, −0.45 dBFS
Rev. A | Page 23 of 24
AD8137
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 70. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)—Dimensions shown in millimeters (inches)
3.00
BSC SQ
0.60 MAX
0.50
0.40
0.30
0.45
1
8
PIN 1
INDICATOR
0.90
0.85
0.80
TOP
VIEW
2.75
BSC SQ
0.50
BSC
0.25
MIN
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
1.50
REF
EXPOSED
PAD
(BOTTOM VIEW)
5
1.90
1.75
1.60
4
1.60
1.45
1.30
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body (CP-8-2)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8137YR
AD8137YR-REEL
AD8137YR-REEL7
AD8137YRZ1
AD8137YRZ-REEL1
AD8137YRZ-REEL71
AD8137YCP-R2
AD8137YCP-REEL
AD8137YCP-REEL7
AD8137YCPZ-R21
AD8137YCPZ-REEL1
AD8137YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D04771–0–8/04(A)
Rev. A | Page 24 of 24
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
Branding
HFB
HFB
HFB
HGB
HGB
HGB