AD OP467AY/883 Quad precision, high speed operational amplifier Datasheet

a
Quad Precision, High Speed
Operational Amplifier
OP467
FEATURES
High Slew Rate – 170 V/␮s
Wide Bandwidth – 28 MHz
Fast Settling Time – <200 ns to 0.01%
Low Offset Voltage – <500 ␮V
Unity-Gain Stable
Low Voltage Operation ⴞ5 V to ⴞ15 V
Low Supply Current – <10 mA
Drives Capacitive Loads
PIN CONNECTIONS
14-Lead Ceramic DIP (Y Suffix) and
14-Lead Epoxy DIP (P Suffix)
OUT A 1
V+ 4
The dc performance of OP467 includes less than 0.5 mV of
offset, voltage noise density below 6 nV/√Hz and total supply
current under 10 mA. Common-mode rejection and power
supply rejection ratios are typically 85 dB. PSRR is maintained
to better than 40 dB with input frequencies as high as 1 MHz.
The low offset and drift plus high speed and low noise, make the
OP467 usable in applications such as high speed detectors and
instrumentation.
12 +IN D
OP467
10 +IN C
+IN B 5
–IN B 6
+
+
OUT B 7
–IN C
8
OUT C
2
15 –IN D
+IN A
3
14 +IN D
V+
4
13 V–
NC 5
+IN B
5
12 +IN C
V+ 6
–IN B
6
11 –IN C
NC 7
OUT B
7
10 OUT C
NC
8
3
2
1
20 19
–IN D
–IN A
NC
16 OUT D
OUT D
1
–IN A
20-Position Chip Carrier
(RC Suffix)
OUT A
18 +IN D
+IN A 4
17 NC
OP467
16 V–
(TOP VIEW)
15 NC
14 +IN C
+IN B 8
NC = NO CONNECT
9
10 11 12 13
–IN C
NC
NC
9
9
OUT A
16-Lead SOL
(S Suffix)
OP467
11 V–
OUT C
The OP467’s internal compensation ensures stable unity-gain
operation, and it can drive large capacitive loads without oscillation. With a gain bandwidth product of 28 MHz driving a 30 pF
load, output slew rate in excess of 170 V/µs, and settling time to
0.01% in less than 200 ns, the OP467 provides excellent dynamic accuracy in high speed data-acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.
13 –IN D
+
–IN B
The OP467 is a quad, high speed, precision operational amplifier. It offers the performance of a high speed op amp combined
with the advantages of a precision operational amplifier all in a
single package. The OP467 is an ideal choice for applications
where, traditionally, more than one op amp was used to achieve
this level of speed and precision.
14 OUT D
+
+IN A 3
APPLICATIONS
High Speed Image Display Drivers
High Frequency Active Filters
Fast Instrumentation Amplifiers
High Speed Detectors
Integrators
Photo Diode Preamps
GENERAL DESCRIPTION
2
OUT B
–IN A
NC = NO CONNECT
V+
+IN
OUT
–IN
The OP467 is specified for operation from ± 5 V to ± 15 V over
the extended industrial temperature range (–40°C to +85°C) and
is available in 14-lead plastic and ceramic DIP, plus SOL-16
and 20-lead LCC surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet and
availability.
V–
Figure 1. Simplified Schematic
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
OP467–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15.0 V, TA = +25ⴗC unless otherwise noted)
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
IB
Input Offset Current
IOS
Common-Mode Rejection
Large Signal Voltage Gain
CMR
CMR
AVO
Offset Voltage Drift
Bias Current Drift
Long Term Offset Voltage Drift
∆VOS/∆T
∆IB/∆T
∆VOS/∆T
Min
–40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, –40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, –40°C ≤ TA ≤ +85°C
VCM = ± 12 V
VCM = ± 12 V, –40°C ≤ TA ≤ +85°C
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
80
80
83
77.5
Typ
Max
Units
0.2
0.5
1
600
700
100
150
mV
mV
nA
nA
nA
nA
dB
dB
dB
dB
µV/°C
pA/°C
µV
150
150
10
10
90
88
86
3.5
0.2
Note 1
750
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
± 13.0
± 12.9
± 13.5
± 13.12
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
± 4.5 V ≤ VS = ± 18 V
–40°C ≤ TA ≤ +85°C
VO = 0 V
VO = 0 V, –40°C ≤ TA ≤ +85°C
96
86
120
115
8
dB
dB
mA
mA
V
Supply Current
ISY
Supply Voltage Range
VS
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
Full-Power Bandwidth
Settling Time
Phase Margin
Input Capacitance
Common Mode
Differential
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
GBP
SR
BWρ
tS
θ0
eN p-p
eN
iN
AV = +1, CL = 30 pF
VIN = 10 V Step, RL = 2 kΩ, CL = 30 pF
AV = +1
AV = –1
VIN = 10 V Step
To 0.01%, VIN = 10 V Step
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
± 4.5
125
10
13
± 18
28
MHz
170
350
2.7
200
45
V/µs
V/µs
MHz
ns
Degrees
2.0
1.0
pF
pF
0.15
6
8
µV p-p
nV/√Hz
pA/√Hz
NOTE
1
Long Term Offset Voltage Drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
–2–
REV. C
OP467
ELECTRICAL CHARACTERISTICS (@ V = ⴞ5.0 V, T = +25ⴗC unless otherwise noted)
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
IB
Input Offset Current
IOS
Common-Mode Rejection
Large Signal Voltage Gain
CMR
CMR
AVO
Offset Voltage Drift
Bias Current Drift
∆VOS/∆T
∆IB/∆T
A
Conditions
–40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, –40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, –40°C ≤ TA ≤ +85°C
VCM = ± 2.0 V
VCM = ± 2.0 V, –40°C ≤ TA ≤ +85°C
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
Min
Typ
Max
Units
0.3
0.5
1
600
700
100
150
35
0.2
mV
mV
nA
nA
nA
nA
dB
dB
dB
dB
µV/°C
pA/°C
125
150
20
76
76
80
74
85
80
83
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
± 3.0
± 3.0
± 3.5
± 3.20
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
± 4.5 V ≤ VS = ± 5.5 V
–40°C ≤ TA ≤ +85°C
VO = 0 V
VO = 0 V, –40°C ≤ TA ≤ +85°C
92
83
107
105
8
dB
dB
mA
mA
Supply Current
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
Full-Power Bandwidth
Settling Time
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
ISY
GBP
SR
BWρ
tS
θ0
eN p-p
eN
iN
AV = +1
VIN = 5 V Step, RL = 2 kΩ, CL = 39 pF
AV = +1
AV = –1
VIN = 5 V Step
To 0.01%, VIN = 5 V Step
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Specifications subject to change without notice.
REV. C
–3–
10
11
22
MHz
90
90
2.5
280
45
V/µs
V/µs
MHz
ns
Degrees
0.15
7
8
µV p-p
nV/√Hz
pA/√Hz
OP467
WAFER TEST LIMITS1 ( @ V = ⴞ15.0 V, T = +25ⴗC unless otherwise noted.)
S
A
Parameter
Symbol
Conditions
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range2
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current
VOS
IB
IOS
VCM = 0 V
VCM = 0 V
CMRR
PSRR
AVO
VO
ISY
VCM = ± 12 V
V = ± 4.5 V to ± 18 V
RL = 2 kΩ
RL = 2 kΩ
VO = 0 V, RL = ∞
Limit
Units
± 0.5
600
100
± 12
80
96
83
± 13.0
10
mV max
nA max
nA max
V min/max
dB min
dB min
dB min
V min
mA max
NOTES
1
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2
Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 26 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . Limited
Storage Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP467A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP467G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
␪A3
␪JC
Units
14-Lead Cerdip (Y)
14-Lead Plastic DIP (P)
16-Lead SOL (S)
20-Contact LCC (RC)
94
76
88
78
10
33
23
33
°C/W
°C/W
°C/W
°C/W
Model
Temperature
Ranges
Package
Descriptions
Package
Options
OP467AY/883
OP467ARC/883
OP467GP
OP467GS
OP467GBC
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
+25°C
14-Lead Cerdip
20-Contact LCC
14-Lead Plastic DIP
16-Lead SOL
DICE
Q-14
E-20A
N-14
R-16
DICE CHARACTERISTICS
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.
3
θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit
board for SOIC package.
OP467 Die Size 0.111 ⫻ 0.100 inch, 11,100 sq. mils Substrate is Connected to V+, Number of Transistors 165.
–4–
REV. C
Typical Performance Characteristics– OP467
80
100
VS = 615V
RL = 1MV
CL = 30pF
70
60
VS = 615V
TA = +258C
30
PHASE
20
0
10
90
0
180
IMPEDANCE – V
OPEN-LOOP GAIN – dB
40
PHASE SHIFT – Degrees
80
GAIN
50
60
AVCL = +100
40
AVCL = +10
20
–10
AVCL = +1
–20
1k
10k
100k
1M
10M
0
100
100M
1k
FREQUENCY – Hz
Figure 2. Open-Loop Gain, Phase vs. Frequency
10k
FREQUENCY – Hz
100k
1M
Figure 5. Closed-Loop Output Impedance vs. Frequency
80
VS = 615V
TA = +258C
0.3
GAIN ERROR – dB
CLOSED-LOOP GAIN – dB
60
40
20
0.2
VS = 65
0.1
VS = 615
0.0
–0.1
–0.2
0
–0.3
–20
10k
100k
1M
FREQUENCY – Hz
10M
100M
100k
3.4
1M
5.8
10M
FREQUENCY – Hz
Figure 3. Closed-Loop Gain vs. Frequency
Figure 6. Gain Linearity vs. Frequency
30
25
MAXIMUM OUTPUT SWING – Volts
AVCL = –1
OPEN-LOOP GAIN – V/mV
20
15
TA = +1258C
TA = +258C
10
TA = –558C
5
0
0
65
610
615
SUPPLY VOLTAGE – Volts
AVCL = +1
20
15
10
5
0
1k
620
VS = 615V
TA = +258C
RL = 2kV
10k
100k
1M
FREQUENCY – Hz
Figure 4. Open-Loop Gain vs. Supply Voltage
REV. C
25
Figure 7. Max VOUT Swing vs. Frequency
–5–
10M
OP467
10
60
VS = 65V
TA = +258C
RL = 2kV
AVCL = –1
8
AVCL = –1
6
4
40
30
20
10
2
0
10k
100k
FREQUENCY – Hz
1M
0
10M
Figure 8. Max VOUT Swing vs. Frequency
120
200
400
600
800
1000
1200
LOAD CAPACITANCE – pF
1400
1600
Figure 11. Small Signal Overshoot vs. Load Capacitance
60
VS = 615V
TA = +258C
100
VS = 65V
RL = 2kV
VIN = 100mV p-p
50
AVCL = +1
AVCL = –1
OVERSHOOT – %
80
60
40
40
30
20
10
20
0
1k
0
10k
100k
1M
0
10M
200
400
FREQUENCY – Hz
Figure 9. Common-Mode Rejection vs. Frequency
120
600
800
1000
1200
LOAD CAPACITANCE – pF
1400
1600
Figure 12. Small Signal Overshoot vs. Load Capacitance
60
VS = 615V
TA = +258C
VS = 615V
50
100
40
30
80
GAIN – dB
POWER SUPPLY REJECTION – dB
AVCL = +1
AVCL = +1
0
1k
COMMON-MODE REJECTION – Volts
VS = 615V
RL = 2kV
VIN = 100mV p-p
50
OVERSHOOT – %
MAXIMUM OUTPUT SWING – Volts
12
60
40
1000pF
20
10
200pF
0
–10
–20
20
CIN = NETWORK
ANALYZER
–30
0
100
500pF
10000pF
1k
10k
FREQUENCY – Hz
100k
–40
10k
1M
100k
1M
10M
100M
FREQUENCY – Hz
Figure 10. Power-Supply Rejection vs. Frequency
Figure 13. Noninverting Gain vs. Capacitive Loads
–6–
REV. C
OP467
4
0
VS = 615V
–10
VS = 615V
VIN = 65V
CL = 50pF
3
CHANNEL SEPARATION – dB
–20
2
VOUT ERROR – mV
–30
–40
–50
–60
1
0
–1
–70
–2
–80
–3
–90
–100
100
–4
1k
10k
100k
1M
FREQUENCY – Hz
10M
0
100M
Figure 14. Channel Separation vs. Frequency
200
300
TIME – ns
400
500
Figure 17. Settling Time, Negative Edge
12
4
65V # VS # 15V
INPUT CURRENT NOISE DENSITY – pA/ Hz
100
VS = 615V
VIN = 65V
CL = 50pF
3
10
VOUT ERROR – mV
2
8
6
4
1
0
–1
–2
2
–3
0
–4
1
10
100
FREQUENCY – Hz
0
1k
100
200
300
TIME – ns
400
500
Figure 18. Settling Time, Positive Edge
Figure 15. Input Current Noise Density vs. Frequency
20
100
TA = +258C
INPUT VOLTAGE RANGE – Volts
nV/ Hz
15
10
10
5
0
–5
–10
–15
1.0
0.1
–20
1
10
100
FREQUENCY – Hz
1k
10k
65
610
615
620
SUPPLY VOLTAGE – Volts
Figure 19. Input Voltage Range vs. Supply Voltage
Figure 16. Voltage Noise Density vs. Frequency
REV. C
0
–7–
OP467
50
500
VS1 = 615V
VS2 = 65V
RL = 10kV
CL = 50pF
40
30
VS = 615V
TA = +258C
1252 3 OP AMPS
400
300
10
UNITS
GAIN – dB
20
0
–10
200
VS2 = 65V
–20
VS1 = 615V
–30
100
–40
–50
10k
100k
1M
FREQUENCY – Hz
10M
0
–100
100M
50
100
150
200
250
300
350
400
Figure 23. Input Offset Voltage Distribution
500
VS = 615V
TA = +258C
VS = 65V
TA = +258C
1252 3 OP AMPS
12
400
10
POSITIVE
SWING
300
8
UNITS
OUTPUT SWING – Volts
0
INPUT OFFSET VOLTAGE – VOS mV
Figure 20. Noninverting Gain vs. Supply Voltage
14
–50
NEGATIVE
SWING
6
200
4
100
2
0
10
100
1k
LOAD RESISTANCE – V
0
–100
10k
50
100
150
200
250
300
350
400
Figure 24. Input Offset Voltage Distribution
500
VS = 65V
TA = +258C
4
VS = 615V
TA = +258C
1252 3 OP AMPS
400
POSITIVE
SWING
3
300
UNITS
OUTPUT SWING – Volts
0
INPUT OFFSET VOLTAGE – VOS mV
Figure 21. Output Swing vs. Load Resistance
5
–50
NEGATIVE
SWING
2
200
1
100
0
0
10
100
1k
LOAD RESISTANCE – V
10k
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TC VOS – mV/8C
Figure 22. Output Swing vs. Load Resistance
Figure 25. TC VOS Distribution
–8–
REV. C
OP467
500
400
VS = 65V
TA = +258C
1252 3 OP AMPS
400
VS = 65V
RL = 2kV
AVCL = +1
350
SLEW RATE – V/ms
300
UNITS
300
200
250
200
150
+SR
100
–SR
100
50
0
–75
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–50
–25
TC VOS – mV/8C
Figure 26. TC VOS Distribution
29.0
100
125
28.5
50
28.0
FM
45
27.5
VS = 615V
RL = 2kV
AVCL = –1
600
–SR
550
SLEW RATE – V/ms
VS = 615V
RL = 2kV
650
GAIN BANDWIDTH PRODUCT – MHz
GBW
PHASE MARGIN – Degrees
75
Figure 29. Slew Rate vs. Temperature
60
55
0
25
50
TEMPERATURE – 8C
500
+SR
450
400
350
300
40
–75
–50
–25
0
25
50
75
100
250
–75
27.0
125
–50
–25
TEMPERATURE – 8C
Figure 27. Phase Margin and Gain Bandwidth vs.
Temperature
100
125
400
VS = 65V
RL = 2kV
AVCL = –1
350
VS = 615V
RL = 2kV
AVCL = +1
350
300
300
250
SLEW RATE – V/ms
SLEW RATE – V/ms
75
Figure 30. Slew Rate vs. Temperature
400
–SR
200
+SR
150
+SR
250
200
100
50
50
0
–75
–50
–25
0
25
50
TEMPERATURE – 8C
75
100
–SR
150
100
0
–75
125
Figure 28. Slew Rate vs. Temperature
REV. C
0
25
50
TEMPERATURE – 8C
–50
–25
0
25
50
TEMPERATURE – 8C
75
100
Figure 31. Slew Rate vs. Temperature
–9–
125
OP467
200
5
RF = 5kV
TA = +258C
VS = 615V
4
0.01%
6
3
0.1%
4
2
2
1
0
0
–2
–5
–4
–4
0.1%
–6
0.01%
–3
–2
–8
–10
0
100
200
SETTLING TIME – ns
300
INPUT BIAS CURRENT – nA
8
OUTPUT STEP FOR 65V SUPPLY – Volts
OUTPUT STEP FOR 615V SUPPLY – Volts
10
160
120
80
40
0
–75
–1
400
Figure 32. Settling Time vs. Output Step
–50
–25
0
25
50
TEMPERATURE – 8C
75
100
125
Figure 34. Input Bias Current vs. Temperature
25
10
VS = 615V
SUPPLY CURRENT – mA
8
INPUT OFFSET CURRENT – nA
TA = +1258C
TA = +258C
TA = –558C
6
4
2
0
0
65
610
615
20
15
10
5
0
–75
620
SUPPLY VOLTAGE – Volts
–50
–25
0
25
50
75
100
125
TEMPERATURE – C
Figure 33. Supply Current vs. Supply Voltage
Figure 35. Input Offset Current vs. Temperature
–10–
REV. C
OP467
effective. On the other hand, ceramic chip capacitors have excellent ESR and ESL (Effective Series Inductance) performance at
higher frequencies, and because of their small size, they can be
placed very close to the device pin, further reducing the stray
inductance. Best results are achieved by using a combination of
these two capacitors. A 5 µF–10 µF tantalum parallel with a
0.1 µF ceramic chip caps are recommended. If additional isolation from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass caps and the power supply. A word of
caution, addition of the ferrite bead will introduce a new pole
and zero to frequency response of the circuit and could cause
unstable operation if it is not selected properly.
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short circuit protected. Shorting the output to
ground or to the supplies may destroy the device.
For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature.
To calculate the maximum internal power dissipation, the following formula can be used:
PD =
TJ
max– TA
θJA
+VS
where TJ and TA are junction and ambient temperatures respectively, PD is device internal power dissipation, and θJA is packaged device thermal resistance given in the data sheet.
+
10mF TANTALUM
0.1mF CERAMIC CHIP
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a quad package
be connected as a unity gain follower with a 1 kΩ feedback
resistor with noninverting input tied to the ground plain.
0.1mF CERAMIC CHIP
–
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
–VS
Satisfactory performance of a high speed op amp largely depends
on a good PC layout. To achieve the best dynamic performance,
following high frequency layout technique is recommended.
GROUNDING
A good ground plain is essential to achieve the optimum performance in high speed applications. It can significantly reduce the
undesirable effects of ground loops and IR drops by providing a
low impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground plain.
To maintain a continuous and low impedance ground, avoid
running any traces on this layer.
POWER SUPPLY CONSIDERATIONS
In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits will cause gain peaking and
additional phase shift, reducing the op amp’s phase margin and
leading to an unstable operation.
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the amplifier’s power
supply rejection.
This is easily done by placing capacitors across the supply line
and the ground plain as close as possible to the device pin. Since
capacitors also have internal parasitic components, such as stray
inductance, selecting the right capacitor is important. To be
effective, they should have low impedance over the frequency
range of interest. Tantalum capacitors are an excellent choice
for their high capacitance/size ratio, but their ESR (Effective
Series Resistance) increases with frequency making them less
Figure 36. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a minimum stray capacitance. Input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance
circuit. Stray capacitance can inject undesirable signals from a
noisy line into a high impedance input. Protect high impedance
input traces by providing guard traces around them. This will
also improve the channel separation significantly.
Additionally, any stray capacitance in parallel with the op amp’s
input capacitance generates a pole in the frequency response of
the circuit. The additional phase shift caused by this pole will
reduce the circuit’s gain margin. If this pole is within the gain
range of the op amp, it will cause unstable performance. To
reduce these undesirable effects, use the lowest impedance
where possible. Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the amplifier. Stray capacitance on the PC board can be reduced by
making the traces narrow and as short as possible. Further reduction can be realized by choosing smaller pad size, increasing
the spacing between the traces, and using PC board material
with a low dielectric constant insulator (Dielectric Constant of
some common insulators: air = 1, Teflon® = 2.2, and FR4 =
4.7; with air being an ideal insulator).
Removing segments of the ground plain directly under the input
and output pads is recommended.
Outputs of high speed amplifiers are very sensitive to capacitive
loads. A capacitive load will introduce a pair of pole and zero to
the circuit’s frequency response, reducing the phase margin,
leading to unstable operation or oscillation.
Teflon is a registered trademark of E.I. du Pont Co.
REV. C
10mF TANTALUM
–11–
OP467
Generally, it is a good design practice to isolate the amplifier’s
output from any capacitive load by placing a resistor between
the amplifier’s output and the rest of the circuits. A series resistor of 10 to 100 ohms is normally sufficient to isolate the output
from a capacitive load.
DLY 4.806ms
100
90
The OP467 is internally compensated to provide stable operation, and is capable of driving large capacitive loads without
oscillation.
10
0%
Sockets are not recommended since they increase the lead inductance/capacitance and reduce the power dissipation of the
package by increasing the leads thermal resistance. If sockets
must be used, use Teflon or pin sockets with the shortest leads
possible.
5V
20ns
Figure 39. Saturation Recovery Time, Negative Rail
HIGH SPEED INSTRUMENTATION AMPLIFIER
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal.
DV1
OUTPUT
5V
The OP467 performance lends itself to a variety of high speed
applications, including high speed precision instrumentation
amplifiers. Figure 40 represents a circuit commonly used for
data acquisition, CCD imaging and other high speed application.
Circuit gain is set by RG. A 2 kΩ resistor will set the circuit gain
to 2; for unity gain, remove RG. For any other gain settings use
the following formula:
15.8V
100
90
G = 2/RG Resistor Value is in kΩ
RC is used for adjusting the dc common-mode rejection, and CC
is used for ac common-mode rejection adjustments.
10
INPUT
0%
–VIN
10V
10V
CC
200ms
2kV
1kV
Figure 37. No Phase Reversal (AV = +1)
RG
SATURATION RECOVERY TIME
10kV
2kV
2kV
OUTPUT
1kV
The OP467 has a fast and symmetrical recovery time from either rail. This feature is very useful in applications such as high
speed instrumentation and measurement circuits, where the
amplifier is frequently exposed to large signals that overload the
amplifier.
1.9kV
10kV
5pF
RC
200V
10T
+VIN
Figure 40. A High Speed Instrumentation Amplifier
DLY 9.842ms
0.01% 10V STEP
VS = 615V
NEG SLOPE
100
90
2.5mV
–2.5mV
10
0%
5V
5V
20ns
Figure 38. Saturation Recovery Time, Positive Rail
Figure 41. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Negative Slope)
–12–
REV. C
OP467
0.01% 10V STEP
VS = 615V
POS SLOPE
2.5mV
–2.5mV
2 MHz BIQUAD BANDPASS FILTER
The circuit in Figure 44 is commonly used in medical imaging
ultrasound receivers. The 30 MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the measured response shows in Figure 45. When the op amp’s bandwidth is too close to the filter’s center frequency, the amplifier’s
internal phase shift causes excess phase shift at 2 MHz, which
alters the filter’s response. In fact, if the chosen op amp has a
bandwidth close to 2 MHz, the combined phase shift of the
three op amps will cause the loop to oscillate.
Careful consideration must be given to the layout of this circuit
as with any other high speed circuit.
Figure 42. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Positive Slope)
If the phase shift introduced by the layout is large enough, it
could alter the circuit performance, or worse, it will oscillate.
R6
1kV
+VS
C1
50pF
+
TO
INPUT
+
2kV
AD9617 1kV
TO
IN-AMP
OUTPUT
2kV
–
R2
2kV
ERROR
TO
SCOPE
R1
3kV
–
–
1/4
OP467
+
2kV
R4
2kV
R3
2kV
–
1/4
OP467
+
1/4
OP467
+
–
–VS
549V
C2
50pF
R5
2kV
–
1/4
OP467
+
VOUT
61.9V
VIN
Figure 43. Settling Time Measurement Circuit
Figure 44. 2 MHz Biquad Filter
0
GAIN – dB
–10
–20
–30
–40
10k
100k
1M
10M
FREQUENCY – Hz
Figure 45. Biquad Filter Response
REV. C
–13–
100M
OP467
+5V
+10V
C1
10pF
VOUTA
1
–
OP467
+
2
3
+15V
0.1mF
1
VDD
2
VREFA
VREFC 27
3
RFBA
RFBC 26
DAC8408
+10V
DGND 28
C3
10pF
4
IOUT 1A
IOUT 1C 25
13
5
IOUT 2A/
IOUT 2B
IOUT 2C/
24
IOUT 2D
12
6
IOUT 1B
IOUT 1D 23
7
RFBB
8
VREFB
9
DB0 (LSB)
DS2 20
+10V
DB1
DS1 19
11 DB2
R/W 18
DIGITAL
CONTROL
SIGNALS
OP467
+
14
VOUTA
OP467
+
8
VOUTB
RFBD 22
9
4
VOUTB
7
–
OP467
11 +
6
5
C2
10pF
+10V
10
VREFD
21
0.1mF
–15V
12 DB3
A/B 17
13 DB4
(MSB) DB7 16
DB5
DB6 15
14
C4
10pF
10
Figure 46. Quad DAC Unipolar Operation
FAST I-TO-V CONVERTER
The fast slew rate and fast settling time of the OP467 are well
suited to the fast buffers and I-to-V converters used in variety of
applications. The circuit in Figure 46 is a unipolar quad D/A
converter consisting of only two ICs. The current output of the
DAC8408 is converted to a voltage by the OP467 configured as
an I-to-V converter. This circuit is capable of settling to 0.1%
within 200 ns. Figures 47 and 48 show the full-scale settling
time of the outputs. To obtain reliable circuit performance, keep
the traces from the DAC’s IOUT to the inverting inputs of the
OP467 short to minimize parasitic capacitance.
251.0ns
100
90
10
0%
2V
100ns
50mV
Figure 48. Voltage Output Settling Time
260.0ns
100
90
DAC-8408
RFB
DC OFFSET
3pF
IOUT
I-V
2kV
2kV
OP467
1kV
50V
AD847
10
0%
604V
2V
50mV
100ns
60.4V
Figure 47. Voltage Output Settling Time
Figure 49. DAC VOUT Settling Time Circuit
–14–
REV. C
OP467
*
* COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
*
ECM
13 98 POLY (2) (1,20) (2,20) 0 0 . 5 0 . 5
R8
13 14 1E6
R9
14 98 25 . 119
C3
13 14 126 . 721E–12
OP467 SPICE MACRO-MODEL
* Node assignments
noninverting input
inverting input
positive supply
negative supply
output
*
. SUBCKT OP467
1
*
* INPUT STAGE
*
I1
4
50
CIN
1
2
IOS
1
2
Q1
5
2
Q2
6
7
R3
99 5
R4
99 6
R5
8
4
R6
9
4
EOS
7
1
EREF
98 0
2
99
50
27
10E–3
1E–12
5E–9
8 QN
9 QN
185 . 681
185 . 681
180 . 508
180 . 508
POLY (1) (14,20) 50E–6
(20,0) 1
1
*
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz
*
R7
10 98 3 . 714E6
C2
10 98 28 . 571E–12
G1
98 10 (5,6) 5 . 386E–3
V1
99 11 1 . 6
V2
12 50 1 . 6
D1
10 11 DX
D2
12 10 DX
RC
10 28 1 . 4E3
CC
28 27 12E–12
*
* POLE AT 400E6
*
R10
15 98
C4
15 98
G2
98 15
1E6
0 . 398E–15
(10,20) 1E–6
*
* OUTPUT STAGE
*
ISY
99 50
RMP1
99 20
RMP2
20 50
RO1
99 26
RO2
26 50
L1
26 27
GO1
26 99
GO2
50 26
G4
23 50
G5
24 50
V3
21 26
V4
26 22
D3
15 21
D4
22 15
D5
99 23
D6
99 24
D7
50 23
D8
50 24
–8 . 183E–3
96 . 429E3
96 . 429E3
200
200
1E–7
(99,15) 5E–3
(15,50) 5E–3
(15,26) 5E–3
(26,15) 5E–3
50
50
DX
DX
DX
DX
DY
DY
*
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467
99
99
99
99
D3
L1
15
24
D7
D8
G5
N+
R5
R6
4
14
13
C2
R8
R9
EREF
98
D2
12
V2
+
–
Figure 50. SPICE Macro-Model Output Stage
R7
G1
ECM
I1
50
50
50
REV. C
C3
–+
EOS
G02
27
9
+
G4
1
R02
8
+
23
CIN
+
EREF
RMP2
7
–
22
IOS
CC
10
–
V4
–+
C4
98
28
26
D4
G2
Q2
Q1
N–
RC
–
R10
2
27
11
D1
6
5
R01
21
R4
R3
G01
V3
+–
20
15
D6
–
ISY
D5
+
V1
RMP1
50
Figure 51. SPICE Macro-Model Input and Gain Stage
–15–
OP467
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip (Y Suffix)
(Q-14)
0.005 (0.13) MIN
14
8
1
7
0.280 (7.11)
0.240 (6.10)
PIN 1
C1759c–0–10/98
14-Lead Plastic DIP (P Suffix)
(N-14)
0.098 (2.49) MAX
14
8
0.310 (7.87)
PIN 1
0.220 (5.59)
0.795 (20.19)
0.725 (18.42)
0.015
(0.381)
MIN
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.92)
0.022 (0.558)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
7
1
0.325 (8.25)
0.300 (7.62)
0.320 (8.13)
0.785 (19.94) MAX
0.200
(5.08)
MAX
0.015 (0.38)
0.008 (0.20)
158
0.200 (5.08)
08
0.125 (3.18)
0.015 (0.38)
0.150
(3.81)
MIN
0.023 (0.58)
0.100
(2.54)
BSC
0.014 (0.36)
16-Lead Wide-Body SOL (S Suffix)
(R-16)
0.008 (0.20)
158
08
0.070 (1.78)
SEATING
PLANE
0.030 (0.76)
20-Terminal Leadless Ceramic Chip Carrier (RC Suffix)
(E-20A)
0.055 (1.40)
0.045 (1.14)
0.2992 (7.60)
0.075 (1.91) REF
88
0.2914 (7.40)
08
1
8
0.3937 (10.00)
0.0500 (1.27 )
BOTTOM
VIEW
0.0157 (0.40 )
0.0291 (0.74 )
0.4133 (10.50)
0.0098 (0.25 )
0.3977 (10.10)
3 458
0.1043 (2.65)
0.040 x 458
0.0926 (2.35)
(1.02 x 458)
REF 3 PLCS
0.0192 (0.49)
0.0125 (0.32)
0.0138 (0.35)
0.0091 (0.23)
NO. 1 PIN INDEX
SEE
DETAIL
ABOVE
0.020 x 458
0.358 (9.09)
0.32 (8.69)
(0.51 x 458)
REF
0.100 (2.54)
0.064 (1.63)
PRINTED IN U.S.A.
0.0500
(1.27)
BSC
0.028 (0.71)
0.022 (0.56)
0.050
(1.27)
BSC
0.4193 (10.65)
PIN 1
0.0040 (0.10)
0.015 (0.38)
9
20
0.0118 (0.30)
0.290 (7.37)
0.060 (1.52)
–16–
REV. C