19-5593; Rev 10/10 DS1330Y/AB 256k Nonvolatile SRAM with Battery Monitor www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Power supply monitor resets processor when VCC power loss occurs and holds processor in reset during VCC ramp-up Battery monitor checks remaining capacity daily Read and write access times of 70ns Unlimited write cycle endurance Typical standby current 50µA Upgrade for 32k x 8 SRAM, EEPROM or Flash Lithium battery is electrically disconnected to retain freshness until power is applied for the first time Full ±10% VCC operating range (DS1330Y) or optional ±5% VCC operating range (DS1330AB) Optional industrial temperature range of -40°C to +85°C, designated IND PowerCap Module (PCM) package - Directly surface-mountable module - Replaceable snap-on PowerCap provides lithium backup battery - Standardized pinout for all nonvolatile (NV) SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver PIN ASSIGNMENT BW NC NC RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GND VBAT 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin POWERCAP MODULE (PCM) (Uses DS9034PC+ or DS9034PCI+ PowerCap) PIN DESCRIPTION A0 – A14 DQ0 – DQ7 CE WE OE RST BW VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Reset Output - Battery Warning - Power (+5V) - Ground - No Connect DESCRIPTION The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Additionally, the DS1330 devices have dedicated circuitry for monitoring the status of VCC and the status of the internal lithium battery. DS1330 devices in the PowerCap module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete NV SRAM module. The devices can be used in place of 32k x 8 SRAM, EEPROM, or Flash components. 1 of 10 DS1330Y/AB READ MODE The DS1330 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1330 devices execute a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1330AB provides full-functional capability for VCC greater than 4.75V and write protects by 4.5V. The DS1330Y provides full-functional capability for VCC greater than 4.5V and write protects by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV SRAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75V for the DS1330AB and 4.5V for the DS1330Y. SYSTEM POWER MONITORING DS1330 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance power supply condition is detected, the NV SRAMs warn a processor-based system of impending power failure by asserting RST . On power-up, RST is held active for 200ms nominal to prevent system operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver. BATTERY MONITORING The DS1330 devices automatically perform periodic battery voltage monitoring on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced. The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing resumes. BW has an open drain output driver. 2 of 10 DS1330Y/AB PACKAGES The 34-pin PowerCap module integrates SRAM memory and NV control along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design allows a DS1330 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. After a DS1330 PCM is reflow soldered, a DS9034PC is snapped on top of the PCM to form a complete NV SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1330 PowerCap modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information. 3 of 10 DS1330Y/AB ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Commercial: Industrial: Storage Temperature Range Lead Temperature (soldering, 10s) Soldering Temperature (reflow) -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C +260°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER DS1330AB Power Supply Voltage (TA: See Note 10) SYMBOL VCC MIN 4.75 TYP 5.0 MAX 5.25 UNITS V DS1330Y Power Supply Voltage VCC 4.5 5.0 5.5 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 0.8 V NOTES DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5% for DS1330AB) (TA: See Note 10) (VCC = 5V ± 10% for DS1330Y) PARAMETER Input Leakage Current SYMBOL IIL MIN -1.0 TYP MAX +1.0 UNITS +1.0 µA I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 Output Current @ 2.4V IOH -1.0 mA 14 Output Current @ 0.4V IOL 2.0 mA 14 µA Standby Current CE =2.2V ICCS1 200 600 µA Standby Current CE =VCC-0.5V ICCS2 50 150 µA Operating Current ICCO1 85 mA Write Protection Voltage (DS1330AB) VTP 4.50 4.62 4.75 V Write Protection Voltage (DS1330Y) VTP 4.25 4.37 4.5 V 4 of 10 NOTES DS1330Y/AB CAPACITANCE (TA = +25°C) PARAMETER Input Capacitance SYMBOL CIN Input/Output Capacitance MIN CI/O TYP 5 MAX 10 UNITS pF 5 10 pF NOTES AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5% for DS1330AB) (TA: See Note 10) (VCC = 5V ± 10% for DS1330Y) PARAMETER DS1330AB-70 DS1330Y-70 SYMBOL MIN 70 UNITS MAX Read Cycle Time tRC Access Time tACC 70 ns OE to Output Valid tOE 45 ns CE to Output Valid tCO 70 ns OE or CE to Output Active tCOE Output High Z from Deselection Output Hold from Address Change tOD tOH 5 ns Write Cycle Time tWC 70 ns Write Pulse Width tWP 55 ns Address Setup Time tAW tWR1 tWR2 0 5 12 ns Write Recovery Time NOTES ns 5 25 5 ns 5 3 ns 12 13 ns 5 Output High Z from WE tODW Output Active from WE tOEW 5 ns 5 Data Setup Time tDS tDH1 tDH2 30 0 7 ns 4 12 13 Data Hold Time 25 ns READ CYCLE SEE NOTE 1 5 of 10 ns DS1330Y/AB WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13 6 of 10 DS1330Y/AB POWER-DOWN/POWER-UP CONDITION BATTERY WARNING DETECTION 7 of 10 DS1330Y/AB POWER-DOWN/POWER-UP TIMING PARAMETER (TA: See Note 10) SYMBOL VCC Fail Detect to CE and WE Inactive tPD VCC slew from VTP to 0V tF VCC Fail Detect to RST Active MIN TYP MAX UNITS NOTES 1.5 µs 11 µs 150 tRPD 15 µs 14 µs VCC slew from 0V to VTP tR 150 VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms VCC Valid to RST Inactive tRPU 350 ms 14 VCC Valid to BW Valid tBPU 1 s 14 150 200 BATTERY WARNING TIMING PARAMETER (TA: See Note 10) SYMBOL MIN TYP MAX Battery Test Cycle tBTC Battery Test Pulse Width tBTPW 1 s tBW 1 s Battery Test to BW Active 24 UNITS NOTES hr (TA = +25°C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 8 of 10 DS1330Y/AB 9. Each DS1330 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to +70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. RST and BW are open drain outputs and cannot source current. External pull-up resistors should be connected to these pins for proper operation. Both pins will sink 10mA. 15. DS1330 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Cycle = 200ns for operating current All voltages are referenced to ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 – 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5ns ORDERING INFORMATION PART DS1330ABP-70+ DS1330ABP-70IND+ DS1330YP-70+ DS1330YP-70IND+ SUPPLY TOLERANCE 5V ± 5% 5V ± 5% 5V ± 10% 5V ± 10% TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 34 PCAP* 34 PCAP* 34 PCAP* 34 PCAP* +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. LAND PACKAGE TYPE PACKAGE CODE OUTLINE NO. PATTERN NO. 34 PCAP PC2+4 — 21-0246 9 of 10 DS1330Y/AB REVISION HISTORY REVISION DESCRIPTION DATE Updated the storage, lead, and soldering information in the Absolute Maximum Ratings section, removed the unused AC timing specs in the AC Electrical Characteristics table, updated the Ordering 10/10 Information table, replaced the package outline drawing with the Package Information table 10 of 10 PAGES CHANGED 1, 4, 5, 9